[llvm] [X86][AVX] Fix handling of out-of-bounds shift amounts in AVX2 vector logical shift nodes #83840 (PR #86922)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 10 03:25:11 PDT 2024
================
@@ -47701,12 +47725,31 @@ static SDValue combineShiftToPMULH(SDNode *N, SelectionDAG &DAG,
return DAG.getNode(ExtOpc, DL, VT, Mulh);
}
-static SDValue combineShiftLeft(SDNode *N, SelectionDAG &DAG) {
+static SDValue combineShiftLeft(SDNode *N, SelectionDAG &DAG,
+ const X86Subtarget &Subtarget) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
EVT VT = N0.getValueType();
+ // Exploits AVX2 VSHLV/VSRLV instructions for efficient unsigned vector shifts
+ // with out-of-bounds clamping.
+ if (N0.getOpcode() == ISD::VSELECT &&
+ supportedVectorVarShift(VT, Subtarget, ISD::SHL)) {
+ SDValue Cond = N0.getOperand(0);
+ SDValue N00 = N0.getOperand(1);
+ SDValue N01 = N0.getOperand(2);
+ APInt SV;
+ if (Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == N1 &&
----------------
RKSimon wrote:
Add a description comment:
```
// fold shl(select(icmp_ult(amt,BW),x,0),amt) -> avx2 psllv(x,amt)
```
https://github.com/llvm/llvm-project/pull/86922
More information about the llvm-commits
mailing list