[llvm] [RISCV][GISEL] Do not initialize GlobalISel objects unless needed (PR #98233)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 9 16:26:26 PDT 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/98233
>From 6a2766ee621669e7329898facf4523b3d2719b05 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 9 Jul 2024 16:11:18 -0700
Subject: [PATCH 1/2] [GISel] Make create.*InstructionSelector arguments const
The InstructionSelector takes `const` arguments.
---
.../Target/AArch64/GISel/AArch64InstructionSelector.cpp | 4 ++--
llvm/lib/Target/Mips/MipsInstructionSelector.cpp | 7 ++++---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 4 ++--
llvm/lib/Target/RISCV/RISCV.h | 7 ++++---
llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp | 4 ++--
5 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 9e0860934f777..1ff8a7e32a156 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -7790,8 +7790,8 @@ void AArch64InstructionSelector::processPHIs(MachineFunction &MF) {
namespace llvm {
InstructionSelector *
createAArch64InstructionSelector(const AArch64TargetMachine &TM,
- AArch64Subtarget &Subtarget,
- AArch64RegisterBankInfo &RBI) {
+ const AArch64Subtarget &Subtarget,
+ const AArch64RegisterBankInfo &RBI) {
return new AArch64InstructionSelector(TM, Subtarget, RBI);
}
}
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index 4e1e27088cce4..332749165a3ff 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -927,9 +927,10 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
}
namespace llvm {
-InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &TM,
- MipsSubtarget &Subtarget,
- MipsRegisterBankInfo &RBI) {
+InstructionSelector *
+createMipsInstructionSelector(const MipsTargetMachine &TM,
+ const MipsSubtarget &Subtarget,
+ const MipsRegisterBankInfo &RBI) {
return new MipsInstructionSelector(TM, Subtarget, RBI);
}
} // end namespace llvm
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index f511a20109803..fdb1ebace0010 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -1330,8 +1330,8 @@ void RISCVInstructionSelector::emitFence(AtomicOrdering FenceOrdering,
namespace llvm {
InstructionSelector *
createRISCVInstructionSelector(const RISCVTargetMachine &TM,
- RISCVSubtarget &Subtarget,
- RISCVRegisterBankInfo &RBI) {
+ const RISCVSubtarget &Subtarget,
+ const RISCVRegisterBankInfo &RBI) {
return new RISCVInstructionSelector(TM, Subtarget, RBI);
}
} // end namespace llvm
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 8d2e1fc340c3e..27a432b818312 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -79,9 +79,10 @@ void initializeRISCVMoveMergePass(PassRegistry &);
FunctionPass *createRISCVPushPopOptimizationPass();
void initializeRISCVPushPopOptPass(PassRegistry &);
-InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
- RISCVSubtarget &,
- RISCVRegisterBankInfo &);
+InstructionSelector *
+createRISCVInstructionSelector(const RISCVTargetMachine &,
+ const RISCVSubtarget &,
+ const RISCVRegisterBankInfo &);
void initializeRISCVDAGToDAGISelLegacyPass(PassRegistry &);
FunctionPass *createRISCVPostLegalizerCombiner();
diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
index d73873812eeb6..2fb499122fbbf 100644
--- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
@@ -1871,7 +1871,7 @@ bool X86InstructionSelector::selectSelect(MachineInstr &I,
InstructionSelector *
llvm::createX86InstructionSelector(const X86TargetMachine &TM,
- X86Subtarget &Subtarget,
- X86RegisterBankInfo &RBI) {
+ const X86Subtarget &Subtarget,
+ const X86RegisterBankInfo &RBI) {
return new X86InstructionSelector(TM, Subtarget, RBI);
}
>From 1d1a442f022c3d68170b1a169cd3d9cd1f695bee Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 9 Jul 2024 15:16:24 -0700
Subject: [PATCH 2/2] [RISCV][GISEL] Do not initialize GlobalISel objects
unless needed
Prior to this commit, we created the GlobalISel objects in the
RISCVSubtarget constructor, even if we are not running GlobalISel. This
patch moves creation of the GlobalISel objects into their getters, which
ensures that we only create these objects if they are actually needed.
This helps since the constructors of the GlobalISel objects have a
significant amount of code.
We make the `unique_ptr`s `mutable` since GlobalISel passes only have
access to `const TargetSubtargetInfo` through `MF.getSubtarget()`.
This patch is tested by the fact that all existing RISC-V GlobalISel
tests remain passing.
---
llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 21 ++++++++++++---------
llvm/lib/Target/RISCV/RISCVSubtarget.h | 8 ++++----
2 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index e84ddc65e2b70..d8414623d302b 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -97,29 +97,32 @@ RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
RVVVectorBitsMin(RVVVectorBitsMin), RVVVectorBitsMax(RVVVectorBitsMax),
FrameLowering(
initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
- InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
- CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
- Legalizer.reset(new RISCVLegalizerInfo(*this));
-
- auto *RBI = new RISCVRegisterBankInfo(getHwMode());
- RegBankInfo.reset(RBI);
- InstSelector.reset(createRISCVInstructionSelector(
- *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
-}
+ InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {}
const CallLowering *RISCVSubtarget::getCallLowering() const {
+ if (!CallLoweringInfo)
+ CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
return CallLoweringInfo.get();
}
InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
+ if (!InstSelector) {
+ InstSelector.reset(createRISCVInstructionSelector(
+ *static_cast<const RISCVTargetMachine *>(&TLInfo.getTargetMachine()),
+ *this, *static_cast<const RISCVRegisterBankInfo *>(getRegBankInfo())));
+ }
return InstSelector.get();
}
const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
+ if (!Legalizer)
+ Legalizer.reset(new RISCVLegalizerInfo(*this));
return Legalizer.get();
}
const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
+ if (!RegBankInfo)
+ RegBankInfo.reset(new RISCVRegisterBankInfo(getHwMode()));
return RegBankInfo.get();
}
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 347c1bc3c278f..b146f48f81b72 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -245,10 +245,10 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
protected:
// GlobalISel related APIs.
- std::unique_ptr<CallLowering> CallLoweringInfo;
- std::unique_ptr<InstructionSelector> InstSelector;
- std::unique_ptr<LegalizerInfo> Legalizer;
- std::unique_ptr<RegisterBankInfo> RegBankInfo;
+ mutable std::unique_ptr<CallLowering> CallLoweringInfo;
+ mutable std::unique_ptr<InstructionSelector> InstSelector;
+ mutable std::unique_ptr<LegalizerInfo> Legalizer;
+ mutable std::unique_ptr<RegisterBankInfo> RegBankInfo;
// Return the known range for the bit length of RVV data registers as set
// at the command line. A value of 0 means nothing is known about that particular
More information about the llvm-commits
mailing list