[llvm] [GISel] Make create.*InstructionSelector arguments const (PR #98243)

[Michael Maitland via llvm-commits]

https://github.com/michaelmaitland created https://github.com/llvm/llvm-project/pull/98243

The InstructionSelector objects all take these arguments in as `const`. This function does not modify the object. Therefore we can mark them as `const` here.

>From 6a2766ee621669e7329898facf4523b3d2719b05 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 9 Jul 2024 16:11:18 -0700
Subject: [PATCH] [GISel] Make create.*InstructionSelector arguments const

The InstructionSelector takes `const` arguments.
---
 .../Target/AArch64/GISel/AArch64InstructionSelector.cpp    | 4 ++--
 llvm/lib/Target/Mips/MipsInstructionSelector.cpp           | 7 ++++---
 llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp   | 4 ++--
 llvm/lib/Target/RISCV/RISCV.h                              | 7 ++++---
 llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp       | 4 ++--
 5 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 9e0860934f777..1ff8a7e32a156 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -7790,8 +7790,8 @@ void AArch64InstructionSelector::processPHIs(MachineFunction &MF) {
 namespace llvm {
 InstructionSelector *
 createAArch64InstructionSelector(const AArch64TargetMachine &TM,
-                                 AArch64Subtarget &Subtarget,
-                                 AArch64RegisterBankInfo &RBI) {
+                                 const AArch64Subtarget &Subtarget,
+                                 const AArch64RegisterBankInfo &RBI) {
   return new AArch64InstructionSelector(TM, Subtarget, RBI);
 }
 }
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index 4e1e27088cce4..332749165a3ff 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -927,9 +927,10 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
 }
 
 namespace llvm {
-InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &TM,
-                                                   MipsSubtarget &Subtarget,
-                                                   MipsRegisterBankInfo &RBI) {
+InstructionSelector *
+createMipsInstructionSelector(const MipsTargetMachine &TM,
+                              const MipsSubtarget &Subtarget,
+                              const MipsRegisterBankInfo &RBI) {
   return new MipsInstructionSelector(TM, Subtarget, RBI);
 }
 } // end namespace llvm
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index f511a20109803..fdb1ebace0010 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -1330,8 +1330,8 @@ void RISCVInstructionSelector::emitFence(AtomicOrdering FenceOrdering,
 namespace llvm {
 InstructionSelector *
 createRISCVInstructionSelector(const RISCVTargetMachine &TM,
-                               RISCVSubtarget &Subtarget,
-                               RISCVRegisterBankInfo &RBI) {
+                               const RISCVSubtarget &Subtarget,
+                               const RISCVRegisterBankInfo &RBI) {
   return new RISCVInstructionSelector(TM, Subtarget, RBI);
 }
 } // end namespace llvm
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 8d2e1fc340c3e..27a432b818312 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -79,9 +79,10 @@ void initializeRISCVMoveMergePass(PassRegistry &);
 FunctionPass *createRISCVPushPopOptimizationPass();
 void initializeRISCVPushPopOptPass(PassRegistry &);
 
-InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
-                                                    RISCVSubtarget &,
-                                                    RISCVRegisterBankInfo &);
+InstructionSelector *
+createRISCVInstructionSelector(const RISCVTargetMachine &,
+                               const RISCVSubtarget &,
+                               const RISCVRegisterBankInfo &);
 void initializeRISCVDAGToDAGISelLegacyPass(PassRegistry &);
 
 FunctionPass *createRISCVPostLegalizerCombiner();
diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
index d73873812eeb6..2fb499122fbbf 100644
--- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
@@ -1871,7 +1871,7 @@ bool X86InstructionSelector::selectSelect(MachineInstr &I,
 
 InstructionSelector *
 llvm::createX86InstructionSelector(const X86TargetMachine &TM,
-                                   X86Subtarget &Subtarget,
-                                   X86RegisterBankInfo &RBI) {
+                                   const X86Subtarget &Subtarget,
+                                   const X86RegisterBankInfo &RBI) {
   return new X86InstructionSelector(TM, Subtarget, RBI);
 }