[llvm] [RISCV][NFC] Remove unused getSelectionDAGInfo (PR #98172)

Michael Maitland via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 9 08:29:09 PDT 2024


https://github.com/michaelmaitland created https://github.com/llvm/llvm-project/pull/98172

None

>From e9685f118f891f8d2e903b6ca53e7729df41d6d6 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 9 Jul 2024 08:26:44 -0700
Subject: [PATCH] [RISCV][NFC] Remove unused getSelectionDAGInfo

---
 llvm/lib/Target/RISCV/RISCVSubtarget.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 347c1bc3c278f..67ec2de1847df 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -86,7 +86,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   RISCVInstrInfo InstrInfo;
   RISCVRegisterInfo RegInfo;
   RISCVTargetLowering TLInfo;
-  SelectionDAGTargetInfo TSInfo;
 
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
@@ -116,9 +115,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   const RISCVTargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
-  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
-    return &TSInfo;
-  }
   bool enableMachineScheduler() const override { return true; }
 
   bool enablePostRAScheduler() const override { return UsePostRAScheduler; }



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