[llvm] [RISCV] Use VP strided load in concat_vectors combine (PR #98131)

[Luke Lau via llvm-commits]

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@@ -9,9 +9,9 @@
 define void @widen_2xv4i16(ptr %x, ptr %z) {
 ; CHECK-LABEL: widen_2xv4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    vse16.v v8, (a1)
+; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
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lukel97 wrote:

The combine checks for the alignment with `TLI.isLegalStridedLoadStore(WideVecVT, Align)`, so I think this should be fine. This is what it was originally combining to anyway, the generic dag combine was just re-combining it smaller SEW

https://github.com/llvm/llvm-project/pull/98131