[llvm] [RISCV] Fix 0-offset aliases for compressed sp-based opcodes (PR #98034)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mc

@llvm/pr-subscribers-backend-risc-v

Author: R (ArcaneNibble)

<details>
<summary>Changes</summary>

The "26.3.1. Stack-Pointer-Based Loads and Stores" compressed opcodes have access to all registers (except x0). Fix the opcode aliases with 0 offset so that the aliases also work for all registers, not only the RVC registers.

Previously, LLVM would accept e.g. `c.lwsp x8, (sp)` but not e.g. `c.lwsp x18, (sp)`, even though e.g. `c.lwsp x18, 0(sp)` would be accepted.

This was noticed while implementing https://github.com/llvm/llvm-project/pull/97925 . The implementation in that other PR is indeed correct (i.e `qk.c.lhusp` et al are restricted to the RVC registers).

---
Full diff: https://github.com/llvm/llvm-project/pull/98034.diff


5 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoC.td (+8-8) 
- (modified) llvm/test/MC/RISCV/rv32fc-aliases-valid.s (+4) 
- (modified) llvm/test/MC/RISCV/rv64c-aliases-valid.s (+4) 
- (modified) llvm/test/MC/RISCV/rvc-aliases-valid.s (+4) 
- (modified) llvm/test/MC/RISCV/rvdc-aliases-valid.s (+4) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 458d081763e931..7385879c063c75 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -716,29 +716,29 @@ let EmitPriority = 0 in {
 let Predicates = [HasStdExtCOrZca] in {
 def : InstAlias<"c.lw $rd, (${rs1})", (C_LW GPRC:$rd, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.sw $rs2, (${rs1})", (C_SW GPRC:$rs2, GPRCMem:$rs1, 0)>;
-def : InstAlias<"c.lwsp $rd, (${rs1})", (C_LWSP GPRC:$rd, SPMem:$rs1, 0)>;
-def : InstAlias<"c.swsp $rs2, (${rs1})", (C_SWSP GPRC:$rs2, SPMem:$rs1, 0)>;
+def : InstAlias<"c.lwsp $rd, (${rs1})", (C_LWSP GPRNoX0:$rd, SPMem:$rs1, 0)>;
+def : InstAlias<"c.swsp $rs2, (${rs1})", (C_SWSP GPRNoX0:$rs2, SPMem:$rs1, 0)>;
 }
 
 let Predicates = [HasStdExtCOrZca, IsRV64] in {
 def : InstAlias<"c.ld $rd, (${rs1})", (C_LD GPRC:$rd, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.sd $rs2, (${rs1})", (C_SD GPRC:$rs2, GPRCMem:$rs1, 0)>;
-def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRC:$rd, SPMem:$rs1, 0)>;
-def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPRC:$rs2, SPMem:$rs1, 0)>;
+def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRNoX0:$rd, SPMem:$rs1, 0)>;
+def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPRNoX0:$rs2, SPMem:$rs1, 0)>;
 }
 
 let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
 def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRCMem:$rs1, 0)>;
-def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32C:$rd, SPMem:$rs1, 0)>;
-def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32C:$rs2, SPMem:$rs1, 0)>;
+def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32:$rd, SPMem:$rs1, 0)>;
+def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32:$rs2, SPMem:$rs1, 0)>;
 }
 
 let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
 def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRCMem:$rs1, 0)>;
-def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64C:$rd, SPMem:$rs1, 0)>;
-def : InstAlias<"c.fsdsp $rs2, (${rs1})", (C_FSDSP FPR64C:$rs2, SPMem:$rs1, 0)>;
+def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64:$rd, SPMem:$rs1, 0)>;
+def : InstAlias<"c.fsdsp $rs2, (${rs1})", (C_FSDSP FPR64:$rs2, SPMem:$rs1, 0)>;
 }
 } // EmitPriority = 0
 
diff --git a/llvm/test/MC/RISCV/rv32fc-aliases-valid.s b/llvm/test/MC/RISCV/rv32fc-aliases-valid.s
index 596b865f826dfb..d992d07ec677eb 100644
--- a/llvm/test/MC/RISCV/rv32fc-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv32fc-aliases-valid.s
@@ -12,3 +12,7 @@ c.fsw f8, (x9)
 c.flwsp f8, (x2)
 # CHECK-EXPAND: c.fswsp fs0, 0(sp)
 c.fswsp f8, (x2)
+# CHECK-EXPAND: c.flwsp fs2, 0(sp)
+c.flwsp f18, (x2)
+# CHECK-EXPAND: c.fswsp fs2, 0(sp)
+c.fswsp f18, (x2)
diff --git a/llvm/test/MC/RISCV/rv64c-aliases-valid.s b/llvm/test/MC/RISCV/rv64c-aliases-valid.s
index 92fcf337bb797d..ccf9e6a4fc2dd1 100644
--- a/llvm/test/MC/RISCV/rv64c-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv64c-aliases-valid.s
@@ -108,3 +108,7 @@ c.sd x8, (x9)
 c.ldsp x8, (x2)
 # CHECK-EXPAND: c.sdsp s0, 0(sp)
 c.sdsp x8, (x2)
+# CHECK-EXPAND: c.ldsp s2, 0(sp)
+c.ldsp x18, (x2)
+# CHECK-EXPAND: c.sdsp s2, 0(sp)
+c.sdsp x18, (x2)
diff --git a/llvm/test/MC/RISCV/rvc-aliases-valid.s b/llvm/test/MC/RISCV/rvc-aliases-valid.s
index e72b0bbac678fe..fa73922e80ecf0 100644
--- a/llvm/test/MC/RISCV/rvc-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvc-aliases-valid.s
@@ -17,3 +17,7 @@ c.sw x8, (x9)
 c.lwsp x8, (x2)
 # CHECK-EXPAND: c.swsp s0, 0(sp)
 c.swsp x8, (x2)
+# CHECK-EXPAND: c.lwsp s2, 0(sp)
+c.lwsp x18, (x2)
+# CHECK-EXPAND: c.swsp s2, 0(sp)
+c.swsp x18, (x2)
diff --git a/llvm/test/MC/RISCV/rvdc-aliases-valid.s b/llvm/test/MC/RISCV/rvdc-aliases-valid.s
index c2a727af4ee190..f74ee05575d53f 100644
--- a/llvm/test/MC/RISCV/rvdc-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvdc-aliases-valid.s
@@ -16,3 +16,7 @@ c.fsd f8, (x9)
 c.fldsp f8, (x2)
 # CHECK-EXPAND: c.fsdsp fs0, 0(sp)
 c.fsdsp f8, (x2)
+# CHECK-EXPAND: c.fldsp fs2, 0(sp)
+c.fldsp f18, (x2)
+# CHECK-EXPAND: c.fsdsp fs2, 0(sp)
+c.fsdsp f18, (x2)

``````````

</details>


https://github.com/llvm/llvm-project/pull/98034