[llvm] [AArch64] Lower for power of 2 signed divides with scalar type (PR #97879)
David Sherwood via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 8 01:41:49 PDT 2024
================
@@ -17544,13 +17544,14 @@ AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
SmallVectorImpl<SDNode *> &Created) const {
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
if (isIntDivCheap(N->getValueType(0), Attr))
- return SDValue(N,0); // Lower SDIV as SDIV
+ return SDValue(N, 0); // Lower SDIV as SDIV
EVT VT = N->getValueType(0);
// For scalable and fixed types, mark them as cheap so we can handle it much
// later. This allows us to handle larger than legal types.
- if (VT.isScalableVector() || Subtarget->useSVEForFixedLengthVectors())
+ if (VT.isScalableVector() ||
+ (!VT.isScalarInteger() && Subtarget->useSVEForFixedLengthVectors()))
----------------
david-arm wrote:
So I had a fix for #97821 downstream as well and I believe here you actually want something like:
```
if (VT.isScalableVector() ||
(VT.isFixedLengthVector() && Subtarget->useSVEForFixedLengthVectors())
```
since it's not obvious to me that `!VT.isScalarInteger()` is equivalent to `VT.isFixedLengthVector()`.
https://github.com/llvm/llvm-project/pull/97879
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