[llvm] [AArch64] Add support for missing AArch64 opcodes in `AArch64InstrInfo::getMemOpInfo` (PR #97954)

[Romain Thomas via llvm-commits]

romainthomas wrote:

> Some of these are being added in #97561

Thanks for pointing out this PR. In the end, feel free to merge my PR into yours 
if it makes more sense to have one single PR for these updates.

> But from what I can tell with different widths and limits

After checking your PR, I can also see the differences. 

For instance, you define `STRWpre` as:

https://github.com/llvm/llvm-project/blob/1422591dbea2d03ab386f3fd098648cd697bf9da/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp#L3681-L3686

But according to `llvm-mc` it follows this encoding:

```
str     w8, [x1, #32]! // encoding: [0x28,0x0c,0x02,0xb8]
                       // <MCInst #6847 STRWpre
                       //  <MCOperand Reg:236>
                       //  <MCOperand Reg:212>
                       //  <MCOperand Reg:236>
                       //  <MCOperand Imm:32>>
```

Thus, in my understanding, the `Scale` should be 1 and the Width `4` ?  

Regarding, the `Width` for the instructions that load/store pair of registers, 
I understand the `Width` as twice the size of the register being stored/loaded 
so `LDPSpre` should be `2 * 4` and not only `4`?


```
ldp     s15, s11, [x3, #-0x40]! // encoding: [0x6f,0x2c,0xf8,0x2d]
                                // <MCInst #4424 LDPSpre
                                //  <MCOperand Reg:238>
                                //  <MCOperand Reg:187>
                                //  <MCOperand Reg:183>
                                //  <MCOperand Reg:238>
                                //  <MCOperand Imm:-16>>
```                              

https://github.com/llvm/llvm-project/blob/1422591dbea2d03ab386f3fd098648cd697bf9da/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp#L3858-L3870


Note that my updates are coming from a manual analysis of the MC encoding.

https://github.com/llvm/llvm-project/pull/97954