[llvm] [RISCV] Add QingKe "XW" compressed opcode extension (PR #97925)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,188 @@
+//===-- RISCVInstrInfoXwch.td ------------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extension(s) defined by WCH.
+//
+//===----------------------------------------------------------------------===//
+
+class QK_Stack<bits<2> funct2, dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+  bits<3> rd_rs2;
+
+  let Inst{15-11} = 0b10000;
+  let Inst{6-5} = funct2;
+  let Inst{4-2} = rd_rs2;
+  let Inst{1-0} = 0b00;
+}
+
+//===----------------------------------------------------------------------===//
+// Operand definitions.
+//===----------------------------------------------------------------------===//
+
+def uimm4_with_predicate : RISCVUImmLeafOp<4> {
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isUInt<4>(Imm);
+  }];
+}
+
+def uimm5_with_predicate : RISCVUImmLeafOp<5> {
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isUInt<5>(Imm);
+  }];
+}
+
+// A 5-bit unsigned immediate where the least significant bit is zero.
+def uimm5_lsb0 : RISCVOp,
+                 ImmLeaf<XLenVT, [{return isShiftedUInt<4, 1>(Imm);}]> {
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topperc wrote:

You can drop the ImmLeaf if isn't used by CodeGen.

https://github.com/llvm/llvm-project/pull/97925