[llvm] [RISCV] Add QingKe "XW" compressed opcode extension (PR #97925)

[via llvm-commits]

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@@ -371,6 +371,9 @@ The current vendor extensions supported are:
 ``XSfcease``
   LLVM implements `the SiFive sf.cease instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
 
+``Xwchc``
+  LLVM implements `the custom compressed opcodes present in some QingKe cores` by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes by the name "XW".
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ArcaneNibble wrote:

I don't believe there is a proper specification. I initially reverse-engineered the encoding from the vendor binary toolchain. @wangpc-pp later emailed the vendor who confirmed the encoding as correct ( https://discourse.llvm.org/t/rfc-supporting-wch-qingke-xw-compressed-opcodes/79392/12?u=arcanenibble )

https://github.com/llvm/llvm-project/pull/97925