[llvm] [AArch64] Lower for power of 2 signed divides with scalar type (PR #97879)

[via llvm-commits]

https://github.com/vfdff created https://github.com/llvm/llvm-project/pull/97879

Expected same assemble for code which doesn't use sve registers when we compile it with/without -msve-vector-bits=256.

Fix https://github.com/llvm/llvm-project/issues/97821

>From e6650da0561180a1d40384422e526f5910a4b568 Mon Sep 17 00:00:00 2001
From: zhongyunde 00443407 <zhongyunde at huawei.com>
Date: Sat, 6 Jul 2024 02:10:50 -0400
Subject: [PATCH] [AArch64][SVE] Lower for power of 2 signed divides with
 scalar type

Expected same assemble for code which doesn't use sve registers
when we compile it with/without -msve-vector-bits=256.

Fix https://github.com/llvm/llvm-project/issues/97821
---
 llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |  5 +++--
 .../AArch64/sve-fixed-length-sdiv-pow2.ll       | 17 +++++++++++++++++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 9f6f66e9e0c70f..f072c9a9b21781 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17544,13 +17544,14 @@ AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
                                      SmallVectorImpl<SDNode *> &Created) const {
   AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
   if (isIntDivCheap(N->getValueType(0), Attr))
-    return SDValue(N,0); // Lower SDIV as SDIV
+    return SDValue(N, 0); // Lower SDIV as SDIV
 
   EVT VT = N->getValueType(0);
 
   // For scalable and fixed types, mark them as cheap so we can handle it much
   // later. This allows us to handle larger than legal types.
-  if (VT.isScalableVector() || Subtarget->useSVEForFixedLengthVectors())
+  if (VT.isScalableVector() ||
+      (!VT.isScalarInteger() && Subtarget->useSVEForFixedLengthVectors()))
     return SDValue(N, 0);
 
   // fold (sdiv X, pow2)
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
index 21a5abdeaa4d53..46c5ec375721c8 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
@@ -383,4 +383,21 @@ define void @sdiv_v32i64(ptr %a) vscale_range(16,0) #0 {
   ret void
 }
 
+define i32 @sdiv_int(i32 %begin, i32 %first) #0 {
+; CHECK-LABEL: sdiv_int:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub w8, w0, w1
+; CHECK-NEXT:    add w9, w8, #1
+; CHECK-NEXT:    add w10, w8, #2
+; CHECK-NEXT:    cmp w9, #0
+; CHECK-NEXT:    csinc w8, w10, w8, lt
+; CHECK-NEXT:    sub w0, w0, w8, asr #1
+; CHECK-NEXT:    ret
+  %sub = add i32 %begin, 1
+  %add = sub i32 %sub, %first
+  %div.neg = sdiv i32 %add, -2
+  %sub1 = add i32 %div.neg, %begin
+  ret i32 %sub1
+}
+
 attributes #0 = { "target-features"="+sve" }