[compiler-rt] [llvm] [compiler-rt][X86] Better unify ProcessorFeatures and X86TargetPraser (PR #97856)

Aiden Grossman via llvm-commits llvm-commits at lists.llvm.org
Fri Jul 5 18:50:10 PDT 2024


https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/97856

>From 1d0935ca48226d4825f6e005ebbc9e1df2d8cc2e Mon Sep 17 00:00:00 2001
From: Aiden Grossman <aidengrossman at google.com>
Date: Fri, 5 Jul 2024 20:01:30 +0000
Subject: [PATCH 1/2] [compiler-rt][X86] Better unify ProcessorFeatures and
 X86TargetPraser

compiler-rt's ProcessorFeatures and the definitions in X86TargetParser
need to be kpet in sync to ensure correct functionality. Currently there
are quite a few differences between the two (not currently impacting
functionality). These have primarily stemmed from updates made on the
LLVM side that did not touch the compiler-rt side (like the removal of
the knights landing features). This patch attempts to rectify the
situation and better unify the structs.
---
 compiler-rt/lib/builtins/cpu_model/x86.c       | 17 ++++++-----------
 .../llvm/TargetParser/X86TargetParser.def      |  6 +++---
 llvm/lib/TargetParser/X86TargetParser.cpp      | 18 +++++++++---------
 3 files changed, 18 insertions(+), 23 deletions(-)

diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c
index 7e8acb3e73eda9..5dbb1004d0fda4 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -125,8 +125,8 @@ enum ProcessorFeatures {
   FEATURE_AVX512BW,
   FEATURE_AVX512DQ,
   FEATURE_AVX512CD,
-  FEATURE_AVX512ER,
-  FEATURE_AVX512PF,
+  FEATURE_NF,
+  FEATURE_CF,
   FEATURE_AVX512VBMI,
   FEATURE_AVX512IFMA,
   FEATURE_AVX5124VNNIW,
@@ -142,7 +142,7 @@ enum ProcessorFeatures {
   // FIXME: Below Features has some missings comparing to gcc, it's because gcc
   // has some not one-to-one mapped in llvm.
   FEATURE_3DNOW,
-  // FEATURE_3DNOWP,
+  // FEATURE_3DNOWA,
   FEATURE_ADX = 40,
   // FEATURE_ABM,
   FEATURE_CLDEMOTE = 42,
@@ -171,7 +171,7 @@ enum ProcessorFeatures {
   // FEATURE_OSXSAVE,
   FEATURE_PCONFIG = 63,
   FEATURE_PKU,
-  FEATURE_PREFETCHWT1,
+  FEATURE_EVEX512,
   FEATURE_PRFCHW,
   FEATURE_PTWRITE,
   FEATURE_RDPID,
@@ -205,6 +205,7 @@ enum ProcessorFeatures {
   FEATURE_X86_64_V2,
   FEATURE_X86_64_V3,
   FEATURE_X86_64_V4,
+  FEATURE_APXF,
   FEATURE_AVXIFMA,
   FEATURE_AVXVNNIINT8,
   FEATURE_AVXNECONVERT,
@@ -217,7 +218,7 @@ enum ProcessorFeatures {
   FEATURE_SM3,
   FEATURE_SHA512,
   FEATURE_SM4,
-  FEATURE_APXF,
+  FEATUE_EGPR,
   FEATURE_USERMSR,
   FEATURE_AVX10_1_256,
   FEATURE_AVX10_1_512,
@@ -870,10 +871,6 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
     setFeature(FEATURE_AVX512IFMA);
   if (HasLeaf7 && ((EBX >> 24) & 1))
     setFeature(FEATURE_CLWB);
-  if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
-    setFeature(FEATURE_AVX512PF);
-  if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
-    setFeature(FEATURE_AVX512ER);
   if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
     setFeature(FEATURE_AVX512CD);
   if (HasLeaf7 && ((EBX >> 29) & 1))
@@ -883,8 +880,6 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
   if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
     setFeature(FEATURE_AVX512VL);
 
-  if (HasLeaf7 && ((ECX >> 0) & 1))
-    setFeature(FEATURE_PREFETCHWT1);
   if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
     setFeature(FEATURE_AVX512VBMI);
   if (HasLeaf7 && ((ECX >> 4) & 1))
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def
index 0e4ad873e36391..3fb901fccbd658 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -191,7 +191,7 @@ X86_FEATURE_COMPAT(FSGSBASE,        "fsgsbase",               0)
 X86_FEATURE       (CRC32,           "crc32")
 X86_FEATURE       (INVPCID,         "invpcid")
 X86_FEATURE       (RDPRU,           "rdpru")
-X86_FEATURE       (SAHF,            "sahf")
+X86_FEATURE       (LAHF_LM,         "sahf")
 X86_FEATURE       (VZEROUPPER,      "vzeroupper")
 X86_FEATURE_COMPAT(LWP,             "lwp",                    0)
 X86_FEATURE_COMPAT(LZCNT,           "lzcnt",                  0)
@@ -250,7 +250,7 @@ X86_FEATURE_COMPAT(SHA512,          "sha512",                 0)
 X86_FEATURE_COMPAT(SM4,             "sm4",                    0)
 X86_FEATURE       (EGPR,            "egpr")
 X86_FEATURE_COMPAT(USERMSR,         "usermsr",                0)
-X86_FEATURE_COMPAT(AVX10_1,         "avx10.1-256",           36)
+X86_FEATURE_COMPAT(AVX10_1_256,     "avx10.1-256",           36)
 X86_FEATURE_COMPAT(AVX10_1_512,     "avx10.1-512",           37)
 X86_FEATURE       (ZU,              "zu")
 // These features aren't really CPU features, but the frontend can set them.
@@ -264,7 +264,7 @@ X86_MICROARCH_LEVEL(X86_64_BASELINE,"x86-64",               95)
 X86_MICROARCH_LEVEL(X86_64_V2,      "x86-64-v2",            96)
 X86_MICROARCH_LEVEL(X86_64_V3,      "x86-64-v3",            97)
 X86_MICROARCH_LEVEL(X86_64_V4,      "x86-64-v4",            98)
-X86_MICROARCH_LEVEL(APXF,           "apxf",                111)
+X86_MICROARCH_LEVEL(APXF,           "apxf",                 99)
 #undef X86_FEATURE_COMPAT
 #undef X86_FEATURE
 #undef X86_MICROARCH_LEVEL
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index 141ecb936b7084..a5d0fa953979a4 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -66,7 +66,7 @@ constexpr FeatureBitset FeaturesNocona =
 
 // Basic 64-bit capable CPU.
 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
-constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
+constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureLAHF_LM |
                                             FeaturePOPCNT | FeatureCRC32 |
                                             FeatureSSE4_2 | FeatureCMPXCHG16B;
 constexpr FeatureBitset FeaturesX86_64_V3 =
@@ -78,7 +78,7 @@ constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 | FeatureEVEX512 |
 
 // Intel Core CPUs
 constexpr FeatureBitset FeaturesCore2 =
-    FeaturesNocona | FeatureSAHF | FeatureSSSE3;
+    FeaturesNocona | FeatureLAHF_LM | FeatureSSSE3;
 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
 constexpr FeatureBitset FeaturesNehalem =
     FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2;
@@ -186,14 +186,14 @@ constexpr FeatureBitset FeaturesK8 =
 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
 constexpr FeatureBitset FeaturesAMDFAM10 =
     FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
-    FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
+    FeaturePRFCHW | FeatureLAHF_LM | FeatureSSE4_A;
 
 // Bobcat architecture processors.
 constexpr FeatureBitset FeaturesBTVER1 =
     FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
     FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
-    FeatureSAHF;
+    FeatureLAHF_LM;
 constexpr FeatureBitset FeaturesBTVER2 =
     FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 |
     FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
@@ -203,7 +203,7 @@ constexpr FeatureBitset FeaturesBDVER1 =
     FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
     FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 |
     FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
-    FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
+    FeaturePOPCNT | FeaturePRFCHW | FeatureLAHF_LM | FeatureSSE | FeatureSSE2 |
     FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A |
     FeatureXOP | FeatureXSAVE;
 constexpr FeatureBitset FeaturesBDVER2 =
@@ -221,7 +221,7 @@ constexpr FeatureBitset FeaturesZNVER1 =
     FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
     FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
     FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
-    FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
+    FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureLAHF_LM | FeatureSHA |
     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
     FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
     FeatureXSAVEOPT | FeatureXSAVES;
@@ -507,7 +507,7 @@ constexpr FeatureBitset ImpliedFeaturesRDPRU = {};
 constexpr FeatureBitset ImpliedFeaturesRDRND = {};
 constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
 constexpr FeatureBitset ImpliedFeaturesRTM = {};
-constexpr FeatureBitset ImpliedFeaturesSAHF = {};
+constexpr FeatureBitset ImpliedFeaturesLAHF_LM = {};
 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
 constexpr FeatureBitset ImpliedFeaturesSGX = {};
 constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
@@ -615,13 +615,13 @@ constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
 
 // AVX10 Features
-constexpr FeatureBitset ImpliedFeaturesAVX10_1 =
+constexpr FeatureBitset ImpliedFeaturesAVX10_1_256 =
     FeatureAVX512CD | FeatureAVX512VBMI | FeatureAVX512IFMA |
     FeatureAVX512VNNI | FeatureAVX512BF16 | FeatureAVX512VPOPCNTDQ |
     FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureVAES | FeatureVPCLMULQDQ |
     FeatureAVX512FP16;
 constexpr FeatureBitset ImpliedFeaturesAVX10_1_512 =
-    FeatureAVX10_1 | FeatureEVEX512;
+    FeatureAVX10_1_256 | FeatureEVEX512;
 
 // APX Features
 constexpr FeatureBitset ImpliedFeaturesEGPR = {};

>From bc5ec931ccc3833192fac26322ea8bf6662285ae Mon Sep 17 00:00:00 2001
From: Aiden Grossman <aidengrossman at google.com>
Date: Sat, 6 Jul 2024 01:49:56 +0000
Subject: [PATCH 2/2] Rename VZEROUPPER

---
 llvm/include/llvm/TargetParser/X86TargetParser.def | 2 +-
 llvm/lib/TargetParser/X86TargetParser.cpp          | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def
index 3fb901fccbd658..21628ed9697c2c 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -192,7 +192,7 @@ X86_FEATURE       (CRC32,           "crc32")
 X86_FEATURE       (INVPCID,         "invpcid")
 X86_FEATURE       (RDPRU,           "rdpru")
 X86_FEATURE       (LAHF_LM,         "sahf")
-X86_FEATURE       (VZEROUPPER,      "vzeroupper")
+X86_FEATURE       (LM,              "lm")
 X86_FEATURE_COMPAT(LWP,             "lwp",                    0)
 X86_FEATURE_COMPAT(LZCNT,           "lzcnt",                  0)
 X86_FEATURE_COMPAT(MOVBE,           "movbe",                  0)
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index a5d0fa953979a4..07e85d3a8f4a85 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -508,6 +508,7 @@ constexpr FeatureBitset ImpliedFeaturesRDRND = {};
 constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
 constexpr FeatureBitset ImpliedFeaturesRTM = {};
 constexpr FeatureBitset ImpliedFeaturesLAHF_LM = {};
+constexpr FeatureBitset ImpliedFeaturesLM = {};
 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
 constexpr FeatureBitset ImpliedFeaturesSGX = {};
 constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
@@ -517,7 +518,6 @@ constexpr FeatureBitset ImpliedFeaturesUINTR = {};
 constexpr FeatureBitset ImpliedFeaturesUSERMSR = {};
 constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
 constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
-constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
 constexpr FeatureBitset ImpliedFeaturesX87 = {};
 constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
 



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