[llvm] [RISCV] vsetvl pseudo may cross inline asm without sideeffect (PR #97794)

[Luke Lau via llvm-commits]

lukel97 wrote:

Does the inline assembly need to model somehow that it uses `vl` and `vtype`? Marking them as clobbered seems to fix it for me (although I don't think it's the same as an input)

```llvm
define void @foo(<vscale x 8 x half> %0, <vscale x 8 x half> %1) {
entry:
  %2 = tail call i64 @llvm.riscv.vsetvli.i64(i64 3000, i64 0, i64 0)
  %3 = tail call <vscale x 8 x float> asm sideeffect "vfmadd.vv $0, $1, $2", "=^vr,^vr,^vr,0,~{vl},~{vtype}"(<vscale x 8 x float> zeroinitializer, <vscale x 8 x float> zeroinitializer, <vscale x 8 x float> zeroinitializer)
  %4 = tail call <vscale x 8 x float> asm sideeffect "vfmadd.vv $0, $1, $2", "=^vr,^vr,^vr,0,~{vl},~{vtype}"(<vscale x 8 x float> zeroinitializer, <vscale x 8 x float> zeroinitializer, <vscale x 8 x float> %3)
  tail call void @llvm.riscv.vse.nxv8f16.i64(<vscale x 8 x half> %0, ptr null, i64 %2)
  ret void
}
```

Not opposed to adding back the side effect if we need to keep real world code working though. I guess I'm surprised that the machine scheduler would move asm with side effects past an implicit-def.

https://github.com/llvm/llvm-project/pull/97794