[llvm] [RISCV] Lower unmasked zero-stride vp.stride to a splat of one scalar load. (PR #97394)

[Luke Lau via llvm-commits]

lukel97 wrote:

I gave this a try and it is possible to replace the strided intrinsics, PoC here: https://github.com/llvm/llvm-project/compare/main...lukel97:llvm-project:remove-riscv-masked-strided-intrinsics

The two main prerequsities were that we need to make `RISCVDAGToDAGISel::performCombineVMergeAndVOps` slightly smarter (#78565), and detect VLMAX EVL operands when lowering VP nodes to VL nodes

https://github.com/llvm/llvm-project/pull/97394