[llvm] [AArch64][PAC] Lower jump-tables using hardened pseudo. (PR #97666)
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Wed Jul 3 20:22:05 PDT 2024
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``````````bash
git-clang-format --diff 507b0f6714ec94e286d8c1ef16f871e1b1564426 6b7eb51ee224e3419103b0484570c985250faaf1 -- llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 79d3f7e386..fc05f0e826 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -1401,9 +1401,9 @@ void AArch64AsmPrinter::LowerHardenedBRJumpTable(const MachineInstr &MI) {
MCInstLowering.lowerOperand(JTMOHi, JTMCHi);
MCInstLowering.lowerOperand(JTMOLo, JTMCLo);
- EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::ADRP)
- .addReg(AArch64::X17)
- .addOperand(JTMCHi));
+ EmitToStreamer(
+ *OutStreamer,
+ MCInstBuilder(AArch64::ADRP).addReg(AArch64::X17).addOperand(JTMCHi));
++InstsEmitted;
EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::ADDXri)
@@ -1413,7 +1413,6 @@ void AArch64AsmPrinter::LowerHardenedBRJumpTable(const MachineInstr &MI) {
.addImm(0));
++InstsEmitted;
-
EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::LDRSWroX)
.addReg(AArch64::X16)
.addReg(AArch64::X17)
@@ -1427,9 +1426,9 @@ void AArch64AsmPrinter::LowerHardenedBRJumpTable(const MachineInstr &MI) {
AArch64FI->setJumpTableEntryInfo(JTI, 4, AdrLabel);
OutStreamer->emitLabel(AdrLabel);
- EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::ADR)
- .addReg(AArch64::X17)
- .addExpr(AdrLabelE));
+ EmitToStreamer(
+ *OutStreamer,
+ MCInstBuilder(AArch64::ADR).addReg(AArch64::X17).addExpr(AdrLabelE));
++InstsEmitted;
EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::ADDXrs)
@@ -1439,14 +1438,12 @@ void AArch64AsmPrinter::LowerHardenedBRJumpTable(const MachineInstr &MI) {
.addImm(0));
++InstsEmitted;
- EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::BR)
- .addReg(AArch64::X16));
+ EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::BR).addReg(AArch64::X16));
++InstsEmitted;
assert(STI->getInstrInfo()->getInstSizeInBytes(MI) >= InstsEmitted * 4);
}
-
void AArch64AsmPrinter::LowerMOPS(llvm::MCStreamer &OutStreamer,
const llvm::MachineInstr &MI) {
unsigned Opcode = MI.getOpcode();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 4248c7e8d6..eb6c2dfdc3 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -10680,8 +10680,8 @@ SDValue AArch64TargetLowering::LowerBR_JT(SDValue Op,
// With jump-table-hardening, we only expand the full jump table dispatch
// sequence later, to guarantee the integrity of the intermediate values.
- if (DAG.getMachineFunction().getFunction()
- .hasFnAttribute("jump-table-hardening") ||
+ if (DAG.getMachineFunction().getFunction().hasFnAttribute(
+ "jump-table-hardening") ||
Subtarget->getTargetTriple().isArm64e()) {
assert(Subtarget->isTargetMachO() &&
"hardened jump-table not yet supported on non-macho");
``````````
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https://github.com/llvm/llvm-project/pull/97666
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