[llvm] Add extended mnemonics (PR #97571)
Dominik Steenken via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 3 06:03:57 PDT 2024
https://github.com/dominik-steenken created https://github.com/llvm/llvm-project/pull/97571
This PR adds a number of thus-far missing extended mnemonics to the assembler and disassembler for SystemZ.
The following mnemonics have been added and are supported for the assembler and disassembler:
- `NOP(R)?`
- `LFI`
- `RISBG(N)?Z`
- `R(N|O|X)SBG(T)?`
- `(N|O|X)HHR`
- `(N|O|X)HLR`
- `(N|O|X)LHR`
The following mnemonics have been added and are supported for the assembler only:
- `JC(TH)?`
- `LLG(F|H)I`
- `NOT(G)?R`
>From ba695e18eff8683f6e030a2d87d202927e8d2f03 Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Wed, 3 Jul 2024 11:25:09 +0200
Subject: [PATCH 1/5] [SystemZ] Support Disassembly of NOP and NOPR This is
accomplished by two additional instruction formats, representing conditional
branch instructions whose condition is never true.
---
llvm/lib/Target/SystemZ/SystemZInstrFormats.td | 13 +++++++++++++
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 11 ++++++++---
llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 6 ++++++
llvm/lib/Target/SystemZ/SystemZScheduleZ14.td | 6 ++++++
llvm/lib/Target/SystemZ/SystemZScheduleZ15.td | 5 +++++
llvm/lib/Target/SystemZ/SystemZScheduleZ16.td | 5 +++++
llvm/lib/Target/SystemZ/SystemZScheduleZ196.td | 5 +++++
llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td | 5 +++++
llvm/test/MC/Disassembler/SystemZ/insns.txt | 17 ++++++++++-------
llvm/test/MC/SystemZ/insn-good.s | 6 +++---
10 files changed, 66 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 3dba33b66bf4f..1f6f5ef72dd3d 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -2349,6 +2349,12 @@ class AsmCondBranchRR<string mnemonic, bits<8> opcode>
: InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
mnemonic#"\t$R1, $R2", []>;
+class NeverCondBranchRR<string mnemonic, bits<8> opcode>
+ : InstRR<opcode, (outs), (ins GR64:$R2),
+ mnemonic#"\t$R2", []> {
+ let R1 = 0;
+}
+
class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
SDPatternOperator operator = null_frag>
: InstRR<opcode, (outs), (ins ADDR64:$R2),
@@ -2370,6 +2376,13 @@ class AsmCondBranchRX<string mnemonic, bits<8> opcode>
(ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$M1, $XBD2", []>;
+class NeverCondBranchRX<string mnemonic, bits<8> opcode>
+ : InstRXb<opcode, (outs),
+ (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ mnemonic#"\t$XBD2", []> {
+ let M1 = 0;
+}
+
class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
: InstRXb<opcode, (outs), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
!subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 7c6ab3f9b1ab5..9f078ec636b34 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -111,11 +111,16 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
// NOPs. These are again variants of the conditional branches, with the
// condition mask set to "never". NOP_bare can't be an InstAlias since it
// would need R0D hard coded which is not part of ADDR64BitRegClass.
-def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>;
+def NOP : NeverCondBranchRX<"nop", 0x47>;
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in
def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>;
-def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>;
-def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>;
+def NOPR : NeverCondBranchRR<"nopr", 0x07>;
+def NOPR_bare : InstAlias<"nopr", (NOPR R0D), 0>;
+// def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>;
+// let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in
+// def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>;
+// def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>;
+// def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>;
// An alias of BRC 0, label
def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>;
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
index 9ce1a0d06b5af..e80eb2e78816d 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -1553,5 +1553,11 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
+
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
index 120d4a457ee39..66d85f7e108a3 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
@@ -1643,5 +1643,11 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
+
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
index acba3a1fd9919..1e667b06cfa37 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
@@ -1689,5 +1689,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
index dd82b2b9b71e7..b1230f6047027 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
@@ -1722,5 +1722,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
index 226db9d4272f9..43cbb490585b3 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -1235,5 +1235,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, LSU, EndGroup], (instregex "NOP(R)?$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
index f5ecdb1f43800..19066229c91d9 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -1280,5 +1280,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, LSU, NormalGr], (instregex "NOP(R)?$")>;
}
diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt
index 23714dfc3a8e6..529b25e226de6 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt
@@ -1315,22 +1315,22 @@
# CHECK: bassm %r15, %r1
0x0c 0xf1
-# CHECK: bc 0, 0
+# CHECK: nop 0
0x47 0x00 0x00 0x00
-# CHECK: bc 0, 4095
+# CHECK: nop 4095
0x47 0x00 0x0f 0xff
-# CHECK: bc 0, 0(%r1)
+# CHECK: nop 0(%r1)
0x47 0x00 0x10 0x00
-# CHECK: bc 0, 0(%r15)
+# CHECK: nop 0(%r15)
0x47 0x00 0xf0 0x00
-# CHECK: bc 0, 4095(%r1,%r15)
+# CHECK: nop 4095(%r1,%r15)
0x47 0x01 0xff 0xff
-# CHECK: bc 0, 4095(%r15,%r1)
+# CHECK: nop 4095(%r15,%r1)
0x47 0x0f 0x1f 0xff
# CHECK: bo 0(%r13)
@@ -1375,9 +1375,12 @@
# CHECK: bno 0
0x47 0xe0 0x00 0x00
-# CHECK: bcr 0, %r14
+# CHECK: nopr %r14
0x07 0x0e
+# CHECK: nopr %r7
+0x07 0x07
+
# CHECK: bor %r13
0x07 0x1d
diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s
index 2add4a108319e..9f6b11eba3343 100644
--- a/llvm/test/MC/SystemZ/insn-good.s
+++ b/llvm/test/MC/SystemZ/insn-good.s
@@ -13122,10 +13122,10 @@
niy 524287(%r1), 42
niy 524287(%r15), 42
-#CHECK: bc 0, 0 # encoding: [0x47,0x00,0x00,0x00]
+#CHECK: nop 0 # encoding: [0x47,0x00,0x00,0x00]
#CHECK: nop # encoding: [0x47,0x00,0x00,0x00]
-#CHECK: bcr 0, %r7 # encoding: [0x07,0x07]
-#CHECK: bcr 0, %r0 # encoding: [0x07,0x00]
+#CHECK: nopr %r7 # encoding: [0x07,0x07]
+#CHECK: nopr %r0 # encoding: [0x07,0x00]
nop 0
nop
>From 5c3fe99dc0513d44a72547f61006af58279e8c7a Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Wed, 3 Jul 2024 12:42:46 +0200
Subject: [PATCH 2/5] [SystemZ] Add missing instruction / mnemonic aliases This
adds aliases JC, JCTH, LFI, LLGFI and LLGHI
---
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 5 +++++
llvm/test/MC/SystemZ/insn-good-z196.s | 3 +++
llvm/test/MC/SystemZ/insn-good.s | 9 +++++++++
3 files changed, 17 insertions(+)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 9f078ec636b34..59ad8dc06da79 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -469,6 +469,8 @@ let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
}
+def LLGFI : InstAlias<"llgfi\t$R1, $RI1",(LLILF GR64:$R1, imm64lf32:$RI1)>;
+def LLGHI : InstAlias<"llghi\t$R1, $RI1",(LLILL GR64:$R1, imm64ll16:$RI1)>;
// Register loads.
let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {
@@ -978,6 +980,7 @@ let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;
}
+def LFI : InstAlias<"lfi\t$R1, $RI1",(IILF GR32:$R1, uimm32:$RI1)>;
def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;
@@ -2335,6 +2338,8 @@ defm : BlockLoadStore<load, i64, MVCImm, NCImm, OCImm, XCImm, 7>;
def JCT : MnemonicAlias<"jct", "brct">;
def JCTG : MnemonicAlias<"jctg", "brctg">;
+def JC : MnemonicAlias<"jc", "brc">;
+def JCTH : MnemonicAlias<"jcth", "brcth">;
def JAS : MnemonicAlias<"jas", "bras">;
def JASL : MnemonicAlias<"jasl", "brasl">;
def JXH : MnemonicAlias<"jxh", "brxh">;
diff --git a/llvm/test/MC/SystemZ/insn-good-z196.s b/llvm/test/MC/SystemZ/insn-good-z196.s
index fc90b18e66d8f..d2a7724d3a9a2 100644
--- a/llvm/test/MC/SystemZ/insn-good-z196.s
+++ b/llvm/test/MC/SystemZ/insn-good-z196.s
@@ -276,10 +276,13 @@
#CHECK: brcth %r7, frob at PLT # encoding: [0xcc,0x76,A,A,A,A]
# fixup A - offset: 2, value: frob at PLT+2, kind: FK_390_PC32DBL
#CHECK: brcth %r8, frob at PLT # encoding: [0xcc,0x86,A,A,A,A]
+# fixup A - offset: 2, value: frob at PLT+2, kind: FK_390_PC32DBL
+#CHECK: brcth %r8, frob at PLT # encoding: [0xcc,0x86,A,A,A,A]
# fixup A - offset: 2, value: frob at PLT+2, kind: FK_390_PC32DBL
brcth %r7,frob at PLT
brcth %r8,frob at PLT
+ jcth %r8,frob at PLT
#CHECK: cdfbra %f0, 0, %r0, 0 # encoding: [0xb3,0x95,0x00,0x00]
#CHECK: cdfbra %f0, 0, %r0, 15 # encoding: [0xb3,0x95,0x0f,0x00]
diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s
index 9f6b11eba3343..957222109b389 100644
--- a/llvm/test/MC/SystemZ/insn-good.s
+++ b/llvm/test/MC/SystemZ/insn-good.s
@@ -1441,6 +1441,8 @@
jo foo
bro foo
+#CHECK: brc 2, foo # encoding: [0xa7,0x24,A,A]
+#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL
#CHECK: brc 2, foo # encoding: [0xa7,0x24,A,A]
#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL
#CHECK: jh foo # encoding: [0xa7,0x24,A,A]
@@ -1452,6 +1454,7 @@
#CHECK: jp foo # encoding: [0xa7,0x24,A,A]
#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL
brc 2, foo
+ jc 2, foo
jh foo
jp foo
brh foo
@@ -8694,11 +8697,13 @@
#CHECK: iilf %r0, 0 # encoding: [0xc0,0x09,0x00,0x00,0x00,0x00]
#CHECK: iilf %r0, 4294967295 # encoding: [0xc0,0x09,0xff,0xff,0xff,0xff]
+#CHECK: iilf %r15, 0 # encoding: [0xc0,0xf9,0x00,0x00,0x00,0x00]
#CHECK: iilf %r15, 0 # encoding: [0xc0,0xf9,0x00,0x00,0x00,0x00]
iilf %r0, 0
iilf %r0, 0xffffffff
iilf %r15, 0
+ lfi %r15, 0
#CHECK: iilh %r0, 0 # encoding: [0xa5,0x02,0x00,0x00]
#CHECK: iilh %r0, 32768 # encoding: [0xa5,0x02,0x80,0x00]
@@ -10307,11 +10312,13 @@
#CHECK: llihf %r0, 0 # encoding: [0xc0,0x0e,0x00,0x00,0x00,0x00]
#CHECK: llihf %r0, 4294967295 # encoding: [0xc0,0x0e,0xff,0xff,0xff,0xff]
+#CHECK: llihf %r15, 0 # encoding: [0xc0,0xfe,0x00,0x00,0x00,0x00]
#CHECK: llihf %r15, 0 # encoding: [0xc0,0xfe,0x00,0x00,0x00,0x00]
llihf %r0, 0
llihf %r0, 0xffffffff
llihf %r15, 0
+ llghi %r15, 0
#CHECK: llihh %r0, 0 # encoding: [0xa5,0x0c,0x00,0x00]
#CHECK: llihh %r0, 32768 # encoding: [0xa5,0x0c,0x80,0x00]
@@ -10335,11 +10342,13 @@
#CHECK: llilf %r0, 0 # encoding: [0xc0,0x0f,0x00,0x00,0x00,0x00]
#CHECK: llilf %r0, 4294967295 # encoding: [0xc0,0x0f,0xff,0xff,0xff,0xff]
+#CHECK: llilf %r15, 0 # encoding: [0xc0,0xff,0x00,0x00,0x00,0x00]
#CHECK: llilf %r15, 0 # encoding: [0xc0,0xff,0x00,0x00,0x00,0x00]
llilf %r0, 0
llilf %r0, 0xffffffff
llilf %r15, 0
+ llgfi %r15, 0
#CHECK: llilh %r0, 0 # encoding: [0xa5,0x0e,0x00,0x00]
#CHECK: llilh %r0, 32768 # encoding: [0xa5,0x0e,0x80,0x00]
>From 8b5bc22f5ce58cf153cbeecbb5152a70e5024d3b Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Wed, 3 Jul 2024 12:46:39 +0200
Subject: [PATCH 3/5] [SystemZ] Add NOTR and NOTGR for the AsmParser only This
necessitates a new InstructionFormat (UnaryRRFa). The instructions are not
made available for the disassembler because distinguishing their encoding
from encodings of other instructions (NORK and NOGRK) requires a check on the
register choice (R2 == R3) that, to my knowledge, the disassembler is
currently not capable of.
---
llvm/lib/Target/SystemZ/SystemZInstrFormats.td | 13 +++++++++++++
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 4 ++++
llvm/lib/Target/SystemZ/SystemZScheduleZ15.td | 1 +
llvm/lib/Target/SystemZ/SystemZScheduleZ16.td | 1 +
llvm/test/MC/SystemZ/insn-good-z15.s | 4 ++++
5 files changed, 23 insertions(+)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 1f6f5ef72dd3d..cac79f6f234f7 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -3452,6 +3452,19 @@ class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
let OpType = "reg";
}
+
+class UnaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+ RegisterOperand cls1, RegisterOperand cls2>
+ : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls2:$R3),
+ mnemonic#"\t$R1, $R2",
+ [(set cls1:$R1, (operator cls2:$R2, cls2:$R3))]> {
+ let R3 = R2;
+ let M4 = 0;
+ let OpKey = mnemonic#cls1;
+ let OpType = "reg";
+}
+
+
multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
SDPatternOperator operator, RegisterOperand cls1,
RegisterOperand cls2> {
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 59ad8dc06da79..21cdfd5deff7e 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -1380,6 +1380,10 @@ let Predicates = [FeatureMiscellaneousExtensions3],
let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>;
def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>;
+ let isAsmParserOnly = 1 in {
+ def NOTR : UnaryRRFa<"notr", 0xB976, nor, GR32, GR32>;
+ def NOTGR : UnaryRRFa<"notgr", 0xB966, nor, GR64, GR64>;
+ }
}
// NXOR.
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
index 1e667b06cfa37..f19df310e6599 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
@@ -471,6 +471,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "NC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NN(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NO(G)?RK$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "NOT(G)?R$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NX(G)?RK$")>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
index b1230f6047027..c6fec335ebb33 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
@@ -471,6 +471,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "NC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NN(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NO(G)?RK$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "NOT(G)?R$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NX(G)?RK$")>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/SystemZ/insn-good-z15.s b/llvm/test/MC/SystemZ/insn-good-z15.s
index 36476161ea46d..108f842116231 100644
--- a/llvm/test/MC/SystemZ/insn-good-z15.s
+++ b/llvm/test/MC/SystemZ/insn-good-z15.s
@@ -146,24 +146,28 @@
#CHECK: nogrk %r0, %r15, %r0 # encoding: [0xb9,0x66,0x00,0x0f]
#CHECK: nogrk %r15, %r0, %r0 # encoding: [0xb9,0x66,0x00,0xf0]
#CHECK: nogrk %r7, %r8, %r9 # encoding: [0xb9,0x66,0x90,0x78]
+#CHECK: notgr %r7, %r8 # encoding: [0xb9,0x66,0x80,0x78]
nogrk %r0,%r0,%r0
nogrk %r0,%r0,%r15
nogrk %r0,%r15,%r0
nogrk %r15,%r0,%r0
nogrk %r7,%r8,%r9
+ notgr %r7,%r8
#CHECK: nork %r0, %r0, %r0 # encoding: [0xb9,0x76,0x00,0x00]
#CHECK: nork %r0, %r0, %r15 # encoding: [0xb9,0x76,0xf0,0x00]
#CHECK: nork %r0, %r15, %r0 # encoding: [0xb9,0x76,0x00,0x0f]
#CHECK: nork %r15, %r0, %r0 # encoding: [0xb9,0x76,0x00,0xf0]
#CHECK: nork %r7, %r8, %r9 # encoding: [0xb9,0x76,0x90,0x78]
+#CHECK: notr %r7, %r8 # encoding: [0xb9,0x76,0x80,0x78]
nork %r0,%r0,%r0
nork %r0,%r0,%r15
nork %r0,%r15,%r0
nork %r15,%r0,%r0
nork %r7,%r8,%r9
+ notr %r7,%r8
#CHECK: nxgrk %r0, %r0, %r0 # encoding: [0xb9,0x67,0x00,0x00]
#CHECK: nxgrk %r0, %r0, %r15 # encoding: [0xb9,0x67,0xf0,0x00]
>From 673e6d7edcbb02ae80077dc559a4773a9678c739 Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Wed, 3 Jul 2024 13:02:49 +0200
Subject: [PATCH 4/5] [SystemZ] Introduce handling of T and Z bits for the
RIE-f instruction format Also add two extended mnemonics that use this
feature, RISBGZ and RISBGNZ. T and Z bit handling are provided by extending
the RIE-f format with two optional `bits<8>` parameters that OR their content
onto the I3 and I4 fields. Setting these to `0x80` ensures that the highest
bit of I3 or I4 will be set, thus setting the T or Z bit, respectively.
---
.../lib/Target/SystemZ/SystemZInstrFormats.td | 24 +++++++++++++++----
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 8 +++++--
llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 2 +-
llvm/lib/Target/SystemZ/SystemZScheduleZ14.td | 2 +-
llvm/lib/Target/SystemZ/SystemZScheduleZ15.td | 2 +-
llvm/lib/Target/SystemZ/SystemZScheduleZ16.td | 2 +-
.../lib/Target/SystemZ/SystemZScheduleZ196.td | 2 +-
.../Target/SystemZ/SystemZScheduleZEC12.td | 2 +-
llvm/test/MC/Disassembler/SystemZ/insns.txt | 22 ++++++++++-------
llvm/test/MC/SystemZ/insn-good-zEC12.s | 14 ++++++++++-
llvm/test/MC/SystemZ/insn-good.s | 14 ++++++++++-
11 files changed, 71 insertions(+), 23 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index cac79f6f234f7..878f1d6377c50 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -363,7 +363,7 @@ class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{7-0} = op{7-0};
}
-class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, bits<8> I3Or = 0, bits<8> I4Or = 0>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
@@ -377,8 +377,22 @@ class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = R2;
- let Inst{31-24} = I3;
- let Inst{23-16} = I4;
+ let Inst{31} = !if(I3Or{7}, 1, I3{7});
+ let Inst{30} = !if(I3Or{6}, 1, I3{6});
+ let Inst{29} = !if(I3Or{5}, 1, I3{5});
+ let Inst{28} = !if(I3Or{4}, 1, I3{4});
+ let Inst{27} = !if(I3Or{3}, 1, I3{3});
+ let Inst{26} = !if(I3Or{2}, 1, I3{2});
+ let Inst{25} = !if(I3Or{1}, 1, I3{1});
+ let Inst{24} = !if(I3Or{0}, 1, I3{0});
+ let Inst{23} = !if(I4Or{7}, 1, I4{7});
+ let Inst{22} = !if(I4Or{6}, 1, I4{6});
+ let Inst{21} = !if(I4Or{5}, 1, I4{5});
+ let Inst{20} = !if(I4Or{4}, 1, I4{4});
+ let Inst{19} = !if(I4Or{3}, 1, I4{3});
+ let Inst{18} = !if(I4Or{2}, 1, I4{2});
+ let Inst{17} = !if(I4Or{1}, 1, I4{1});
+ let Inst{16} = !if(I4Or{0}, 1, I4{0});
let Inst{15-8} = I5;
let Inst{7-0} = op{7-0};
}
@@ -5025,11 +5039,11 @@ multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
}
class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
- RegisterOperand cls2>
+ RegisterOperand cls2, bits<8> I3Or = 0, bits<8> I4Or = 0>
: InstRIEf<opcode, (outs cls1:$R1),
(ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
imm32zx8:$I5),
- mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
+ mnemonic#"\t$R1, $R2, $I3, $I4, $I5", [], I3Or, I4Or> {
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
}
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 21cdfd5deff7e..4b540d61312b5 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -1538,13 +1538,17 @@ def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>;
let Defs = [CC] in {
let isCodeGenOnly = 1 in
def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
- let CCValues = 0xE, CompareZeroCCMask = 0xE in
+ let CCValues = 0xE, CompareZeroCCMask = 0xE in {
def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
+ def RISBGZ : RotateSelectRIEf<"risbgz", 0xEC55, GR64, GR64, 0, 128>;
+ }
}
// On zEC12 we have a variant of RISBG that does not set CC.
-let Predicates = [FeatureMiscellaneousExtensions] in
+let Predicates = [FeatureMiscellaneousExtensions] in {
def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>;
+ def RISBGNZ : RotateSelectRIEf<"risbgnz", 0xEC59, GR64, GR64, 0, 128>;
+}
// Forms of RISBG that only affect one word of the destination register.
// They do not set CC.
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
index e80eb2e78816d..d0fec02777875 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -506,9 +506,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
index 66d85f7e108a3..a6d89ce9443c5 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
@@ -516,9 +516,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
index f19df310e6599..455354e283ad8 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
@@ -531,9 +531,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
index c6fec335ebb33..92abf0ba4022c 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
@@ -531,9 +531,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
index 43cbb490585b3..99d0d674bbbb2 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -469,9 +469,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(32)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(32)?(Z)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
index 19066229c91d9..5b334da2bac34 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -480,9 +480,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt
index 529b25e226de6..392993d4e2a36 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt
@@ -13971,11 +13971,11 @@
# CHECK: risbg %r0, %r0, 0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x55
-# CHECK: risbg %r0, %r0, 0, 0, 63
-0xec 0x00 0x00 0x00 0x3f 0x55
+# CHECK: risbg %r0, %r0, 0, 0, 255
+0xec 0x00 0x00 0x00 0xff 0x55
-# CHECK: risbg %r0, %r0, 0, 255, 0
-0xec 0x00 0x00 0xff 0x00 0x55
+# CHECK: risbg %r0, %r0, 0, 127, 0
+0xec 0x00 0x00 0x7f 0x00 0x55
# CHECK: risbg %r0, %r0, 255, 0, 0
0xec 0x00 0xff 0x00 0x00 0x55
@@ -13989,14 +13989,17 @@
# CHECK: risbg %r4, %r5, 6, 7, 8
0xec 0x45 0x06 0x07 0x08 0x55
+# CHECK: risbgz %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x87 0x08 0x55
+
# CHECK: risbgn %r0, %r0, 0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x59
-# CHECK: risbgn %r0, %r0, 0, 0, 63
-0xec 0x00 0x00 0x00 0x3f 0x59
+# CHECK: risbgn %r0, %r0, 0, 0, 255
+0xec 0x00 0x00 0x00 0xff 0x59
-# CHECK: risbgn %r0, %r0, 0, 255, 0
-0xec 0x00 0x00 0xff 0x00 0x59
+# CHECK: risbgn %r0, %r0, 0, 127, 0
+0xec 0x00 0x00 0x7f 0x00 0x59
# CHECK: risbgn %r0, %r0, 255, 0, 0
0xec 0x00 0xff 0x00 0x00 0x59
@@ -14010,6 +14013,9 @@
# CHECK: risbgn %r4, %r5, 6, 7, 8
0xec 0x45 0x06 0x07 0x08 0x59
+# CHECK: risbgnz %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x87 0x08 0x59
+
# CHECK: risbhg %r0, %r0, 0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x5d
diff --git a/llvm/test/MC/SystemZ/insn-good-zEC12.s b/llvm/test/MC/SystemZ/insn-good-zEC12.s
index db37d28686e9b..a564491c6c36f 100644
--- a/llvm/test/MC/SystemZ/insn-good-zEC12.s
+++ b/llvm/test/MC/SystemZ/insn-good-zEC12.s
@@ -462,21 +462,33 @@
#CHECK: risbgn %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59]
#CHECK: risbgn %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x59]
#CHECK: risbgn %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x59]
-#CHECK: risbgn %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59]
+#CHECK: risbgnz %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59]
+#CHECK: risbgn %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59]
#CHECK: risbgn %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x59]
+#CHECK: risbgn %r0, %r0, 0, 0, 127 # encoding: [0xec,0x00,0x00,0x00,0x7f,0x59]
+#CHECK: risbgnz %r0, %r0, 0, 127, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59]
+#CHECK: risbgn %r0, %r0, 0, 127, 0 # encoding: [0xec,0x00,0x00,0x7f,0x00,0x59]
+#CHECK: risbgn %r0, %r0, 127, 0, 0 # encoding: [0xec,0x00,0x7f,0x00,0x00,0x59]
#CHECK: risbgn %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x59]
#CHECK: risbgn %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x59]
#CHECK: risbgn %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x59]
+#CHECK: risbgnz %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x87,0x08,0x59]
risbgn %r0,%r0,0,0,0
risbgn %r0,%r0,0,0,63
risbgn %r0,%r0,0,0,64
risbgn %r0,%r0,0,0,255
+ risbgnz %r0,%r0,0,255,0
risbgn %r0,%r0,0,255,0
risbgn %r0,%r0,255,0,0
+ risbgn %r0,%r0,0,0,127
+ risbgnz %r0,%r0,0,127,0
+ risbgn %r0,%r0,0,127,0
+ risbgn %r0,%r0,127,0,0
risbgn %r0,%r15,0,0,0
risbgn %r15,%r0,0,0,0
risbgn %r4,%r5,6,7,8
+ risbgnz %r4,%r5,6,7,8
#CHECK: tabort 0 # encoding: [0xb2,0xfc,0x00,0x00]
#CHECK: tabort 0(%r1) # encoding: [0xb2,0xfc,0x10,0x00]
diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s
index 957222109b389..35d107afefcfa 100644
--- a/llvm/test/MC/SystemZ/insn-good.s
+++ b/llvm/test/MC/SystemZ/insn-good.s
@@ -13689,21 +13689,33 @@
#CHECK: risbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55]
#CHECK: risbg %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x55]
#CHECK: risbg %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x55]
-#CHECK: risbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55]
+#CHECK: risbgz %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55]
+#CHECK: risbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55]
#CHECK: risbg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x55]
+#CHECK: risbg %r0, %r0, 0, 0, 127 # encoding: [0xec,0x00,0x00,0x00,0x7f,0x55]
+#CHECK: risbgz %r0, %r0, 0, 127, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55]
+#CHECK: risbg %r0, %r0, 0, 127, 0 # encoding: [0xec,0x00,0x00,0x7f,0x00,0x55]
+#CHECK: risbg %r0, %r0, 127, 0, 0 # encoding: [0xec,0x00,0x7f,0x00,0x00,0x55]
#CHECK: risbg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x55]
#CHECK: risbg %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x55]
#CHECK: risbg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x55]
+#CHECK: risbgz %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x87,0x08,0x55]
risbg %r0,%r0,0,0,0
risbg %r0,%r0,0,0,63
risbg %r0,%r0,0,0,64
risbg %r0,%r0,0,0,255
+ risbgz %r0,%r0,0,255,0
risbg %r0,%r0,0,255,0
risbg %r0,%r0,255,0,0
+ risbg %r0,%r0,0,0,127
+ risbgz %r0,%r0,0,127,0
+ risbg %r0,%r0,0,127,0
+ risbg %r0,%r0,127,0,0
risbg %r0,%r15,0,0,0
risbg %r15,%r0,0,0,0
risbg %r4,%r5,6,7,8
+ risbgz %r4,%r5,6,7,8
#CHECK: rll %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x1d]
#CHECK: rll %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0x1d]
>From 8d3bb4413a1b0f397f2346a85d66936e7bfda154 Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Wed, 3 Jul 2024 13:19:54 +0200
Subject: [PATCH 5/5] [SystemZ] Add extended mnemonics for R(N|O|X)SBG(T)?
These are extended mnemonics of the "Rotate and (And / Or / Xor) selected
bits" instructions. For this use case, a new instruction format was added,
`FixedRotateSelectRIEf`, which allows the full specification of all immediate
fields in the instruction. This is useful here since most extended mnemonics
we add use constant values for all these immediates. The remainder merely set
the T bit for the instruction, and can thus be expressed using existing
formats.
---
.../lib/Target/SystemZ/SystemZInstrFormats.td | 11 +++
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 19 ++++-
llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 3 +-
llvm/lib/Target/SystemZ/SystemZScheduleZ14.td | 3 +-
llvm/lib/Target/SystemZ/SystemZScheduleZ15.td | 3 +-
llvm/lib/Target/SystemZ/SystemZScheduleZ16.td | 3 +-
.../lib/Target/SystemZ/SystemZScheduleZ196.td | 3 +-
.../Target/SystemZ/SystemZScheduleZEC12.td | 3 +-
llvm/test/MC/Disassembler/SystemZ/insns.txt | 82 +++++++++++++++++--
llvm/test/MC/SystemZ/insn-good.s | 30 +++++++
10 files changed, 142 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 878f1d6377c50..f2eb331f2426d 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -5048,6 +5048,17 @@ class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
let DisableEncoding = "$R1src";
}
+class FixedRotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
+ RegisterOperand cls2, bits<8> I3_in, bits<8> I4_in, bits<8> I5_in = 0>
+ : InstRIEf<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
+ mnemonic#"\t$R1, $R2", []> {
+ let I3 = I3_in;
+ let I4 = I4_in;
+ let I5 = I5_in;
+ let Constraints = "$R1 = $R1src";
+ let DisableEncoding = "$R1src";
+}
+
class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
: InstRXYb<opcode, (outs),
(ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 4b540d61312b5..898b80e3a7a3d 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -1566,9 +1566,22 @@ let Predicates = [FeatureHighWord] in {
// bits of the first operand. The CC result only describes the selected bits,
// so isn't useful for a full comparison against zero.
let Defs = [CC] in {
- def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
- def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
- def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
+ def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
+ def NHHR : FixedRotateSelectRIEf<"nhhr", 0xEC54, GR64, GR64, 0, 31>;
+ def NHLR : FixedRotateSelectRIEf<"nhlr", 0xEC54, GR64, GR64, 0, 31, 32>;
+ def NLHR : FixedRotateSelectRIEf<"nlhr", 0xEC54, GR64, GR64, 32, 63, 32>;
+ def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
+ def OHHR : FixedRotateSelectRIEf<"ohhr", 0xEC56, GR64, GR64, 0, 31>;
+ def OHLR : FixedRotateSelectRIEf<"ohlr", 0xEC56, GR64, GR64, 0, 31, 32>;
+ def OLHR : FixedRotateSelectRIEf<"olhr", 0xEC56, GR64, GR64, 32, 63, 32>;
+ def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
+ def XHHR : FixedRotateSelectRIEf<"xhhr", 0xEC57, GR64, GR64, 0, 31>;
+ def XHLR : FixedRotateSelectRIEf<"xhlr", 0xEC57, GR64, GR64, 0, 31, 32>;
+ def XLHR : FixedRotateSelectRIEf<"xlhr", 0xEC57, GR64, GR64, 32, 63, 32>;
+ // 128 on I3 sets the T bit for the instruction
+ def RNSBGT : RotateSelectRIEf<"rnsbgt", 0xEC54, GR64, GR64, 128>;
+ def ROSBGT : RotateSelectRIEf<"rosbgt", 0xEC56, GR64, GR64, 128>;
+ def RXSBGT : RotateSelectRIEf<"rxsbgt", 0xEC57, GR64, GR64, 128>;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
index d0fec02777875..3e87b2ed7ae9c 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -512,7 +512,8 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat3, WLat3, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat3, WLat3, FXa2, Cracked], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat3, WLat3, FXa2, Cracked], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
index a6d89ce9443c5..323262b831e3a 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
@@ -522,7 +522,8 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
index 455354e283ad8..3a1eec594590e 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
@@ -537,7 +537,8 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
index 92abf0ba4022c..0a56fd78fb09b 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
@@ -537,7 +537,8 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
index 99d0d674bbbb2..64bd642e0d2f8 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -475,7 +475,8 @@ def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(32)?(Z)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
index 5b334da2bac34..a8dfe3b0391c6 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -486,7 +486,8 @@ def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt
index 392993d4e2a36..ef59e2ed2bd2a 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt
@@ -14133,15 +14133,24 @@
# CHECK: rnsbg %r0, %r0, 0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x54
-# CHECK: rnsbg %r0, %r0, 0, 0, 63
-0xec 0x00 0x00 0x00 0x3f 0x54
+# CHECK: rnsbg %r0, %r0, 0, 0, 255
+0xec 0x00 0x00 0x00 0xff 0x54
# CHECK: rnsbg %r0, %r0, 0, 255, 0
0xec 0x00 0x00 0xff 0x00 0x54
-# CHECK: rnsbg %r0, %r0, 255, 0, 0
+# CHECK: rnsbgt %r0, %r0, 127, 0, 0
0xec 0x00 0xff 0x00 0x00 0x54
+# CHECK: rnsbg %r0, %r0, 0, 0, 127
+0xec 0x00 0x00 0x00 0x7f 0x54
+
+# CHECK: rnsbg %r0, %r0, 0, 127, 0
+0xec 0x00 0x00 0x7f 0x00 0x54
+
+# CHECK: rnsbg %r0, %r0, 127, 0, 0
+0xec 0x00 0x7f 0x00 0x00 0x54
+
# CHECK: rnsbg %r0, %r15, 0, 0, 0
0xec 0x0f 0x00 0x00 0x00 0x54
@@ -14151,18 +14160,40 @@
# CHECK: rnsbg %r4, %r5, 6, 7, 8
0xec 0x45 0x06 0x07 0x08 0x54
+# CHECK: rnsbgt %r4, %r5, 6, 7, 8
+0xec 0x45 0x86 0x07 0x08 0x54
+
+# CHECK: nhhr %r0, %r1
+0xec 0x01 0x00 0x1f 0x00 0x54
+
+# CHECK: nhlr %r0, %r1
+0xec 0x01 0x00 0x1f 0x20 0x54
+
+# CHECK: nlhr %r0, %r1
+0xec 0x01 0x20 0x3f 0x20 0x54
+
# CHECK: rosbg %r0, %r0, 0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x56
-# CHECK: rosbg %r0, %r0, 0, 0, 63
-0xec 0x00 0x00 0x00 0x3f 0x56
+
+# CHECK: rosbg %r0, %r0, 0, 0, 255
+0xec 0x00 0x00 0x00 0xff 0x56
# CHECK: rosbg %r0, %r0, 0, 255, 0
0xec 0x00 0x00 0xff 0x00 0x56
-# CHECK: rosbg %r0, %r0, 255, 0, 0
+# CHECK: rosbgt %r0, %r0, 127, 0, 0
0xec 0x00 0xff 0x00 0x00 0x56
+# CHECK: rosbg %r0, %r0, 0, 0, 127
+0xec 0x00 0x00 0x00 0x7f 0x56
+
+# CHECK: rosbg %r0, %r0, 0, 127, 0
+0xec 0x00 0x00 0x7f 0x00 0x56
+
+# CHECK: rosbg %r0, %r0, 127, 0, 0
+0xec 0x00 0x7f 0x00 0x00 0x56
+
# CHECK: rosbg %r0, %r15, 0, 0, 0
0xec 0x0f 0x00 0x00 0x00 0x56
@@ -14172,6 +14203,18 @@
# CHECK: rosbg %r4, %r5, 6, 7, 8
0xec 0x45 0x06 0x07 0x08 0x56
+# CHECK: rosbgt %r4, %r5, 6, 7, 8
+0xec 0x45 0x86 0x07 0x08 0x56
+
+# CHECK: ohhr %r0, %r1
+0xec 0x01 0x00 0x1f 0x00 0x56
+
+# CHECK: ohlr %r0, %r1
+0xec 0x01 0x00 0x1f 0x20 0x56
+
+# CHECK: olhr %r0, %r1
+0xec 0x01 0x20 0x3f 0x20 0x56
+
# CHECK: rp 0
0xb2 0x77 0x00 0x00
@@ -14262,15 +14305,24 @@
# CHECK: rxsbg %r0, %r0, 0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x57
-# CHECK: rxsbg %r0, %r0, 0, 0, 63
-0xec 0x00 0x00 0x00 0x3f 0x57
+# CHECK: rxsbg %r0, %r0, 0, 0, 255
+0xec 0x00 0x00 0x00 0xff 0x57
# CHECK: rxsbg %r0, %r0, 0, 255, 0
0xec 0x00 0x00 0xff 0x00 0x57
-# CHECK: rxsbg %r0, %r0, 255, 0, 0
+# CHECK: rxsbgt %r0, %r0, 127, 0, 0
0xec 0x00 0xff 0x00 0x00 0x57
+# CHECK: rxsbg %r0, %r0, 0, 0, 127
+0xec 0x00 0x00 0x00 0x7f 0x57
+
+# CHECK: rxsbg %r0, %r0, 0, 127, 0
+0xec 0x00 0x00 0x7f 0x00 0x57
+
+# CHECK: rxsbg %r0, %r0, 127, 0, 0
+0xec 0x00 0x7f 0x00 0x00 0x57
+
# CHECK: rxsbg %r0, %r15, 0, 0, 0
0xec 0x0f 0x00 0x00 0x00 0x57
@@ -14280,6 +14332,18 @@
# CHECK: rxsbg %r4, %r5, 6, 7, 8
0xec 0x45 0x06 0x07 0x08 0x57
+# CHECK: rxsbgt %r4, %r5, 6, 7, 8
+0xec 0x45 0x86 0x07 0x08 0x57
+
+# CHECK: xhhr %r0, %r1
+0xec 0x01 0x00 0x1f 0x00 0x57
+
+# CHECK: xhlr %r0, %r1
+0xec 0x01 0x00 0x1f 0x20 0x57
+
+# CHECK: xlhr %r0, %r1
+0xec 0x01 0x20 0x3f 0x20 0x57
+
# CHECK: s %r0, 0
0x5b 0x00 0x00 0x00
diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s
index 35d107afefcfa..d3990be81b897 100644
--- a/llvm/test/MC/SystemZ/insn-good.s
+++ b/llvm/test/MC/SystemZ/insn-good.s
@@ -13775,9 +13775,14 @@
#CHECK: rnsbg %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x54]
#CHECK: rnsbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x54]
#CHECK: rnsbg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x54]
+#CHECK: rnsbgt %r0, %r0, 127, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x54]
#CHECK: rnsbg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x54]
#CHECK: rnsbg %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x54]
#CHECK: rnsbg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x54]
+#CHECK: rnsbgt %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x86,0x07,0x08,0x54]
+#CHECK: nhhr %r0, %r1 # encoding: [0xec,0x01,0x00,0x1f,0x00,0x54]
+#CHECK: nhlr %r2, %r3 # encoding: [0xec,0x23,0x00,0x1f,0x20,0x54]
+#CHECK: nlhr %r4, %r5 # encoding: [0xec,0x45,0x20,0x3f,0x20,0x54]
rnsbg %r0,%r0,0,0,0
rnsbg %r0,%r0,0,0,63
@@ -13785,9 +13790,14 @@
rnsbg %r0,%r0,0,0,255
rnsbg %r0,%r0,0,255,0
rnsbg %r0,%r0,255,0,0
+ rnsbgt %r0,%r0,127,0,0
rnsbg %r0,%r15,0,0,0
rnsbg %r15,%r0,0,0,0
rnsbg %r4,%r5,6,7,8
+ rnsbgt %r4,%r5,6,7,8
+ nhhr %r0, %r1
+ nhlr %r2, %r3
+ nlhr %r4, %r5
#CHECK: rosbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x56]
#CHECK: rosbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x56]
@@ -13795,9 +13805,14 @@
#CHECK: rosbg %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x56]
#CHECK: rosbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x56]
#CHECK: rosbg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x56]
+#CHECK: rosbgt %r0, %r0, 127, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x56]
#CHECK: rosbg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x56]
#CHECK: rosbg %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x56]
#CHECK: rosbg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x56]
+#CHECK: rosbgt %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x86,0x07,0x08,0x56]
+#CHECK: ohhr %r0, %r1 # encoding: [0xec,0x01,0x00,0x1f,0x00,0x56]
+#CHECK: ohlr %r2, %r3 # encoding: [0xec,0x23,0x00,0x1f,0x20,0x56]
+#CHECK: olhr %r4, %r5 # encoding: [0xec,0x45,0x20,0x3f,0x20,0x56]
rosbg %r0,%r0,0,0,0
rosbg %r0,%r0,0,0,63
@@ -13805,9 +13820,14 @@
rosbg %r0,%r0,0,0,255
rosbg %r0,%r0,0,255,0
rosbg %r0,%r0,255,0,0
+ rosbgt %r0,%r0,127,0,0
rosbg %r0,%r15,0,0,0
rosbg %r15,%r0,0,0,0
rosbg %r4,%r5,6,7,8
+ rosbgt %r4,%r5,6,7,8
+ ohhr %r0, %r1
+ ohlr %r2, %r3
+ olhr %r4, %r5
#CHECK: rp 0 # encoding: [0xb2,0x77,0x00,0x00]
#CHECK: rp 0(%r1) # encoding: [0xb2,0x77,0x10,0x00]
@@ -13873,9 +13893,14 @@
#CHECK: rxsbg %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x57]
#CHECK: rxsbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x57]
#CHECK: rxsbg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x57]
+#CHECK: rxsbgt %r0, %r0, 127, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x57]
#CHECK: rxsbg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x57]
#CHECK: rxsbg %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x57]
#CHECK: rxsbg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x57]
+#CHECK: rxsbgt %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x86,0x07,0x08,0x57]
+#CHECK: xhhr %r0, %r1 # encoding: [0xec,0x01,0x00,0x1f,0x00,0x57]
+#CHECK: xhlr %r2, %r3 # encoding: [0xec,0x23,0x00,0x1f,0x20,0x57]
+#CHECK: xlhr %r4, %r5 # encoding: [0xec,0x45,0x20,0x3f,0x20,0x57]
rxsbg %r0,%r0,0,0,0
rxsbg %r0,%r0,0,0,63
@@ -13883,9 +13908,14 @@
rxsbg %r0,%r0,0,0,255
rxsbg %r0,%r0,0,255,0
rxsbg %r0,%r0,255,0,0
+ rxsbgt %r0,%r0,127,0,0
rxsbg %r0,%r15,0,0,0
rxsbg %r15,%r0,0,0,0
rxsbg %r4,%r5,6,7,8
+ rxsbgt %r4,%r5,6,7,8
+ xhhr %r0, %r1
+ xhlr %r2, %r3
+ xlhr %r4, %r5
#CHECK: s %r0, 0 # encoding: [0x5b,0x00,0x00,0x00]
#CHECK: s %r0, 4095 # encoding: [0x5b,0x00,0x0f,0xff]
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