[llvm] [AArch64] All bits of an exact right shift are demanded (PR #97448)

[via llvm-commits]

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@@ -22142,6 +22142,10 @@ static SDValue performVectorShiftCombine(SDNode *N,
     if (DCI.DAG.ComputeNumSignBits(Op.getOperand(0)) > ShiftImm)
       return Op.getOperand(0);
 
+  // If the right shift is exact, the shifted out bits matter.
+  if (N->getOpcode() == AArch64ISD::VASHR && N->getFlags().hasExact())
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CarolineConcatto wrote:

I think I have the same comments as David, I can see that CreateLShr also has the flag isExact.
It will not be triggered by your patch in : https://github.com/llvm/llvm-project/pull/92528, because you only add 
auto *AShr = Builder.CreateAShr(Cast, 24, "", true);
But, maybe this patch should also test for that one.

https://github.com/llvm/llvm-project/pull/97448