[llvm] [RISCV] Support vXf16 vector_shuffle with Zvfhmin. (PR #97491)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 2 16:52:44 PDT 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/97491
We can shuffle vXf16 vectors just like vXi16 vectors. We don't need any FP instructions. Update the predicates for vrgather and vslides patterns to only check the predicates based on the equivalent integer type. If we use the FP type it will check Zvfh and block Zvfhmin.
These are probably not the only patterns that need to be fixed, but the test from the bug report.
Fixes #97477
>From ff0516298828fcc59b8ad42dec2410d3fb30f5f6 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 2 Jul 2024 16:47:26 -0700
Subject: [PATCH] [RISCV] Support vXf16 vector_shuffle with Zvfhmin.
We can shuffle vXf16 vectors just like vXi16 vectors. We don't
need any FP instructions. Update the predicates for vrgather and
vslides patterns to only check the predicates based on the
equivalent integer type. If we use the FP type it will check Zvfh
and block Zvfhmin.
These are probably not the only patterns that need to be fixed,
but the test from the bug report.
Fixes #97477
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
.../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 6 ++--
.../RISCV/rvv/fixed-vectors-fp-shuffles.ll | 34 +++++++++++++++++++
3 files changed, 38 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7e38e14689fa0..02767d0c2b5c2 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1317,7 +1317,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP},
VT, Custom);
setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
- ISD::EXTRACT_SUBVECTOR},
+ ISD::EXTRACT_SUBVECTOR, ISD::VECTOR_SHUFFLE},
VT, Custom);
setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index a7945f2ee6c1b..cc294bf9254e8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -2117,7 +2117,8 @@ multiclass VPatWidenFPMulAccVL_VV_VF_RM<SDNode vop, string instruction_name> {
multiclass VPatSlideVL_VX_VI<SDNode vop, string instruction_name> {
foreach vti = AllVectors in {
- let Predicates = GetVTypePredicates<vti>.Predicates in {
+ defvar ivti = GetIntVTypeInfo<vti>.Vti;
+ let Predicates = GetVTypePredicates<ivti>.Predicates in {
def : Pat<(vti.Vector (vop (vti.Vector vti.RegClass:$rd),
(vti.Vector vti.RegClass:$rs1),
uimm5:$rs2, (vti.Mask V0),
@@ -3001,8 +3002,7 @@ foreach vti = AllFloatVectors in {
(vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>;
}
defvar ivti = GetIntVTypeInfo<vti>.Vti;
- let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
- GetVTypePredicates<ivti>.Predicates) in {
+ let Predicates = GetVTypePredicates<ivti>.Predicates in {
def : Pat<(vti.Vector
(riscv_vrgather_vv_vl vti.RegClass:$rs2,
(ivti.Vector vti.RegClass:$rs1),
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
index 45c0a22b1939f..c92bfcd7e50a5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <4 x half> @shuffle_v4f16(<4 x half> %x, <4 x half> %y) {
; CHECK-LABEL: shuffle_v4f16:
@@ -262,6 +264,38 @@ define <8 x double> @splice_binary2(<8 x double> %x, <8 x double> %y) {
%s = shufflevector <8 x double> %x, <8 x double> %y, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
ret <8 x double> %s
}
+
+define <4 x half> @vrgather_permute_shuffle_vu_v4f16(<4 x half> %x) {
+; CHECK-LABEL: vrgather_permute_shuffle_vu_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 4096
+; CHECK-NEXT: addi a0, a0, 513
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsext.vf2 v10, v9
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %s = shufflevector <4 x half> %x, <4 x half> poison, <4 x i32> <i32 1, i32 2, i32 0, i32 1>
+ ret <4 x half> %s
+}
+
+define <4 x half> @vrgather_shuffle_vv_v4f16(<4 x half> %x, <4 x half> %y) {
+; CHECK-LABEL: vrgather_shuffle_vv_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI21_0)
+; CHECK-NEXT: addi a0, a0, %lo(.LCPI21_0)
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; CHECK-NEXT: vle16.v v11, (a0)
+; CHECK-NEXT: vmv.v.i v0, 8
+; CHECK-NEXT: vrgather.vv v10, v8, v11
+; CHECK-NEXT: vrgather.vi v10, v9, 1, v0.t
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %s = shufflevector <4 x half> %x, <4 x half> %y, <4 x i32> <i32 1, i32 2, i32 0, i32 5>
+ ret <4 x half> %s
+}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}
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