[llvm] [AMDGPU] Add IR LiveReg type-based optimization (PR #66838)

[Jeffrey Byrnes via llvm-commits]

jrbyrnes wrote:

> This pass, like most combiners, should work bottom up not top down. Would that avoid the issue?

Yes we can achieve the loop integration with reverse iteration and integrated deletion -- this is implemented in the latest version.

During this implemetaion, I found what I thought to be a regression, but this was actually flagging a bug in the way deleting PHIs was handled in the previous version. In the previous version, when we are unable to convert all incoming values for a coerced PHI, we would flag the PHI for deletion -- to be deleted post loop. However, we did not also update the ValMap, so users would still update their operands to use the coerced PHI, which would then be deleted. The latest contains the fix for this. This will only occur when we having a weird incoming value for a PHI (e.g. vector literal); I assume it is for this reason that PSDB didn't notice it.

https://github.com/llvm/llvm-project/pull/66838