[llvm] 57555c6 - [RISCV] Don't custom lower f16 SCALAR_TO_VECTOR with Zvfhmin.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 2 14:52:45 PDT 2024
Author: Craig Topper
Date: 2024-07-02T14:48:21-07:00
New Revision: 57555c6a0a96790bf1408b056405abe07899ead4
URL: https://github.com/llvm/llvm-project/commit/57555c6a0a96790bf1408b056405abe07899ead4
DIFF: https://github.com/llvm/llvm-project/commit/57555c6a0a96790bf1408b056405abe07899ead4.diff
LOG: [RISCV] Don't custom lower f16 SCALAR_TO_VECTOR with Zvfhmin.
This doesn't appear to be tested and our custom handler doesn't
support this right now.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ee45f730dc450..7e38e14689fa0 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1074,7 +1074,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP},
VT, Custom);
setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
- ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR},
+ ISD::EXTRACT_SUBVECTOR},
VT, Custom);
if (Subtarget.hasStdExtZfhminOrZhinxmin())
setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
@@ -1317,7 +1317,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP},
VT, Custom);
setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
- ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR},
+ ISD::EXTRACT_SUBVECTOR},
VT, Custom);
setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
More information about the llvm-commits
mailing list