[llvm] [RISCV] Allow non-power-of-2 vectors for VLS code generation (PR #97010)

[Philip Reames via llvm-commits]

preames wrote:

I'm focusing my comment on the codegen changes to understand the merits of this approach over alternatives.

Glancing through, I see a couple major categories of changes:
* VL only changes.  Code sequence doesn't change.  Depending on micro architecture, this can be either profitable, or useless.
* LD/ST related changes -- more discussion below.
* Splitting vs Widening - We appear to have some cases where we are splitting arithmetic operations which could be widened to the next legal type.  Example would be some of the FP/int conversion cases.  (The non-power of two legal case side steps this choice.)
* Just poor codegen - examples, some of the sum reduction examples should be a single masked vmv.v.x instead of a series of vslides.  

I think we can improve the codegen for the non-zero VL quite a ways before we worry about the LD/ST cases.  I'd like to see us do so because it makes it easier to assess the alternatives.  

On LD/ST specifically, I do not have a super strong opinion on which approach to take.  To an extend, I'm happy to defer to the person driving this forward.  I have a mild preference for something which works for any VL (not just 3, 7, 15), but that preference is not strong.  

https://github.com/llvm/llvm-project/pull/97010