[llvm] [RISCV] Pack build_vectors into largest available element type (PR #97351)

[Philip Reames via llvm-commits]

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@@ -1267,43 +1267,53 @@ define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) {
 ;
 ; RVA22U64-LABEL: buildvec_v16i8_loads_contigous:
 ; RVA22U64:       # %bb.0:
-; RVA22U64-NEXT:    addi a6, a0, 8
-; RVA22U64-NEXT:    lbu t6, 1(a0)
+; RVA22U64-NEXT:    lbu a1, 1(a0)
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preames wrote:

We don't appear to have support in tree for rva22u32 (as an mattr alias).  I went digging through profile docs, and I can't find any mention of the rva22u32 profile variants; rva22 appears to only define 64 bit versions.

Do you have a particular arch string for a configuration which exercises the case you're concerned about here?

https://github.com/llvm/llvm-project/pull/97351