[llvm] [RISCV] Allow non-power-of-2 vectors for VLS code generation (PR #97010)

[Matt Arsenault via llvm-commits]

================
@@ -349,6 +349,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
   setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
 
   setTruncStoreAction(MVT::v3i32, MVT::v3i8, Expand);
+  setTruncStoreAction(MVT::v5i32, MVT::v5i8, Expand);
----------------
arsenm wrote:

Seems suspicious we don't need a v5i32->v5i16 case. Probably missing test coverage 

https://github.com/llvm/llvm-project/pull/97010