[llvm] [AMDGPU] Set register bank for i1 arguments/return values (PR #96155)

[Matt Arsenault via llvm-commits]

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@@ -3745,6 +3745,21 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     if (!DstBank)
       DstBank = SrcBank;
 
+    // The calling convention is to be updated such that i1 function arguments
+    // or return values are assigned to SGPRs without promoting to i32. With
+    // this, for i1 function arguments, the call of getRegBank() above gives
+    // incorrect result. We set both src and dst banks to VCCRegBank.
+    if (!MI.getOperand(1).getReg().isVirtual() &&
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arsenm wrote:

You need to add MIR tests showing the regclass / regbank / physreg with i1 permutations here first to review this usefully. You shouldn't need to check isCopy again either. Freeze is just the same as copy, except it can't have the physreg inputs 

https://github.com/llvm/llvm-project/pull/96155