[llvm] [AArch64] Refactor predicate register class decode functions (PR #97412)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 2 05:46:39 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: None (DevM-uk)
<details>
<summary>Changes</summary>
In a previous PR #<!-- -->81716, a new decoder function was added to llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp. During code review it was suggested that, as most of the decoder functions were very similar in structure, that they be refactored into a single, templated function. I have added the refactored function, removed the definitions of the replaced functions, and replaced the references to the replaced functions in AArch64Disassembler.cpp and llvm/lib/Target/AArch64/AArch64RegisterInfo.td. To reduce the number of duplicate references in AArch64RegisterInfo.td, I have also made a small change to llvm/utils/TableGen/DecoderEmitter.cpp.
---
Patch is 71.51 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/97412.diff
3 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64RegisterInfo.td (+63-16)
- (modified) llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (+233-595)
- (modified) llvm/utils/TableGen/DecoderEmitter.cpp (+2-1)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index dfaa67dd1959d..4dc33e6168cbd 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -160,25 +160,30 @@ def GPR64common : RegisterClass<"AArch64", [i64], 64,
(add (sequence "X%u", 0, 28), FP, LR)> {
let AltOrders = [(rotl GPR64common, 8)];
let AltOrderSelect = [{ return 1; }];
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>";
}
// GPR register classes which exclude SP/WSP.
def GPR32 : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR)> {
let AltOrders = [(rotl GPR32, 8)];
let AltOrderSelect = [{ return 1; }];
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>";
}
def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> {
let AltOrders = [(rotl GPR64, 8)];
let AltOrderSelect = [{ return 1; }];
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>";
}
// GPR register classes which include SP/WSP.
def GPR32sp : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WSP)> {
let AltOrders = [(rotl GPR32sp, 8)];
let AltOrderSelect = [{ return 1; }];
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>";
}
def GPR64sp : RegisterClass<"AArch64", [i64], 64, (add GPR64common, SP)> {
let AltOrders = [(rotl GPR64sp, 8)];
let AltOrderSelect = [{ return 1; }];
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID,0, 32>";
}
def GPR32sponly : RegisterClass<"AArch64", [i32], 32, (add WSP)>;
@@ -446,18 +451,24 @@ def Q31 : AArch64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias<B31>;
def FPR8 : RegisterClass<"AArch64", [i8], 8, (sequence "B%u", 0, 31)> {
let Size = 8;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>";
}
def FPR16 : RegisterClass<"AArch64", [f16, bf16, i16], 16, (sequence "H%u", 0, 31)> {
let Size = 16;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>";
}
def FPR16_lo : RegisterClass<"AArch64", [f16], 16, (trunc FPR16, 16)> {
let Size = 16;
}
-def FPR32 : RegisterClass<"AArch64", [f32, i32], 32,(sequence "S%u", 0, 31)>;
+def FPR32 : RegisterClass<"AArch64", [f32, i32], 32,(sequence "S%u", 0, 31)> {
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>";
+}
def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
v1i64, v4f16, v4bf16],
- 64, (sequence "D%u", 0, 31)>;
+ 64, (sequence "D%u", 0, 31)> {
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>";
+}
def FPR64_lo : RegisterClass<"AArch64",
[v8i8, v4i16, v2i32, v1i64, v4f16, v4bf16, v2f32,
v1f64],
@@ -469,21 +480,27 @@ def FPR64_lo : RegisterClass<"AArch64",
def FPR128 : RegisterClass<"AArch64",
[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, f128,
v8f16, v8bf16],
- 128, (sequence "Q%u", 0, 31)>;
+ 128, (sequence "Q%u", 0, 31)> {
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>";
+}
// The lower 16 vector registers. Some instructions can only take registers
// in this range.
def FPR128_lo : RegisterClass<"AArch64",
[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16,
v8bf16],
- 128, (trunc FPR128, 16)>;
+ 128, (trunc FPR128, 16)> {
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 16>";
+}
// The lower 8 vector registers. Some instructions can only take registers
// in this range.
def FPR128_0to7 : RegisterClass<"AArch64",
[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16,
v8bf16],
- 128, (trunc FPR128, 8)>;
+ 128, (trunc FPR128, 8)> {
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 8>";
+}
// Pairs, triples, and quads of 64-bit vector registers.
def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
@@ -495,12 +512,15 @@ def DSeqQuads : RegisterTuples<[dsub0, dsub1, dsub2, dsub3],
(rotl FPR64, 2), (rotl FPR64, 3)]>;
def DD : RegisterClass<"AArch64", [untyped], 64, (add DSeqPairs)> {
let Size = 128;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::DDRegClassID, 0, 32>";
}
def DDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> {
let Size = 192;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::DDDRegClassID, 0, 32>";
}
def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> {
let Size = 256;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::DDDDRegClassID, 0, 32>";
}
// Pairs, triples, and quads of 128-bit vector registers.
@@ -513,12 +533,15 @@ def QSeqQuads : RegisterTuples<[qsub0, qsub1, qsub2, qsub3],
(rotl FPR128, 2), (rotl FPR128, 3)]>;
def QQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqPairs)> {
let Size = 256;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::QQRegClassID, 0, 32>";
}
def QQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqTriples)> {
let Size = 384;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::QQQRegClassID, 0, 32>";
}
def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> {
let Size = 512;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::QQQQRegClassID, 0, 32>";
}
@@ -904,9 +927,15 @@ class PPRClass<int firstreg, int lastreg> : RegisterClass<
let Size = 16;
}
-def PPR : PPRClass<0, 15>;
-def PPR_3b : PPRClass<0, 7>; // Restricted 3 bit SVE predicate register class.
-def PPR_p8to15 : PPRClass<8, 15>;
+def PPR : PPRClass<0, 15> {
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PPRRegClassID, 0, 16>";
+}
+def PPR_3b : PPRClass<0, 7> { // Restricted 3 bit SVE predicate register class.
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PPRRegClassID, 0, 8>";
+}
+def PPR_p8to15 : PPRClass<8, 15> {
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PNRRegClassID, 8, 8>";
+}
class PPRAsmOperand <string name, string RegClass, int Width>: AsmOperandClass {
let Name = "SVE" # name # "Reg";
@@ -941,7 +970,9 @@ class PNRClass<int firstreg, int lastreg> : RegisterClass<
let Size = 16;
}
-def PNR : PNRClass<0, 15>;
+def PNR : PNRClass<0, 15> {
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PNRRegClassID, 0, 16>";
+}
def PNR_3b : PNRClass<0, 7>;
def PNR_p8to15 : PNRClass<8, 15>;
@@ -982,7 +1013,7 @@ class PNRP8to15RegOp<string Suffix, AsmOperandClass C, int Width, RegisterClass
: SVERegOp<Suffix, C, ElementSizeNone, RC> {
let PrintMethod = "printPredicateAsCounter<" # Width # ">";
let EncoderMethod = "EncodePNR_p8to15";
- let DecoderMethod = "DecodePNR_p8to15RegisterClass";
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PNRRegClassID, 8, 8>";
}
def PNRAny_p8to15 : PNRP8to15RegOp<"", PNRAsmAny_p8to15, 0, PNR_p8to15>;
@@ -1013,7 +1044,9 @@ class PPRorPNRAsmOperand<string name, string RegClass, int Width>: AsmOperandCla
let ParserMethod = "tryParseSVEPredicateOrPredicateAsCounterVector";
}
-def PPRorPNR : PPRorPNRClass;
+def PPRorPNR : PPRorPNRClass {
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PPRorPNRRegClassID, 0, 16>";
+}
def PPRorPNRAsmOp8 : PPRorPNRAsmOperand<"PPRorPNRB", "PPRorPNR", 8>;
def PPRorPNRAsmOpAny : PPRorPNRAsmOperand<"PPRorPNRAny", "PPRorPNR", 0>;
def PPRorPNRAny : PPRRegOp<"", PPRorPNRAsmOpAny, ElementSizeNone, PPRorPNR>;
@@ -1024,6 +1057,7 @@ def PSeqPairs : RegisterTuples<[psub0, psub1], [(rotl PPR, 0), (rotl PPR, 1)]>;
def PPR2 : RegisterClass<"AArch64", [untyped], 16, (add PSeqPairs)> {
let Size = 32;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PPR2RegClassID, 0, 16>";
}
class PPRVectorList<int ElementWidth, int NumRegs> : AsmOperandClass {
@@ -1097,9 +1131,15 @@ class ZPRClass<int lastreg> : RegisterClass<"AArch64",
let Size = 128;
}
-def ZPR : ZPRClass<31>;
-def ZPR_4b : ZPRClass<15>; // Restricted 4 bit SVE vector register class.
-def ZPR_3b : ZPRClass<7>; // Restricted 3 bit SVE vector register class.
+def ZPR : ZPRClass<31> {
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>";
+}
+def ZPR_4b : ZPRClass<15> { // Restricted 4 bit SVE vector register class.
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 16>";
+}
+def ZPR_3b : ZPRClass<7> { // Restricted 3 bit SVE vector register class.
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 8>";
+}
class ZPRAsmOperand<string name, int Width, string RegClassSuffix = "">
: AsmOperandClass {
@@ -1176,12 +1216,15 @@ def ZSeqQuads : RegisterTuples<[zsub0, zsub1, zsub2, zsub3], [(rotl ZPR, 0), (
def ZPR2 : RegisterClass<"AArch64", [untyped], 128, (add ZSeqPairs)> {
let Size = 256;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR2RegClassID, 0, 32>";
}
def ZPR3 : RegisterClass<"AArch64", [untyped], 128, (add ZSeqTriples)> {
let Size = 384;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR3RegClassID, 0, 32>";
}
def ZPR4 : RegisterClass<"AArch64", [untyped], 128, (add ZSeqQuads)> {
let Size = 512;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR4RegClassID, 0, 32>";
}
class ZPRVectorList<int ElementWidth, int NumRegs> : AsmOperandClass {
@@ -1379,10 +1422,12 @@ def ZStridedQuadsHi : RegisterTuples<[zsub0, zsub1, zsub2, zsub3], [
def ZPR2Strided : RegisterClass<"AArch64", [untyped], 128,
(add ZStridedPairsLo, ZStridedPairsHi)> {
let Size = 256;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR2StridedRegClassID, 0, 16>";
}
def ZPR4Strided : RegisterClass<"AArch64", [untyped], 128,
(add ZStridedQuadsLo, ZStridedQuadsHi)> {
let Size = 512;
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR4StridedRegClassID, 0, 8>";
}
def ZPR2StridedOrContiguous : RegisterClass<"AArch64", [untyped], 128,
@@ -1401,7 +1446,7 @@ class ZPRVectorListStrided<int ElementWidth, int NumRegs, int Stride>
}
let EncoderMethod = "EncodeZPR2StridedRegisterClass",
- DecoderMethod = "DecodeZPR2StridedRegisterClass" in {
+ DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR2StridedRegClassID, 0, 16>" in {
def ZZ_b_strided
: RegisterOperand<ZPR2Strided, "printTypedVectorList<0, 'b'>"> {
let ParserMatchClass = ZPRVectorListStrided<8, 2, 8>;
@@ -1439,7 +1484,7 @@ def ZPR4StridedOrContiguous : RegisterClass<"AArch64", [untyped], 128,
}
let EncoderMethod = "EncodeZPR4StridedRegisterClass",
- DecoderMethod = "DecodeZPR4StridedRegisterClass" in {
+ DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR4StridedRegClassID, 0, 16>" in {
def ZZZZ_b_strided
: RegisterOperand<ZPR4Strided, "printTypedVectorList<0,'b'>"> {
let ParserMatchClass = ZPRVectorListStrided<8, 4, 4>;
@@ -1774,9 +1819,11 @@ def MatrixTileList : MatrixTileListOperand<>;
def MatrixIndexGPR32_8_11 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 8, 11)> {
let DiagnosticType = "InvalidMatrixIndexGPR32_8_11";
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::MatrixIndexGPR32_8_11RegClassID, 0, 4>";
}
def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)> {
let DiagnosticType = "InvalidMatrixIndexGPR32_12_15";
+ let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::MatrixIndexGPR32_12_15RegClassID, 0, 4>";
}
def MatrixIndexGPR32Op8_11 : RegisterOperand<MatrixIndexGPR32_8_11> {
let EncoderMethod = "encodeMatrixIndexGPR32<AArch64::W8>";
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index ddb875e73ff5a..b97f00c993112 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -38,100 +38,19 @@ using DecodeStatus = MCDisassembler::DecodeStatus;
// Forward declare these because the autogenerated code will reference them.
// Definitions are further down.
-static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
+template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
+static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder);
-static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
static DecodeStatus
DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
const MCDisassembler *Decoder);
-static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address, const void *Decoder);
-static DecodeStatus
-DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
-static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
template <unsigned NumBitsForTile>
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
uint64_t Address,
@@ -140,24 +59,6 @@ static DecodeStatus
DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
uint64_t Address,
const MCDisassembler *Decoder);
-static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo,
- ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/97412
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