[llvm] [RISCV] Implement Intrinsics Support for XCValu Extension in CV32E40P (PR #85603)

[Craig Topper via llvm-commits]

================
@@ -705,6 +705,8 @@ let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {
 def cv_tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
 def cv_tuimm5 : TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
 def cv_uimm10 : ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]>;
+def cv_uimm_pow2: Operand<XLenVT>,
----------------
topperc wrote:

Is this used?

https://github.com/llvm/llvm-project/pull/85603