[llvm] [RISCV] Use EXTLOAD instead of ZEXTLOAD when lowering riscv_masked_strided_load with zero stride. (PR #97317)

[Craig Topper via llvm-commits]

topperc wrote:

> To make sure I understand the reasoning here, let me restate. This is correct because the splat operation works on the element type (not the potentially wider register type), and thus the high bits of the loaded value are fully don't care?
> 
> Assuming that's a correct restatement, LGTM.

That's correct.

https://github.com/llvm/llvm-project/pull/97317