[llvm] [AMDGPU] In instruction selector, allow copy from physical reg to s1 (PR #96157)

[Matt Arsenault via llvm-commits]

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@@ -131,6 +131,16 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
   Register SrcReg = Src.getReg();
 
   if (isVCC(DstReg, *MRI)) {
+    // In planned update of calling convention, i1 arguments/returns are
+    // assigned to SGPRs without promoting to i32. The following if statement
+    // allows insturctions such as "%0:sreg_64_xexec(s1) = COPY $sgpr4_sgpr5"
+    // to be accepted.
+    if (SrcReg.isPhysical() && SrcReg != AMDGPU::SCC) {
+      const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DstReg);
+      if (DstRC)
+        return DstRC->contains(SrcReg);
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arsenm wrote:

The calling convention handling is not the sole source of these copies.

You cannot rely on there being no register class here. Depending on whether there is a use instruction that has been constrained or not, and depending on whatever upstream MIR producer produced, either operand may be a physical register, or a virtual register with a register class and type, or a virtual register with a register bank and type. 

You cannot rely on there being a class or bank. You need to use the class or bank, plus the virtual register type to determine the class. The s1 case is somewhat special because in that case we cannot unambiguously go from type to VCC or SGPR.

Again this needs a MIR test, and then you can enumerate all the possibilities and make sure they all work. 

https://github.com/llvm/llvm-project/pull/96157