[llvm] [X86][MC] Added support for -msse2avx option in llvm-mc (PR #96860)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 1 05:56:40 PDT 2024
https://github.com/JaydeepChauhan14 updated https://github.com/llvm/llvm-project/pull/96860
>From b4a534ad6f811cf0868b7fd1ee641fae8502e171 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinbhai at intel.com>
Date: Thu, 27 Jun 2024 15:17:50 +0800
Subject: [PATCH 1/6] [X86][MC] Added support for -msse2avx option in llvm-mc
---
llvm/include/llvm/MC/MCTargetOptions.h | 1 +
.../llvm/MC/MCTargetOptionsCommandFlags.h | 2 +
llvm/lib/MC/MCTargetOptions.cpp | 2 +-
llvm/lib/MC/MCTargetOptionsCommandFlags.cpp | 6 ++
.../lib/Target/X86/AsmParser/X86AsmParser.cpp | 20 +++++
llvm/test/MC/AsmParser/sse2avx.s | 74 +++++++++++++++++++
.../utils/TableGen/X86InstrMappingEmitter.cpp | 28 +++++++
7 files changed, 132 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/MC/AsmParser/sse2avx.s
diff --git a/llvm/include/llvm/MC/MCTargetOptions.h b/llvm/include/llvm/MC/MCTargetOptions.h
index 0cf2806bd4804..90fe356d47077 100644
--- a/llvm/include/llvm/MC/MCTargetOptions.h
+++ b/llvm/include/llvm/MC/MCTargetOptions.h
@@ -55,6 +55,7 @@ class MCTargetOptions {
bool ShowMCEncoding : 1;
bool ShowMCInst : 1;
bool AsmVerbose : 1;
+ bool SSE2AVX : 1;
/// Preserve Comments in Assembly.
bool PreserveAsmComments : 1;
diff --git a/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h b/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
index dc33f7461ab28..2b5f74fc6c1d8 100644
--- a/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
+++ b/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
@@ -41,6 +41,8 @@ bool getEmitCompactUnwindNonCanonical();
bool getShowMCInst();
+bool getSSE2AVX();
+
bool getFatalWarnings();
bool getNoWarn();
diff --git a/llvm/lib/MC/MCTargetOptions.cpp b/llvm/lib/MC/MCTargetOptions.cpp
index bff4b8da2fb1b..227d9fc347e71 100644
--- a/llvm/lib/MC/MCTargetOptions.cpp
+++ b/llvm/lib/MC/MCTargetOptions.cpp
@@ -16,7 +16,7 @@ MCTargetOptions::MCTargetOptions()
MCNoWarn(false), MCNoDeprecatedWarn(false), MCNoTypeCheck(false),
MCSaveTempLabels(false), MCIncrementalLinkerCompatible(false),
FDPIC(false), ShowMCEncoding(false), ShowMCInst(false), AsmVerbose(false),
- PreserveAsmComments(true), Dwarf64(false),
+ SSE2AVX(false), PreserveAsmComments(true), Dwarf64(false),
EmitDwarfUnwind(EmitDwarfUnwindType::Default),
MCUseDwarfDirectory(DefaultDwarfDirectory),
EmitCompactUnwindNonCanonical(false), PPCUseFullRegisterNames(false) {}
diff --git a/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp b/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
index 2c378643797da..6de42fa981e6d 100644
--- a/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
+++ b/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
@@ -42,6 +42,7 @@ MCOPT(bool, Dwarf64)
MCOPT(EmitDwarfUnwindType, EmitDwarfUnwind)
MCOPT(bool, EmitCompactUnwindNonCanonical)
MCOPT(bool, ShowMCInst)
+MCOPT(bool, SSE2AVX)
MCOPT(bool, FatalWarnings)
MCOPT(bool, NoWarn)
MCOPT(bool, NoDeprecatedWarn)
@@ -107,6 +108,10 @@ llvm::mc::RegisterMCTargetOptionsFlags::RegisterMCTargetOptionsFlags() {
cl::desc("Emit internal instruction representation to assembly file"));
MCBINDOPT(ShowMCInst);
+ static cl::opt<bool> SSE2AVX(
+ "msse2avx", cl::desc("Convert SSE Instructions to AVX Instructions"));
+ MCBINDOPT(SSE2AVX);
+
static cl::opt<bool> FatalWarnings("fatal-warnings",
cl::desc("Treat warnings as errors"));
MCBINDOPT(FatalWarnings);
@@ -156,6 +161,7 @@ MCTargetOptions llvm::mc::InitMCTargetOptionsFromFlags() {
Options.Dwarf64 = getDwarf64();
Options.DwarfVersion = getDwarfVersion();
Options.ShowMCInst = getShowMCInst();
+ Options.SSE2AVX = getSSE2AVX();
Options.ABIName = getABIName();
Options.MCFatalWarnings = getFatalWarnings();
Options.MCNoWarn = getNoWarn();
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index dbea42d55b5fc..ab70fdbc70caa 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -58,6 +58,10 @@ static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
namespace {
+// Including the generated SSE2AVX compression tables.
+#define GET_X86_SSE2AVX_TABLE
+#include "X86GenInstrMapping.inc"
+
static const char OpPrecedence[] = {
0, // IC_OR
1, // IC_XOR
@@ -4141,6 +4145,15 @@ unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
return Match_Success;
}
+void ReplaceSSE2AVXOpcode(llvm::MCInst &Inst) {
+ ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_bound(Table, Opcode);
+ if (I != Table.end() && I->OldOpc == Opcode) {
+ Inst.setOpcode(I->NewOpc);
+ }
+}
+
bool X86AsmParser::matchAndEmitATTInstruction(
SMLoc IDLoc, unsigned &Opcode, MCInst &Inst, OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) {
@@ -4159,6 +4172,13 @@ bool X86AsmParser::matchAndEmitATTInstruction(
SwitchMode(X86::Is16Bit);
ForcedDataPrefix = 0;
}
+
+ // When "-msse2avx" option is enabled ReplaceSSE2AVXOpcode method will
+ // replace SSE instruction with equivalent AVX instruction using mapping given
+ // in table GET_X86_SSE2AVX_TABLE
+ if (MCOptions.SSE2AVX)
+ ReplaceSSE2AVXOpcode(Inst);
+
switch (OriginalError) {
default: llvm_unreachable("Unexpected match result!");
case Match_Success:
diff --git a/llvm/test/MC/AsmParser/sse2avx.s b/llvm/test/MC/AsmParser/sse2avx.s
new file mode 100644
index 0000000000000..ee0c1251478b3
--- /dev/null
+++ b/llvm/test/MC/AsmParser/sse2avx.s
@@ -0,0 +1,74 @@
+# RUN: llvm-mc -triple x86_64-unknown-unknown -msse2avx %s | FileCheck %s
+ .text
+# CHECK: vmovsd -352(%rbp), %xmm0
+ movsd -352(%rbp), %xmm0 # xmm0 = mem[0],zero
+# CHECK-NEXT: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[0]
+ unpcklpd %xmm1, %xmm0 # xmm0 = xmm0[0],xmm1[0]
+# CHECK-NEXT: vmovapd %xmm0, -368(%rbp)
+ movapd %xmm0, -368(%rbp)
+# CHECK-NEXT: vmovapd -368(%rbp), %xmm0
+ movapd -368(%rbp), %xmm0
+# CHECK-NEXT: vmovsd -376(%rbp), %xmm1
+ movsd -376(%rbp), %xmm1 # xmm1 = mem[0],zero
+# CHECK-NEXT: vmovsd -384(%rbp), %xmm0
+ movsd -384(%rbp), %xmm0 # xmm0 = mem[0],zero
+# CHECK-NEXT: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[0]
+ unpcklpd %xmm1, %xmm0 # xmm0 = xmm0[0],xmm1[0]
+# CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm0
+ addpd %xmm1, %xmm0
+# CHECK-NEXT: vmovapd %xmm0, -464(%rbp)
+ movapd %xmm0, -464(%rbp)
+# CHECK-NEXT: vmovaps -304(%rbp), %xmm1
+ movaps -304(%rbp), %xmm1
+# CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0
+ pandn %xmm1, %xmm0
+# CHECK-NEXT: vmovaps %xmm0, -480(%rbp)
+ movaps %xmm0, -480(%rbp)
+# CHECK-NEXT: vmovss -220(%rbp), %xmm1
+ movss -220(%rbp), %xmm1 # xmm1 = mem[0],zero,zero,zero
+# CHECK-NEXT: vinsertps $16, %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+ insertps $16, %xmm1, %xmm0 # xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+# CHECK-NEXT: vmovaps %xmm0, -496(%rbp)
+ movaps %xmm0, -496(%rbp)
+# CHECK-NEXT: vmovss -256(%rbp), %xmm0
+ movss -256(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
+# CHECK-NEXT: vmovaps -192(%rbp), %xmm0
+ movaps -192(%rbp), %xmm0
+# CHECK-NEXT: vdivss %xmm1, %xmm0, %xmm0
+ divss %xmm1, %xmm0
+# CHECK-NEXT: vmovaps %xmm0, -192(%rbp)
+ movaps %xmm0, -192(%rbp)
+# CHECK-NEXT: vmovd -128(%rbp), %xmm0
+ movd -128(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
+# CHECK-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0
+ pinsrd $1, %edx, %xmm0
+# CHECK-NEXT: vmovaps %xmm0, -144(%rbp)
+ movaps %xmm0, -144(%rbp)
+# CHECK-NEXT: vmovd -160(%rbp), %xmm0
+ movd -160(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
+# CHECK-NEXT: vpblendw $170, %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+ pblendw $170, %xmm1, %xmm0 # xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+# CHECK-NEXT: vmovdqa %xmm0, -576(%rbp)
+ movdqa %xmm0, -576(%rbp)
+# CHECK-NEXT: vphsubw %xmm1, %xmm0, %xmm0
+ phsubw %xmm1, %xmm0
+# CHECK-NEXT: vmovdqa %xmm0, -592(%rbp)
+ movdqa %xmm0, -592(%rbp)
+# CHECK-NEXT: vmovaps -496(%rbp), %xmm0
+ movaps -496(%rbp), %xmm0
+# CHECK-NEXT: vroundps $8, %xmm0, %xmm0
+ roundps $8, %xmm0, %xmm0
+# CHECK-NEXT: vmovaps %xmm0, -608(%rbp)
+ movaps %xmm0, -608(%rbp)
+# CHECK-NEXT: vmovapd -432(%rbp), %xmm0
+ movapd -432(%rbp), %xmm0
+# CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
+ pxor %xmm1, %xmm0
+# CHECK-NEXT: vmovaps %xmm0, -640(%rbp)
+ movaps %xmm0, -640(%rbp)
+# CHECK-NEXT: vmovapd -32(%rbp), %xmm0
+ movapd -32(%rbp), %xmm0
+# CHECK-NEXT: vmovupd %xmm0, (%rax)
+ movupd %xmm0, (%rax)
+# CHECK-NEXT: vmovsd -656(%rbp), %xmm0
+ movsd -656(%rbp), %xmm0 # xmm0 = mem[0],zero
diff --git a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
index 950ff1394b9fd..770943177551f 100644
--- a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
+++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
@@ -56,6 +56,8 @@ class X86InstrMappingEmitter {
raw_ostream &OS);
void emitND2NonNDTable(ArrayRef<const CodeGenInstruction *> Insts,
raw_ostream &OS);
+ void emitSSE2AVXTable(ArrayRef<const CodeGenInstruction *> Insts,
+ raw_ostream &OS);
// Prints the definition of class X86TableEntry.
void printClassDef(raw_ostream &OS);
@@ -335,6 +337,31 @@ void X86InstrMappingEmitter::emitND2NonNDTable(
printTable(Table, "X86ND2NonNDTable", "GET_X86_ND2NONND_TABLE", OS);
}
+// Method emitSSE2AVXTable will create table GET_X86_SSE2AVX_TABLE for SSE to
+// AVX instruction mapping in X86GenInstrMapping.inc file, In table first entry
+// will be SSE instruction and second entry will be equivalent AVX instruction
+// Example:- "{ X86::ADDPDrm, X86::VADDPDrm },"
+void X86InstrMappingEmitter::emitSSE2AVXTable(
+ ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
+ std::vector<Entry> Table;
+ for (const CodeGenInstruction *Inst : Insts) {
+ const Record *Rec = Inst->TheDef;
+ StringRef Name = Rec->getName();
+
+ auto *NewRec = Records.getDef(Name);
+ if (!NewRec)
+ continue;
+
+ std::string NewName = ("V" + Name).str();
+ auto *AVXRec = Records.getDef(NewName);
+ if (!AVXRec)
+ continue;
+ auto &AVXInst = Target.getInstruction(AVXRec);
+ Table.push_back(std::pair(Inst, &AVXInst));
+ }
+ printTable(Table, "X86SSE2AVXTable", "GET_X86_SSE2AVX_TABLE", OS);
+}
+
void X86InstrMappingEmitter::run(raw_ostream &OS) {
emitSourceFileHeader("X86 instruction mapping", OS);
@@ -344,6 +371,7 @@ void X86InstrMappingEmitter::run(raw_ostream &OS) {
emitCompressEVEXTable(Insts, OS);
emitNFTransformTable(Insts, OS);
emitND2NonNDTable(Insts, OS);
+ emitSSE2AVXTable(Insts, OS);
}
} // namespace
>From 95021b655437c68b9874049b66fcadcd3a6b24b8 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinbhai at intel.com>
Date: Fri, 28 Jun 2024 13:27:14 +0800
Subject: [PATCH 2/6] Addressd review comments
---
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 6 +++---
llvm/test/MC/AsmParser/sse2avx.s | 6 ++++++
llvm/utils/TableGen/X86InstrMappingEmitter.cpp | 7 ++-----
3 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index ab70fdbc70caa..50cc9ee919fcf 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -4145,7 +4145,7 @@ unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
return Match_Success;
}
-void ReplaceSSE2AVXOpcode(llvm::MCInst &Inst) {
+void replaceSSE2AVXOpcode(llvm::MCInst &Inst) {
ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
unsigned Opcode = Inst.getOpcode();
const auto I = llvm::lower_bound(Table, Opcode);
@@ -4173,11 +4173,11 @@ bool X86AsmParser::matchAndEmitATTInstruction(
ForcedDataPrefix = 0;
}
- // When "-msse2avx" option is enabled ReplaceSSE2AVXOpcode method will
+ // When "-msse2avx" option is enabled replaceSSE2AVXOpcode method will
// replace SSE instruction with equivalent AVX instruction using mapping given
// in table GET_X86_SSE2AVX_TABLE
if (MCOptions.SSE2AVX)
- ReplaceSSE2AVXOpcode(Inst);
+ replaceSSE2AVXOpcode(Inst);
switch (OriginalError) {
default: llvm_unreachable("Unexpected match result!");
diff --git a/llvm/test/MC/AsmParser/sse2avx.s b/llvm/test/MC/AsmParser/sse2avx.s
index ee0c1251478b3..29f2181dfcce8 100644
--- a/llvm/test/MC/AsmParser/sse2avx.s
+++ b/llvm/test/MC/AsmParser/sse2avx.s
@@ -72,3 +72,9 @@
movupd %xmm0, (%rax)
# CHECK-NEXT: vmovsd -656(%rbp), %xmm0
movsd -656(%rbp), %xmm0 # xmm0 = mem[0],zero
+# CHECK-NEXT: extrq $16, $8, %xmm0 # xmm0 = xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
+ extrq $16, $8, %xmm0
+# CHECK-NEXT: insertq $16, $8, %xmm1, %xmm0 # xmm0 = xmm0[0,1],xmm1[0],xmm0[3,4,5,6,7,u,u,u,u,u,u,u,u]
+ insertq $16, $8, %xmm1, %xmm0
+# CHECK-NEXT: pshufw $1, %mm0, %mm2 # mm2 = mm0[1,0,0,0]
+ pshufw $1, %mm0, %mm2
diff --git a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
index 770943177551f..90611de641f30 100644
--- a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
+++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
@@ -337,17 +337,14 @@ void X86InstrMappingEmitter::emitND2NonNDTable(
printTable(Table, "X86ND2NonNDTable", "GET_X86_ND2NONND_TABLE", OS);
}
-// Method emitSSE2AVXTable will create table GET_X86_SSE2AVX_TABLE for SSE to
-// AVX instruction mapping in X86GenInstrMapping.inc file, In table first entry
-// will be SSE instruction and second entry will be equivalent AVX instruction
-// Example:- "{ X86::ADDPDrm, X86::VADDPDrm },"
void X86InstrMappingEmitter::emitSSE2AVXTable(
ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
std::vector<Entry> Table;
for (const CodeGenInstruction *Inst : Insts) {
const Record *Rec = Inst->TheDef;
StringRef Name = Rec->getName();
-
+ if (!isInteresting(Rec))
+ continue;
auto *NewRec = Records.getDef(Name);
if (!NewRec)
continue;
>From 0bf7123acbdae06ebccfc105607b0ccec778c127 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinbhai at intel.com>
Date: Fri, 28 Jun 2024 20:48:41 +0800
Subject: [PATCH 3/6] Added support for intel syntax
---
.../lib/Target/X86/AsmParser/X86AsmParser.cpp | 6 ++
llvm/test/MC/AsmParser/sse2avx-intel.s | 80 +++++++++++++++++++
2 files changed, 86 insertions(+)
create mode 100644 llvm/test/MC/AsmParser/sse2avx-intel.s
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 50cc9ee919fcf..644ed451cb18e 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -4513,6 +4513,12 @@ bool X86AsmParser::matchAndEmitIntelInstruction(
/*Len=*/0, UnsizedMemOp->getMemFrontendSize());
}
+ // When "-msse2avx" option is enabled replaceSSE2AVXOpcode method will
+ // replace SSE instruction with equivalent AVX instruction using mapping given
+ // in table GET_X86_SSE2AVX_TABLE
+ if (MCOptions.SSE2AVX)
+ replaceSSE2AVXOpcode(Inst);
+
// If exactly one matched, then we treat that as a successful match (and the
// instruction will already have been filled in correctly, since the failing
// matches won't have modified it).
diff --git a/llvm/test/MC/AsmParser/sse2avx-intel.s b/llvm/test/MC/AsmParser/sse2avx-intel.s
new file mode 100644
index 0000000000000..72f3638a41a81
--- /dev/null
+++ b/llvm/test/MC/AsmParser/sse2avx-intel.s
@@ -0,0 +1,80 @@
+# RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -msse2avx %s | FileCheck %s
+ .text
+# CHECK: vmovsd -352(%rbp), %xmm0
+ movsd xmm0, qword ptr [rbp - 352] # xmm0 = mem[0],zero
+# CHECK-NEXT: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[0]
+ unpcklpd xmm0, xmm1 # xmm0 = xmm0[0],xmm1[0]
+# CHECK-NEXT: vmovapd %xmm0, -368(%rbp)
+ movapd xmmword ptr [rbp - 368], xmm0
+# CHECK-NEXT: vmovapd -368(%rbp), %xmm0
+ movapd xmm0, xmmword ptr [rbp - 368]
+# CHECK-NEXT: vmovapd %xmm0, -432(%rbp)
+ movapd xmmword ptr [rbp - 432], xmm0
+# CHECK-NEXT: movabsq $4613937818241073152, %rax # imm = 0x4008000000000000
+ movabs rax, 4613937818241073152
+# CHECK-NEXT: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[0]
+ unpcklpd xmm0, xmm1 # xmm0 = xmm0[0],xmm1[0]
+# CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm0
+ addpd xmm0, xmm1
+# CHECK-NEXT: vmovapd %xmm0, -464(%rbp)
+ movapd xmmword ptr [rbp - 464], xmm0
+# CHECK-NEXT: vmovaps -304(%rbp), %xmm1
+ movaps xmm1, xmmword ptr [rbp - 304]
+# CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0
+ pandn xmm0, xmm1
+# CHECK-NEXT: vmovaps %xmm0, -480(%rbp)
+ movaps xmmword ptr [rbp - 480], xmm0
+# CHECK-NEXT: vmovss -220(%rbp), %xmm1
+ movss xmm1, dword ptr [rbp - 220] # xmm1 = mem[0],zero,zero,zero
+# CHECK-NEXT: vinsertps $16, %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+ insertps xmm0, xmm1, 16 # xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+# CHECK-NEXT: vmovaps %xmm0, -496(%rbp)
+ movaps xmmword ptr [rbp - 496], xmm0
+# CHECK-NEXT: vmovss -252(%rbp), %xmm1
+ movss xmm1, dword ptr [rbp - 252] # xmm1 = mem[0],zero,zero,zero
+# CHECK-NEXT: vmovaps %xmm1, -192(%rbp)
+ movaps xmmword ptr [rbp - 192], xmm1
+# CHECK-NEXT: vdivss %xmm1, %xmm0, %xmm0
+ divss xmm0, xmm1
+# CHECK-NEXT: vmovaps %xmm0, -192(%rbp)
+ movaps xmmword ptr [rbp - 192], xmm0
+# CHECK-NEXT: vmovd -128(%rbp), %xmm0
+ movd xmm0, dword ptr [rbp - 128] # xmm0 = mem[0],zero,zero,zero
+# CHECK-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0
+ pinsrd xmm0, edx, 1
+# CHECK-NEXT: vmovaps %xmm0, -144(%rbp)
+ movaps xmmword ptr [rbp - 144], xmm0
+# CHECK-NEXT: vmovd -160(%rbp), %xmm0
+ movd xmm0, dword ptr [rbp - 160] # xmm0 = mem[0],zero,zero,zero
+# CHECK-NEXT: vpblendw $170, %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+ pblendw xmm0, xmm1, 170 # xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+# CHECK-NEXT: vmovdqa %xmm0, -576(%rbp)
+ movdqa xmmword ptr [rbp - 576], xmm0
+# CHECK-NEXT: vphsubw %xmm1, %xmm0, %xmm0
+ phsubw xmm0, xmm1
+# CHECK-NEXT: vmovdqa %xmm0, -592(%rbp)
+ movdqa xmmword ptr [rbp - 592], xmm0
+# CHECK-NEXT: vmovaps -496(%rbp), %xmm0
+ movaps xmm0, xmmword ptr [rbp - 496]
+# CHECK-NEXT: vroundps $8, %xmm0, %xmm0
+ roundps xmm0, xmm0, 8
+# CHECK-NEXT: vmovaps %xmm0, -608(%rbp)
+ movaps xmmword ptr [rbp - 608], xmm0
+# CHECK-NEXT: vmovapd -432(%rbp), %xmm0
+ movapd xmm0, xmmword ptr [rbp - 432]
+# CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
+ pxor xmm0, xmm1
+# CHECK-NEXT: vmovaps %xmm0, -640(%rbp)
+ movaps xmmword ptr [rbp - 640], xmm0
+# CHECK-NEXT: vmovapd %xmm0, -32(%rbp)
+ movapd xmmword ptr [rbp - 32], xmm0
+# CHECK-NEXT: vmovupd %xmm0, (%rax)
+ movupd xmmword ptr [rax], xmm0
+# CHECK-NEXT: vmovsd -656(%rbp), %xmm0
+ movsd xmm0, qword ptr [rbp - 656] # xmm0 = mem[0],zero
+# CHECK-NEXT: extrq $8, $16, %xmm0 # xmm0 = xmm0[1,2],zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
+ extrq xmm0, 16, 8
+# CHECK-NEXT: insertq $8, $16, %xmm1, %xmm0 # xmm0 = xmm0[0],xmm1[0,1],xmm0[3,4,5,6,7,u,u,u,u,u,u,u,u]
+ insertq xmm0, xmm1, 16, 8
+# CHECK-NEXT: pshufw $1, %mm0, %mm2 # mm2 = mm0[1,0,0,0]
+ pshufw mm2, mm0, 1
>From 8f2a402acd8aeede670d35e16159d31596363c37 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinbhai at intel.com>
Date: Fri, 28 Jun 2024 23:40:30 +0800
Subject: [PATCH 4/6] Moved replaceSSE2AVXOpcode inside
X86AsmParser::processInstruction
---
.../lib/Target/X86/AsmParser/X86AsmParser.cpp | 36 ++++++++-----------
llvm/test/MC/AsmParser/sse2avx-intel.s | 4 +--
2 files changed, 17 insertions(+), 23 deletions(-)
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 644ed451cb18e..304758ad989d1 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -3749,7 +3749,22 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
return false;
}
+void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_bound(Table, Opcode);
+ if (I != Table.end() && I->OldOpc == Opcode) {
+ Inst.setOpcode(I->NewOpc);
+ }
+}
+
bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
+ // When "-msse2avx" option is enabled replaceSSE2AVXOpcode method will
+ // replace SSE instruction with equivalent AVX instruction using mapping given
+ // in table GET_X86_SSE2AVX_TABLE
+ if (MCOptions.SSE2AVX)
+ replaceSSE2AVXOpcode(Inst);
+
if (ForcedOpcodePrefix != OpcodePrefix_VEX3 &&
X86::optimizeInstFromVEX3ToVEX2(Inst, MII.get(Inst.getOpcode())))
return true;
@@ -4145,15 +4160,6 @@ unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
return Match_Success;
}
-void replaceSSE2AVXOpcode(llvm::MCInst &Inst) {
- ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
- unsigned Opcode = Inst.getOpcode();
- const auto I = llvm::lower_bound(Table, Opcode);
- if (I != Table.end() && I->OldOpc == Opcode) {
- Inst.setOpcode(I->NewOpc);
- }
-}
-
bool X86AsmParser::matchAndEmitATTInstruction(
SMLoc IDLoc, unsigned &Opcode, MCInst &Inst, OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) {
@@ -4173,12 +4179,6 @@ bool X86AsmParser::matchAndEmitATTInstruction(
ForcedDataPrefix = 0;
}
- // When "-msse2avx" option is enabled replaceSSE2AVXOpcode method will
- // replace SSE instruction with equivalent AVX instruction using mapping given
- // in table GET_X86_SSE2AVX_TABLE
- if (MCOptions.SSE2AVX)
- replaceSSE2AVXOpcode(Inst);
-
switch (OriginalError) {
default: llvm_unreachable("Unexpected match result!");
case Match_Success:
@@ -4513,12 +4513,6 @@ bool X86AsmParser::matchAndEmitIntelInstruction(
/*Len=*/0, UnsizedMemOp->getMemFrontendSize());
}
- // When "-msse2avx" option is enabled replaceSSE2AVXOpcode method will
- // replace SSE instruction with equivalent AVX instruction using mapping given
- // in table GET_X86_SSE2AVX_TABLE
- if (MCOptions.SSE2AVX)
- replaceSSE2AVXOpcode(Inst);
-
// If exactly one matched, then we treat that as a successful match (and the
// instruction will already have been filled in correctly, since the failing
// matches won't have modified it).
diff --git a/llvm/test/MC/AsmParser/sse2avx-intel.s b/llvm/test/MC/AsmParser/sse2avx-intel.s
index 72f3638a41a81..11d25089c250a 100644
--- a/llvm/test/MC/AsmParser/sse2avx-intel.s
+++ b/llvm/test/MC/AsmParser/sse2avx-intel.s
@@ -16,7 +16,7 @@
unpcklpd xmm0, xmm1 # xmm0 = xmm0[0],xmm1[0]
# CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm0
addpd xmm0, xmm1
-# CHECK-NEXT: vmovapd %xmm0, -464(%rbp)
+# CHECK-NEXT: vmovapd %xmm0, -464(%rbp)
movapd xmmword ptr [rbp - 464], xmm0
# CHECK-NEXT: vmovaps -304(%rbp), %xmm1
movaps xmm1, xmmword ptr [rbp - 304]
@@ -50,7 +50,7 @@
pblendw xmm0, xmm1, 170 # xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
# CHECK-NEXT: vmovdqa %xmm0, -576(%rbp)
movdqa xmmword ptr [rbp - 576], xmm0
-# CHECK-NEXT: vphsubw %xmm1, %xmm0, %xmm0
+# CHECK-NEXT: vphsubw %xmm1, %xmm0, %xmm0
phsubw xmm0, xmm1
# CHECK-NEXT: vmovdqa %xmm0, -592(%rbp)
movdqa xmmword ptr [rbp - 592], xmm0
>From c90119457e7c71167bdaf3f319ba8015b5cabd34 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinbhai at intel.com>
Date: Sat, 29 Jun 2024 19:35:09 +0800
Subject: [PATCH 5/6] Addressed review comments
---
llvm/include/llvm/MC/MCTargetOptions.h | 3 ++-
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 6 ++----
llvm/test/MC/AsmParser/sse2avx-intel.s | 2 +-
llvm/test/MC/AsmParser/sse2avx.s | 2 +-
4 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/llvm/include/llvm/MC/MCTargetOptions.h b/llvm/include/llvm/MC/MCTargetOptions.h
index 90fe356d47077..8ac96c64f0786 100644
--- a/llvm/include/llvm/MC/MCTargetOptions.h
+++ b/llvm/include/llvm/MC/MCTargetOptions.h
@@ -55,7 +55,6 @@ class MCTargetOptions {
bool ShowMCEncoding : 1;
bool ShowMCInst : 1;
bool AsmVerbose : 1;
- bool SSE2AVX : 1;
/// Preserve Comments in Assembly.
bool PreserveAsmComments : 1;
@@ -66,6 +65,8 @@ class MCTargetOptions {
// ELF.
bool X86RelaxRelocations = true;
+ bool SSE2AVX : 1;
+
EmitDwarfUnwindType EmitDwarfUnwind;
int DwarfVersion = 0;
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 304758ad989d1..c425067e085ce 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -3749,13 +3749,12 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
return false;
}
-void replaceSSE2AVXOpcode(MCInst &Inst) {
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
unsigned Opcode = Inst.getOpcode();
const auto I = llvm::lower_bound(Table, Opcode);
- if (I != Table.end() && I->OldOpc == Opcode) {
+ if (I != Table.end() && I->OldOpc == Opcode)
Inst.setOpcode(I->NewOpc);
- }
}
bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
@@ -4178,7 +4177,6 @@ bool X86AsmParser::matchAndEmitATTInstruction(
SwitchMode(X86::Is16Bit);
ForcedDataPrefix = 0;
}
-
switch (OriginalError) {
default: llvm_unreachable("Unexpected match result!");
case Match_Success:
diff --git a/llvm/test/MC/AsmParser/sse2avx-intel.s b/llvm/test/MC/AsmParser/sse2avx-intel.s
index 11d25089c250a..69198e0ca42ce 100644
--- a/llvm/test/MC/AsmParser/sse2avx-intel.s
+++ b/llvm/test/MC/AsmParser/sse2avx-intel.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -msse2avx %s | FileCheck %s
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -msse2avx %s | FileCheck %s
.text
# CHECK: vmovsd -352(%rbp), %xmm0
movsd xmm0, qword ptr [rbp - 352] # xmm0 = mem[0],zero
diff --git a/llvm/test/MC/AsmParser/sse2avx.s b/llvm/test/MC/AsmParser/sse2avx.s
index 29f2181dfcce8..a21ca6529cabd 100644
--- a/llvm/test/MC/AsmParser/sse2avx.s
+++ b/llvm/test/MC/AsmParser/sse2avx.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple x86_64-unknown-unknown -msse2avx %s | FileCheck %s
+# RUN: llvm-mc -triple x86_64 -msse2avx %s | FileCheck %s
.text
# CHECK: vmovsd -352(%rbp), %xmm0
movsd -352(%rbp), %xmm0 # xmm0 = mem[0],zero
>From 3623d8d0693009c2b8121fcc11fb2420dd46bed8 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinbhai at intel.com>
Date: Mon, 1 Jul 2024 20:55:59 +0800
Subject: [PATCH 6/6] Added support for instructions BLENDVPD,BLENDVPS,PBLENDVB
---
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 6 ++++++
llvm/test/MC/AsmParser/sse2avx.s | 6 ++++++
llvm/utils/TableGen/X86InstrMappingEmitter.cpp | 3 +++
3 files changed, 15 insertions(+)
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index c425067e085ce..8212adee4574d 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -3755,6 +3755,12 @@ static void replaceSSE2AVXOpcode(MCInst &Inst) {
const auto I = llvm::lower_bound(Table, Opcode);
if (I != Table.end() && I->OldOpc == Opcode)
Inst.setOpcode(I->NewOpc);
+
+ if (X86::isBLENDVPD(Opcode) || X86::isBLENDVPS(Opcode) ||
+ X86::isPBLENDVB(Opcode)) {
+ unsigned RegNo = Inst.getOperand(2).getReg();
+ Inst.addOperand(MCOperand::createReg(RegNo));
+ }
}
bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
diff --git a/llvm/test/MC/AsmParser/sse2avx.s b/llvm/test/MC/AsmParser/sse2avx.s
index a21ca6529cabd..e514ece1a2613 100644
--- a/llvm/test/MC/AsmParser/sse2avx.s
+++ b/llvm/test/MC/AsmParser/sse2avx.s
@@ -78,3 +78,9 @@
insertq $16, $8, %xmm1, %xmm0
# CHECK-NEXT: pshufw $1, %mm0, %mm2 # mm2 = mm0[1,0,0,0]
pshufw $1, %mm0, %mm2
+# CHECK-NEXT: vpblendvb %xmm2, %xmm2, %xmm1, %xmm1
+ pblendvb %xmm0, %xmm2, %xmm1
+# CHECK-NEXT: vblendvps %xmm0, %xmm0, %xmm2, %xmm2
+ blendvps %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: vblendvpd %xmm0, %xmm0, %xmm2, %xmm2
+ blendvpd %xmm0, %xmm0, %xmm2
diff --git a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
index 90611de641f30..e8039db11d784 100644
--- a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
+++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
@@ -350,6 +350,9 @@ void X86InstrMappingEmitter::emitSSE2AVXTable(
continue;
std::string NewName = ("V" + Name).str();
+ // Handle instructions BLENDVPD, BLENDVPS ,PBLENDVB
+ if (Name.ends_with("rm0") || Name.ends_with("rr0"))
+ NewName.back() = 'r';
auto *AVXRec = Records.getDef(NewName);
if (!AVXRec)
continue;
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