[llvm] [RISCV] Enable encodng conflict framework for RISCV target. (PR #97287)
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Mon Jul 1 05:15:21 PDT 2024
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:warning: C/C++ code formatter, clang-format found issues in your code. :warning:
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You can test this locally with the following command:
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git-clang-format --diff e258bb38dc8f00cc366df877d0e6f869657b7a8b 75c3da27b904c9e1298ecbfd7bd3828618b50eec -- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp llvm/utils/TableGen/SearchableTableEmitter.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index 19cfde4fbd..071f321b66 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -122,7 +122,7 @@ void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNo).getImm();
auto Range = RISCVSysReg::lookupSysRegByEncoding(Imm);
- for(auto It : Range){
+ for (auto It : Range) {
if (It.haveRequiredFeatures(STI.getFeatureBits())) {
markup(O, Markup::Register) << It.Name;
return;
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https://github.com/llvm/llvm-project/pull/97287
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