[llvm] 7b2e16f - [AArch64] Fix scheduling model issue #96394 (#97047)
via llvm-commits
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Mon Jul 1 03:34:27 PDT 2024
Author: David Sherwood
Date: 2024-07-01T11:34:23+01:00
New Revision: 7b2e16f9526107998f5e3459994152a83c452087
URL: https://github.com/llvm/llvm-project/commit/7b2e16f9526107998f5e3459994152a83c452087
DIFF: https://github.com/llvm/llvm-project/commit/7b2e16f9526107998f5e3459994152a83c452087.diff
LOG: [AArch64] Fix scheduling model issue #96394 (#97047)
The NeoverseZeroMove predicate assumes that the first operand is always
an immediate, which isn't always true. For example, it could be a stack
offset, etc. This patch fixes that by checking if the operand is an
immediate first.
Added:
llvm/test/CodeGen/AArch64/misched-move-imm.mir
Modified:
llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
index 97abec10f7942..33b76a4f65f05 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
@@ -60,8 +60,9 @@ def NeoverseZeroMove : MCSchedPredicate<
// MOV Wd, #0
// MOV Xd, #0
CheckAll<[CheckOpcode<[MOVZWi, MOVZXi]>,
- CheckAll<[CheckImmOperand<1, 0>,
- CheckImmOperand<2, 0>]>]>,
+ CheckIsImmOperand<1>,
+ CheckImmOperand<1, 0>,
+ CheckImmOperand<2, 0>]>,
// MOV Wd, WZR
// MOV Xd, XZR
// MOV Wd, Wn
diff --git a/llvm/test/CodeGen/AArch64/misched-move-imm.mir b/llvm/test/CodeGen/AArch64/misched-move-imm.mir
new file mode 100644
index 0000000000000..b5ff01b3c5b13
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/misched-move-imm.mir
@@ -0,0 +1,52 @@
+# RUN: llc -run-pass=machine-scheduler -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 %s -o /dev/null 2>&1
+# Just ensure this doesn't crash. Ensures in the neoverse-v2
+# scheduling model we don't attempt to treat the first input
+# operand of MOVZXi as an immediate operand.
+
+--- |
+ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
+
+ declare void @foo2(<2 x float>) #0
+
+ define void @foo1() #0 {
+ call void @foo2(<2 x float> <float 2.500000e-01, float 7.500000e-01>)
+ ret void
+ }
+
+ attributes #0 = { "target-cpu"="neoverse-v2" }
+
+...
+---
+name: foo1
+alignment: 16
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64 }
+ - { id: 1, class: gpr64 }
+ - { id: 2, class: gpr64common }
+ - { id: 3, class: gpr64common }
+ - { id: 4, class: fpr64 }
+frameInfo:
+ maxAlignment: 1
+ adjustsStack: true
+ hasCalls: true
+ maxCallFrameSize: 0
+constants:
+ - id: 0
+ value: '<2 x i32> <i32 1048576000, i32 1061158912>'
+ alignment: 8
+machineFunctionInfo: {}
+body: |
+ bb.0 (%ir-block.0):
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ %2:gpr64common = MOVZXi target-flags(aarch64-g0, aarch64-nc) %const.0, 0
+ %2:gpr64common = MOVKXi %2, target-flags(aarch64-g1, aarch64-nc) %const.0, 16
+ %2:gpr64common = MOVKXi %2, target-flags(aarch64-g2, aarch64-nc) %const.0, 32
+ %2:gpr64common = MOVKXi %2, target-flags(aarch64-g3) %const.0, 48
+ %4:fpr64 = LDRDui %2, 0 :: (load (s64) from constant-pool)
+ $d0 = COPY %4
+ BL @foo2, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $d0, implicit-def $sp
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ RET_ReallyLR
+
+...
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