[llvm] [SelectionDAG][RISCV] Fix break of vnsrl pattern in issue #94265 (PR #95563)

[Luke Lau via llvm-commits]

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@@ -1884,6 +1884,16 @@ bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {
   return (SrcBits == 64 && DestBits == 32);
 }
 
+bool RISCVTargetLowering::isTruncateFree(SDValue Val, EVT VT2) const {
+  // free truncate from vnsrl and vnsra
+  if (Subtarget.hasStdExtV() &&
+      (Val.getOpcode() == ISD::SRL || Val.getOpcode() == ISD::SRA) &&
+      Val.getValueType().isVector() && VT2.isVector()) {
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lukel97 wrote:

Do we need to check that VT2 is exactly half the size of Val.getValueType()?

https://github.com/llvm/llvm-project/pull/95563