[llvm] [X86] Combine VPERMV3 to VPERMV for i8/i16 (PR #96414)

[Phoebe Wang via llvm-commits]

================
@@ -41273,6 +41273,33 @@ static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL,
 
     return SDValue();
   }
+  case X86ISD::VPERMV3: {
+    // VPERM[I,T]2[B,W] are 3 uops on Skylake and Icelake so we try to use
+    // VPERMV.
+    if (VT.is512BitVector() || (VT.is256BitVector() && !Subtarget.hasEVEX512()))
+      return SDValue();
+    MVT ElementVT = VT.getVectorElementType();
+    if (ElementVT != MVT::i8 && ElementVT != MVT::i16)
+      return SDValue();
----------------
phoebewang wrote:

> Although VPERM2B/W are slower, do would not still avoid an extract subvector by widening D/Q/PS/PD cases?

#97206

https://github.com/llvm/llvm-project/pull/96414