[llvm] eed7c5e - [X86] Peek through bitcast to find more opportunity for VPERMV3 -> VPERMV combine
Phoebe Wang via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 30 02:25:51 PDT 2024
Author: Phoebe Wang
Date: 2024-06-30T17:17:20+08:00
New Revision: eed7c5e29c1dc5f78bd01608430e2b4e0c439bb1
URL: https://github.com/llvm/llvm-project/commit/eed7c5e29c1dc5f78bd01608430e2b4e0c439bb1
DIFF: https://github.com/llvm/llvm-project/commit/eed7c5e29c1dc5f78bd01608430e2b4e0c439bb1.diff
LOG: [X86] Peek through bitcast to find more opportunity for VPERMV3 -> VPERMV combine
A follow up of #96414
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d108c7ea2c51c..1d4af62c3227d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -41336,8 +41336,9 @@ static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL,
case X86ISD::VPERMV3: {
// VPERM[I,T]2[B,W] are 3 uops on Skylake and Icelake so we try to use
// VPERMV.
- SDValue V1 = N.getOperand(0);
- SDValue V2 = N.getOperand(2);
+ SDValue V1 = peekThroughBitcasts(N.getOperand(0));
+ SDValue V2 = peekThroughBitcasts(N.getOperand(2));
+ MVT SVT = V1.getSimpleValueType();
MVT EVT = VT.getVectorElementType();
MVT NVT = VT.getDoubleNumVectorElementsVT();
if ((EVT == MVT::i8 || EVT == MVT::i16) &&
@@ -41346,14 +41347,15 @@ static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL,
V1.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
V1.getConstantOperandVal(1) == 0 &&
V2.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
- V2.getConstantOperandVal(1) == VT.getVectorNumElements() &&
+ V2.getConstantOperandVal(1) == SVT.getVectorNumElements() &&
V1.getOperand(0) == V2.getOperand(0)) {
SDValue Mask =
DAG.getNode(ISD::INSERT_SUBVECTOR, DL, NVT, DAG.getUNDEF(NVT),
N.getOperand(1), DAG.getIntPtrConstant(0, DL));
return DAG.getNode(
ISD::EXTRACT_SUBVECTOR, DL, VT,
- DAG.getNode(X86ISD::VPERMV, DL, NVT, Mask, V1.getOperand(0)),
+ DAG.getNode(X86ISD::VPERMV, DL, NVT, Mask,
+ DAG.getBitcast(NVT, V1.getOperand(0))),
DAG.getIntPtrConstant(0, DL));
}
diff --git a/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll b/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
index 39c7ce1413d1b..c67049d5006ca 100644
--- a/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
+++ b/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
@@ -1638,10 +1638,9 @@ define void @vec256_i16_widen_to_i32_factor2_broadcast_to_v8i32_factor8(ptr %in.
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512BW-NEXT: vpaddb (%rsi), %zmm0, %zmm0
-; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512BW-NEXT: vpmovsxbw {{.*#+}} ymm2 = [0,17,0,19,0,21,0,23,0,25,0,27,0,29,0,31]
-; AVX512BW-NEXT: vpermi2w %ymm1, %ymm0, %ymm2
-; AVX512BW-NEXT: vpaddb (%rdx), %zmm2, %zmm0
+; AVX512BW-NEXT: vpmovsxbw {{.*#+}} ymm1 = [0,17,0,19,0,21,0,23,0,25,0,27,0,29,0,31]
+; AVX512BW-NEXT: vpermw %zmm0, %zmm1, %zmm0
+; AVX512BW-NEXT: vpaddb (%rdx), %zmm0, %zmm0
; AVX512BW-NEXT: vmovdqa64 %zmm0, (%rcx)
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -3539,11 +3538,10 @@ define void @vec384_i16_widen_to_i32_factor2_broadcast_to_v12i32_factor12(ptr %i
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512BW-NEXT: vpaddb (%rsi), %zmm0, %zmm0
-; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512BW-NEXT: vpmovsxbw {{.*#+}} xmm2 = [0,25,0,27,0,29,0,31]
-; AVX512BW-NEXT: vpermi2w %ymm1, %ymm0, %ymm2
+; AVX512BW-NEXT: vpmovsxbw {{.*#+}} xmm1 = [0,25,0,27,0,29,0,31]
+; AVX512BW-NEXT: vpermw %zmm0, %zmm1, %zmm1
; AVX512BW-NEXT: vpbroadcastw %xmm0, %ymm0
-; AVX512BW-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0
+; AVX512BW-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpaddb (%rdx), %zmm0, %zmm0
; AVX512BW-NEXT: vmovdqa64 %zmm0, (%rcx)
; AVX512BW-NEXT: vzeroupper
@@ -3672,11 +3670,10 @@ define void @vec384_i16_widen_to_i48_factor3_broadcast_to_v8i48_factor8(ptr %in.
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512BW-NEXT: vpaddb (%rsi), %zmm0, %zmm0
-; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512BW-NEXT: vpmovsxbw {{.*#+}} xmm2 = [0,25,26,0,28,29,0,31]
-; AVX512BW-NEXT: vpermi2w %ymm1, %ymm0, %ymm2
+; AVX512BW-NEXT: vpmovsxbw {{.*#+}} xmm1 = [0,25,26,0,28,29,0,31]
+; AVX512BW-NEXT: vpermw %zmm0, %zmm1, %zmm1
; AVX512BW-NEXT: vpbroadcastw %xmm0, %xmm0
-; AVX512BW-NEXT: vinserti32x4 $2, %xmm0, %zmm2, %zmm0
+; AVX512BW-NEXT: vinserti32x4 $2, %xmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpaddb (%rdx), %zmm0, %zmm0
; AVX512BW-NEXT: vmovdqa64 %zmm0, (%rcx)
; AVX512BW-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll b/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
index aea76f694a0fc..68749d6cb8fee 100644
--- a/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
+++ b/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
@@ -856,8 +856,7 @@ define <16 x i8> @oddelts_v32i16_shuffle_v16i16_to_v16i8(<32 x i16> %n2) nounwin
; AVX512VBMI-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8:
; AVX512VBMI: # %bb.0:
; AVX512VBMI-NEXT: vmovdqa {{.*#+}} xmm1 = [2,6,10,14,18,22,26,30,34,38,42,46,50,54,58,62]
-; AVX512VBMI-NEXT: vextracti64x4 $1, %zmm0, %ymm2
-; AVX512VBMI-NEXT: vpermt2b %ymm2, %ymm1, %ymm0
+; AVX512VBMI-NEXT: vpermb %zmm0, %zmm1, %zmm0
; AVX512VBMI-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; AVX512VBMI-NEXT: vzeroupper
; AVX512VBMI-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll b/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
index 99e8cdb179c8d..9290f9f17b053 100644
--- a/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
+++ b/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
@@ -1638,10 +1638,9 @@ define void @vec256_i16_widen_to_i32_factor2_broadcast_to_v8i32_factor8(ptr %in.
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512BW-NEXT: vpaddb (%rsi), %zmm0, %zmm0
-; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512BW-NEXT: vpmovsxbw {{.*#+}} ymm2 = [0,17,0,19,0,21,0,23,0,25,0,27,0,29,0,31]
-; AVX512BW-NEXT: vpermi2w %ymm1, %ymm0, %ymm2
-; AVX512BW-NEXT: vpaddb (%rdx), %zmm2, %zmm0
+; AVX512BW-NEXT: vpmovsxbw {{.*#+}} ymm1 = [0,17,0,19,0,21,0,23,0,25,0,27,0,29,0,31]
+; AVX512BW-NEXT: vpermw %zmm0, %zmm1, %zmm0
+; AVX512BW-NEXT: vpaddb (%rdx), %zmm0, %zmm0
; AVX512BW-NEXT: vmovdqa64 %zmm0, (%rcx)
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
More information about the llvm-commits
mailing list