[llvm] [SelectionDAG][RISCV] Fix break of vnsrl pattern in issue #94265 (PR #95563)

[via llvm-commits]

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@@ -4339,6 +4339,21 @@ class TargetLowering : public TargetLoweringBase {
     return isTypeLegal(VT);
   }
 
+  /// Same as isTypeDesirableForOp(unsigned Opc, EVT VT), but also check if
+  /// the target is 'desirable' to truncate or extend OldVT to NewVT only using
+  /// the given node type, without the need of explicit trunc or ext. e.g. On
+  /// RISC-V Vector extension, vnsrl.wi can directly convert <n x i32> to <n x
+  /// i16> when shifting, with no extra trunc operations needed.
+  virtual bool isTypeDesirableForOpWithCast(unsigned Opc, EVT NewVT,
+                                            EVT OldVT) const {
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Fros1er wrote:

I looked through the code and realized isTypeDesirableForOp is not suitable for the issue. isTruncateFree(SDValue, EVT) seems better here.

https://github.com/llvm/llvm-project/pull/95563