[llvm] DAG: Fix assert when legalizing v3f16 ldexp (PR #97098)

[Eli Friedman via llvm-commits]

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@@ -5231,7 +5231,17 @@ SDValue DAGTypeLegalizer::WidenVecRes_ExpOp(SDNode *N) {
   EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDValue InOp = GetWidenedVector(N->getOperand(0));
   SDValue RHS = N->getOperand(1);
-  SDValue ExpOp = RHS.getValueType().isVector() ? GetWidenedVector(RHS) : RHS;
+  EVT ExpVT = RHS.getValueType();
+  SDValue ExpOp = RHS;
+  if (ExpVT.isVector()) {
+    if (getTypeAction(ExpVT) == TargetLowering::TypeWidenVector)
+      ExpOp = GetWidenedVector(RHS);
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efriedma-quic wrote:

Consider the following on x86 with `-mattr=+avx512fp16`:

```
define <2 x half> @test_ldexp_v3f16_v3i32(<2 x half> %a, <2 x i32> %b) {
  %result = call <2 x half> @llvm.ldexp.v2f16.v2i32(<2 x half> %a, <2 x i32> %b)
  ret <2 x half> %result
}
```

We currently widen `<2 x half>` to `<8 x half>`, and `<2 x i32>` to `<4 x i32>`.  And then things sort of work.

If we want to say that the vector lengths are allowed to mismatch (so the trailing elements are poison), we shouldn't touch the exponent at all here.  If it needs to be widened, we can do that when we visit the operand.  If we want to say the vector lengths have to match, we can't assume GetWidenedVector() will return a vector with a matching vector length.

https://github.com/llvm/llvm-project/pull/97098