[llvm] [Asan] Provide TTI hook to provide memory reference infromation of target intrinsics. (PR #97070)
Yeting Kuo via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 28 08:16:16 PDT 2024
https://github.com/yetingk created https://github.com/llvm/llvm-project/pull/97070
Previously asan considers target intrinsics as black boxes, so asan could not instrument accurate check. This patch provide TTI hooks to make targets describe their intrinsic informations to asan.
Note,
1. this patch renames InterestingMemoryOperand to MemoryRefInfo.
2. this patch does not support RVV indexed/segment load/store.
>From 7a34c8d61bcee13fed17c9aa6cd7167833d10398 Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Fri, 28 Jun 2024 00:22:55 -0700
Subject: [PATCH] [Asan] Provide TTI hook to provide memory reference
infromation of target intrinsics.
Previously asan considers target intrinsics as black boxes, so asan
could not instrument accurate check. This patch provide TTI hooks to
make targets describe their intrinsic informations to asan.
Note,
1. this patch renames InterestingMemoryOperand to MemoryRefInfo.
2. this patch does not support RVV indexed/segment load/store.
---
llvm/include/llvm/Analysis/MemoryRefInfo.h | 52 +
.../llvm/Analysis/TargetTransformInfo.h | 13 +
.../llvm/Analysis/TargetTransformInfoImpl.h | 5 +
.../Instrumentation/AddressSanitizerCommon.h | 32 +-
llvm/lib/Analysis/TargetTransformInfo.cpp | 5 +
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 87 +
.../Target/RISCV/RISCVTargetTransformInfo.h | 3 +
.../Instrumentation/AddressSanitizer.cpp | 37 +-
.../Instrumentation/HWAddressSanitizer.cpp | 21 +-
.../RISCV/asan-rvv-intrinsics.ll | 16774 ++++++++++++++++
.../AddressSanitizer/asan-rvv-intrinsics.ll | 2209 ++
11 files changed, 19181 insertions(+), 57 deletions(-)
create mode 100644 llvm/include/llvm/Analysis/MemoryRefInfo.h
create mode 100644 llvm/test/Instrumentation/AddressSanitizer/RISCV/asan-rvv-intrinsics.ll
create mode 100644 llvm/test/Instrumentation/AddressSanitizer/asan-rvv-intrinsics.ll
diff --git a/llvm/include/llvm/Analysis/MemoryRefInfo.h b/llvm/include/llvm/Analysis/MemoryRefInfo.h
new file mode 100644
index 0000000000000..4621f94f6b16c
--- /dev/null
+++ b/llvm/include/llvm/Analysis/MemoryRefInfo.h
@@ -0,0 +1,52 @@
+//===--------- Definition of the MemoryRefInfo class -*- C++ -*------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines MemoryRefInfo class that is used when getting
+// the information of a memory reference instruction.
+//
+//===----------------------------------------------------------------------===//
+#ifndef LLVM_SUPPORT_MEMORYREFINFO_H
+#define LLVM_SUPPORT_MEMORYREFINFO_H
+
+#include "llvm/IR/Instruction.h"
+#include "llvm/Support/TypeSize.h"
+
+namespace llvm {
+class MemoryRefInfo {
+public:
+ Use *PtrUse = nullptr;
+ bool IsWrite;
+ Type *OpType;
+ TypeSize TypeStoreSize = TypeSize::getFixed(0);
+ MaybeAlign Alignment;
+ // The mask Value, if we're looking at a masked load/store.
+ Value *MaybeMask;
+ // The EVL Value, if we're looking at a vp intrinsic.
+ Value *MaybeEVL;
+ // The Stride Value, if we're looking at a strided load/store.
+ Value *MaybeStride;
+
+ MemoryRefInfo() = default;
+ MemoryRefInfo(Instruction *I, unsigned OperandNo, bool IsWrite,
+ class Type *OpType, MaybeAlign Alignment,
+ Value *MaybeMask = nullptr, Value *MaybeEVL = nullptr,
+ Value *MaybeStride = nullptr)
+ : IsWrite(IsWrite), OpType(OpType), Alignment(Alignment),
+ MaybeMask(MaybeMask), MaybeEVL(MaybeEVL), MaybeStride(MaybeStride) {
+ const DataLayout &DL = I->getDataLayout();
+ TypeStoreSize = DL.getTypeStoreSizeInBits(OpType);
+ PtrUse = &I->getOperandUse(OperandNo);
+ }
+
+ Instruction *getInsn() { return cast<Instruction>(PtrUse->getUser()); }
+ Value *getPtr() { return PtrUse->get(); }
+ operator bool() { return PtrUse != nullptr; }
+};
+
+} // namespace llvm
+#endif
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index dcdd9f82cde8e..3a27e8c9263d4 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -23,6 +23,7 @@
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/SmallBitVector.h"
+#include "llvm/Analysis/MemoryRefInfo.h"
#include "llvm/IR/FMF.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/PassManager.h"
@@ -955,6 +956,10 @@ class TargetTransformInfo {
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
bool IsZeroCmp) const;
+ // Add MemoryRefInfo of Intrinsic \p II into array \p Interesting.
+ bool getMemoryRefInfo(SmallVectorImpl<MemoryRefInfo> &Interesting,
+ IntrinsicInst *II) const;
+
/// Should the Select Optimization pass be enabled and ran.
bool enableSelectOptimize() const;
@@ -1932,6 +1937,8 @@ class TargetTransformInfo::Concept {
virtual bool enableAggressiveInterleaving(bool LoopHasReductions) = 0;
virtual MemCmpExpansionOptions
enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const = 0;
+ virtual bool getMemoryRefInfo(SmallVectorImpl<MemoryRefInfo> &Interesting,
+ IntrinsicInst *II) const = 0;
virtual bool enableSelectOptimize() = 0;
virtual bool shouldTreatInstructionLikeSelect(const Instruction *I) = 0;
virtual bool enableInterleavedAccessVectorization() = 0;
@@ -2485,6 +2492,12 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
bool IsZeroCmp) const override {
return Impl.enableMemCmpExpansion(OptSize, IsZeroCmp);
}
+
+ bool getMemoryRefInfo(SmallVectorImpl<MemoryRefInfo> &Interesting,
+ IntrinsicInst *II) const override {
+ return Impl.getMemoryRefInfo(Interesting, II);
+ }
+
bool enableSelectOptimize() override {
return Impl.enableSelectOptimize();
}
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index 0ded98f162abf..c46bd480aa3b3 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -394,6 +394,11 @@ class TargetTransformInfoImplBase {
return {};
}
+ bool getMemoryRefInfo(SmallVectorImpl<MemoryRefInfo> &Interesting,
+ IntrinsicInst *II) const {
+ return false;
+ }
+
bool enableSelectOptimize() const { return true; }
bool shouldTreatInstructionLikeSelect(const Instruction *I) {
diff --git a/llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h b/llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
index 9fe2716220e83..f7bd36c2def03 100644
--- a/llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
+++ b/llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
@@ -14,6 +14,7 @@
#define LLVM_TRANSFORMS_INSTRUMENTATION_ADDRESSSANITIZERCOMMON_H
#include "llvm/Analysis/CFG.h"
+#include "llvm/Analysis/MemoryRefInfo.h"
#include "llvm/Analysis/PostDominators.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/Instruction.h"
@@ -22,37 +23,6 @@
namespace llvm {
-class InterestingMemoryOperand {
-public:
- Use *PtrUse;
- bool IsWrite;
- Type *OpType;
- TypeSize TypeStoreSize = TypeSize::getFixed(0);
- MaybeAlign Alignment;
- // The mask Value, if we're looking at a masked load/store.
- Value *MaybeMask;
- // The EVL Value, if we're looking at a vp intrinsic.
- Value *MaybeEVL;
- // The Stride Value, if we're looking at a strided load/store.
- Value *MaybeStride;
-
- InterestingMemoryOperand(Instruction *I, unsigned OperandNo, bool IsWrite,
- class Type *OpType, MaybeAlign Alignment,
- Value *MaybeMask = nullptr,
- Value *MaybeEVL = nullptr,
- Value *MaybeStride = nullptr)
- : IsWrite(IsWrite), OpType(OpType), Alignment(Alignment),
- MaybeMask(MaybeMask), MaybeEVL(MaybeEVL), MaybeStride(MaybeStride) {
- const DataLayout &DL = I->getDataLayout();
- TypeStoreSize = DL.getTypeStoreSizeInBits(OpType);
- PtrUse = &I->getOperandUse(OperandNo);
- }
-
- Instruction *getInsn() { return cast<Instruction>(PtrUse->getUser()); }
-
- Value *getPtr() { return PtrUse->get(); }
-};
-
// Get AddressSanitizer parameters.
void getAddressSanitizerParams(const Triple &TargetTriple, int LongSize,
bool IsKasan, uint64_t *ShadowBase,
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index c175d1737e54b..3b89e74f5b4ae 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -622,6 +622,11 @@ TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
}
+bool TargetTransformInfo::getMemoryRefInfo(
+ SmallVectorImpl<MemoryRefInfo> &Interesting, IntrinsicInst *II) const {
+ return TTIImpl->getMemoryRefInfo(Interesting, II);
+}
+
bool TargetTransformInfo::enableSelectOptimize() const {
return TTIImpl->enableSelectOptimize();
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 176d0e79253ac..d87f9f8b5f0de 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -13,7 +13,9 @@
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/CodeGen/CostTable.h"
#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
+#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/IR/PatternMatch.h"
#include <cmath>
#include <optional>
@@ -36,6 +38,91 @@ static cl::opt<unsigned> SLPMaxVF(
"exclusively by SLP vectorizer."),
cl::Hidden);
+bool RISCVTTIImpl::getMemoryRefInfo(SmallVectorImpl<MemoryRefInfo> &Interesting,
+ IntrinsicInst *II) const {
+ const DataLayout &DL = getDataLayout();
+ unsigned IntNo = II->getIntrinsicID();
+ LLVMContext &C = II->getContext();
+ IRBuilder<> IB(II);
+ bool HasMask = false;
+
+ switch (IntNo) {
+ case Intrinsic::riscv_vle_mask:
+ case Intrinsic::riscv_vse_mask:
+ HasMask = true;
+ [[fallthrough]];
+ case Intrinsic::riscv_vle:
+ case Intrinsic::riscv_vse: {
+ bool IsWrite = II->getType()->isVoidTy();
+ Type *Ty = IsWrite ? II->getArgOperand(0)->getType() : II->getType();
+ const auto *RVVIInfo = RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo);
+ unsigned VLIndex = RVVIInfo->VLOperand;
+ unsigned PtrOperandNo = VLIndex - 1 - HasMask;
+ MaybeAlign Alignment =
+ II->getArgOperand(PtrOperandNo)->getPointerAlignment(DL);
+ Type *MaskType = Ty->getWithNewType(Type::getInt1Ty(C));
+ Value *Mask = ConstantInt::get(MaskType, 1);
+ if (HasMask)
+ Mask = II->getArgOperand(VLIndex - 1);
+ Value *EVL = II->getArgOperand(VLIndex);
+ Interesting.emplace_back(II, PtrOperandNo, IsWrite, Ty, Alignment, Mask,
+ EVL);
+ return true;
+ }
+ case Intrinsic::riscv_vlse_mask:
+ case Intrinsic::riscv_vsse_mask:
+ HasMask = true;
+ [[fallthrough]];
+ case Intrinsic::riscv_vlse:
+ case Intrinsic::riscv_vsse: {
+ bool IsWrite = II->getType()->isVoidTy();
+ Type *Ty = IsWrite ? II->getArgOperand(0)->getType() : II->getType();
+ const auto *RVVIInfo = RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo);
+ unsigned VLIndex = RVVIInfo->VLOperand;
+ unsigned PtrOperandNo = VLIndex - 2 - HasMask;
+ MaybeAlign Alignment =
+ II->getArgOperand(PtrOperandNo)->getPointerAlignment(DL);
+
+ Value *Stride = II->getArgOperand(PtrOperandNo + 1);
+ // Use the pointer alignment as the element alignment if the stride is a
+ // multiple of the pointer alignment. Otherwise, the element alignment
+ // should be Align(1).
+ unsigned PointerAlign = Alignment.valueOrOne().value();
+ if (!isa<ConstantInt>(Stride) ||
+ cast<ConstantInt>(Stride)->getZExtValue() % PointerAlign != 0)
+ Alignment = Align(1);
+
+ Type *MaskType = Ty->getWithNewType(Type::getInt1Ty(C));
+ Value *Mask = ConstantInt::get(MaskType, 1);
+ if (HasMask)
+ Mask = II->getArgOperand(VLIndex - 1);
+ Value *EVL = II->getArgOperand(VLIndex);
+ Interesting.emplace_back(II, PtrOperandNo, IsWrite, Ty, Alignment, Mask,
+ EVL, Stride);
+ return true;
+ }
+ case Intrinsic::riscv_masked_strided_load:
+ case Intrinsic::riscv_masked_strided_store: {
+ bool IsWrite = IntNo == Intrinsic::riscv_masked_strided_store;
+ Type *Ty = II->getArgOperand(0)->getType();
+ Value *Stride = II->getOperand(2);
+ // Use the pointer alignment as the element alignment if the stride is a
+ // mutiple of the pointer alignment. Otherwise, the element alignment
+ // should be Align(1).
+ MaybeAlign Alignment = II->getArgOperand(1)->getPointerAlignment(DL);
+ unsigned PointerAlign = Alignment.valueOrOne().value();
+ if (!isa<ConstantInt>(Stride) ||
+ cast<ConstantInt>(Stride)->getZExtValue() % PointerAlign != 0)
+ Alignment = Align(1);
+ Value *Mask = II->getArgOperand(3);
+ Interesting.emplace_back(II, /* PtrOperandNo */ 1, IsWrite, Ty, Alignment,
+ Mask, /* MaybeEVL */ nullptr, Stride);
+ return true;
+ }
+ }
+ return false;
+}
+
InstructionCost
RISCVTTIImpl::getRISCVInstructionCost(ArrayRef<unsigned> OpCodes, MVT VT,
TTI::TargetCostKind CostKind) {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index c4d10aada1f4c..09851127a1e5a 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -60,6 +60,9 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}
+ bool getMemoryRefInfo(SmallVectorImpl<MemoryRefInfo> &Interesting,
+ IntrinsicInst *II) const;
+
bool areInlineCompatible(const Function *Caller,
const Function *Callee) const;
diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
index adf77f20cb1c7..8b30a1c191cda 100644
--- a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -29,6 +29,7 @@
#include "llvm/Analysis/MemoryBuiltins.h"
#include "llvm/Analysis/StackSafetyAnalysis.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/BinaryFormat/MachO.h"
#include "llvm/Demangle/Demangle.h"
@@ -754,12 +755,13 @@ struct AddressSanitizer {
bool isInterestingAlloca(const AllocaInst &AI);
bool ignoreAccess(Instruction *Inst, Value *Ptr);
- void getInterestingMemoryOperands(
- Instruction *I, SmallVectorImpl<InterestingMemoryOperand> &Interesting);
+ void getMemoryRefInfos(Instruction *I,
+ SmallVectorImpl<MemoryRefInfo> &Interesting,
+ const TargetTransformInfo *TTI);
- void instrumentMop(ObjectSizeOffsetVisitor &ObjSizeVis,
- InterestingMemoryOperand &O, bool UseCalls,
- const DataLayout &DL, RuntimeCallInserter &RTCI);
+ void instrumentMop(ObjectSizeOffsetVisitor &ObjSizeVis, MemoryRefInfo &O,
+ bool UseCalls, const DataLayout &DL,
+ RuntimeCallInserter &RTCI);
void instrumentPointerComparisonOrSubtraction(Instruction *I,
RuntimeCallInserter &RTCI);
void instrumentAddress(Instruction *OrigIns, Instruction *InsertBefore,
@@ -795,7 +797,8 @@ struct AddressSanitizer {
void instrumentMemIntrinsic(MemIntrinsic *MI, RuntimeCallInserter &RTCI);
Value *memToShadow(Value *Shadow, IRBuilder<> &IRB);
bool suppressInstrumentationSiteForDebug(int &Instrumented);
- bool instrumentFunction(Function &F, const TargetLibraryInfo *TLI);
+ bool instrumentFunction(Function &F, const TargetLibraryInfo *TLI,
+ const TargetTransformInfo *TTI);
bool maybeInsertAsanInitAtFunctionEntry(Function &F);
bool maybeInsertDynamicShadowAtFunctionEntry(Function &F);
void markEscapedLocalAllocas(Function &F);
@@ -1264,7 +1267,8 @@ PreservedAnalyses AddressSanitizerPass::run(Module &M,
Options.MaxInlinePoisoningSize, Options.CompileKernel, Options.Recover,
Options.UseAfterScope, Options.UseAfterReturn);
const TargetLibraryInfo &TLI = FAM.getResult<TargetLibraryAnalysis>(F);
- Modified |= FunctionSanitizer.instrumentFunction(F, &TLI);
+ const TargetTransformInfo &TTI = FAM.getResult<TargetIRAnalysis>(F);
+ Modified |= FunctionSanitizer.instrumentFunction(F, &TLI, &TTI);
}
Modified |= ModuleSanitizer.instrumentModule(M);
if (!Modified)
@@ -1401,8 +1405,9 @@ bool AddressSanitizer::ignoreAccess(Instruction *Inst, Value *Ptr) {
return false;
}
-void AddressSanitizer::getInterestingMemoryOperands(
- Instruction *I, SmallVectorImpl<InterestingMemoryOperand> &Interesting) {
+void AddressSanitizer::getMemoryRefInfos(
+ Instruction *I, SmallVectorImpl<MemoryRefInfo> &Interesting,
+ const TargetTransformInfo *TTI) {
// Do not instrument the load fetching the dynamic shadow address.
if (LocalDynamicShadow == I)
return;
@@ -1520,6 +1525,9 @@ void AddressSanitizer::getInterestingMemoryOperands(
break;
}
default:
+ if (auto *II = dyn_cast<IntrinsicInst>(I))
+ if (TTI->getMemoryRefInfo(Interesting, II))
+ return;
for (unsigned ArgNo = 0; ArgNo < CI->arg_size(); ArgNo++) {
if (!ClInstrumentByval || !CI->isByValArgument(ArgNo) ||
ignoreAccess(I, CI->getArgOperand(ArgNo)))
@@ -1682,7 +1690,7 @@ void AddressSanitizer::instrumentMaskedLoadOrStore(
}
void AddressSanitizer::instrumentMop(ObjectSizeOffsetVisitor &ObjSizeVis,
- InterestingMemoryOperand &O, bool UseCalls,
+ MemoryRefInfo &O, bool UseCalls,
const DataLayout &DL,
RuntimeCallInserter &RTCI) {
Value *Addr = O.getPtr();
@@ -2941,7 +2949,8 @@ bool AddressSanitizer::suppressInstrumentationSiteForDebug(int &Instrumented) {
}
bool AddressSanitizer::instrumentFunction(Function &F,
- const TargetLibraryInfo *TLI) {
+ const TargetLibraryInfo *TLI,
+ const TargetTransformInfo *TTI) {
if (F.empty())
return false;
if (F.getLinkage() == GlobalValue::AvailableExternallyLinkage) return false;
@@ -2979,7 +2988,7 @@ bool AddressSanitizer::instrumentFunction(Function &F,
// We want to instrument every address only once per basic block (unless there
// are calls between uses).
SmallPtrSet<Value *, 16> TempsToInstrument;
- SmallVector<InterestingMemoryOperand, 16> OperandsToInstrument;
+ SmallVector<MemoryRefInfo, 16> OperandsToInstrument;
SmallVector<MemIntrinsic *, 16> IntrinToInstrument;
SmallVector<Instruction *, 8> NoReturnCalls;
SmallVector<BasicBlock *, 16> AllBlocks;
@@ -2995,8 +3004,8 @@ bool AddressSanitizer::instrumentFunction(Function &F,
// Skip instructions inserted by another instrumentation.
if (Inst.hasMetadata(LLVMContext::MD_nosanitize))
continue;
- SmallVector<InterestingMemoryOperand, 1> InterestingOperands;
- getInterestingMemoryOperands(&Inst, InterestingOperands);
+ SmallVector<MemoryRefInfo, 1> InterestingOperands;
+ getMemoryRefInfos(&Inst, InterestingOperands, TTI);
if (!InterestingOperands.empty()) {
for (auto &Operand : InterestingOperands) {
diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
index a0e63bf12400e..47212b2679e81 100644
--- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
@@ -339,16 +339,14 @@ class HWAddressSanitizer {
LoopInfo *LI);
bool ignoreMemIntrinsic(OptimizationRemarkEmitter &ORE, MemIntrinsic *MI);
void instrumentMemIntrinsic(MemIntrinsic *MI);
- bool instrumentMemAccess(InterestingMemoryOperand &O, DomTreeUpdater &DTU,
- LoopInfo *LI);
+ bool instrumentMemAccess(MemoryRefInfo &O, DomTreeUpdater &DTU, LoopInfo *LI);
bool ignoreAccessWithoutRemark(Instruction *Inst, Value *Ptr);
bool ignoreAccess(OptimizationRemarkEmitter &ORE, Instruction *Inst,
Value *Ptr);
- void getInterestingMemoryOperands(
- OptimizationRemarkEmitter &ORE, Instruction *I,
- const TargetLibraryInfo &TLI,
- SmallVectorImpl<InterestingMemoryOperand> &Interesting);
+ void getMemoryRefInfos(OptimizationRemarkEmitter &ORE, Instruction *I,
+ const TargetLibraryInfo &TLI,
+ SmallVectorImpl<MemoryRefInfo> &Interesting);
void tagAlloca(IRBuilder<> &IRB, AllocaInst *AI, Value *Tag, size_t Size);
Value *tagPointer(IRBuilder<> &IRB, Type *Ty, Value *PtrLong, Value *Tag);
@@ -814,10 +812,9 @@ bool HWAddressSanitizer::ignoreAccess(OptimizationRemarkEmitter &ORE,
return Ignored;
}
-void HWAddressSanitizer::getInterestingMemoryOperands(
+void HWAddressSanitizer::getMemoryRefInfos(
OptimizationRemarkEmitter &ORE, Instruction *I,
- const TargetLibraryInfo &TLI,
- SmallVectorImpl<InterestingMemoryOperand> &Interesting) {
+ const TargetLibraryInfo &TLI, SmallVectorImpl<MemoryRefInfo> &Interesting) {
// Skip memory accesses inserted by another instrumentation.
if (I->hasMetadata(LLVMContext::MD_nosanitize))
return;
@@ -1088,7 +1085,7 @@ void HWAddressSanitizer::instrumentMemIntrinsic(MemIntrinsic *MI) {
MI->eraseFromParent();
}
-bool HWAddressSanitizer::instrumentMemAccess(InterestingMemoryOperand &O,
+bool HWAddressSanitizer::instrumentMemAccess(MemoryRefInfo &O,
DomTreeUpdater &DTU,
LoopInfo *LI) {
Value *Addr = O.getPtr();
@@ -1572,7 +1569,7 @@ void HWAddressSanitizer::sanitizeFunction(Function &F,
LLVM_DEBUG(dbgs() << "Function: " << F.getName() << "\n");
- SmallVector<InterestingMemoryOperand, 16> OperandsToInstrument;
+ SmallVector<MemoryRefInfo, 16> OperandsToInstrument;
SmallVector<MemIntrinsic *, 16> IntrinToInstrument;
SmallVector<Instruction *, 8> LandingPadVec;
const TargetLibraryInfo &TLI = FAM.getResult<TargetLibraryAnalysis>(F);
@@ -1586,7 +1583,7 @@ void HWAddressSanitizer::sanitizeFunction(Function &F,
if (InstrumentLandingPads && isa<LandingPadInst>(Inst))
LandingPadVec.push_back(&Inst);
- getInterestingMemoryOperands(ORE, &Inst, TLI, OperandsToInstrument);
+ getMemoryRefInfos(ORE, &Inst, TLI, OperandsToInstrument);
if (MemIntrinsic *MI = dyn_cast<MemIntrinsic>(&Inst))
if (!ignoreMemIntrinsic(ORE, MI))
diff --git a/llvm/test/Instrumentation/AddressSanitizer/RISCV/asan-rvv-intrinsics.ll b/llvm/test/Instrumentation/AddressSanitizer/RISCV/asan-rvv-intrinsics.ll
new file mode 100644
index 0000000000000..a5e42b8dfedc7
--- /dev/null
+++ b/llvm/test/Instrumentation/AddressSanitizer/RISCV/asan-rvv-intrinsics.ll
@@ -0,0 +1,16774 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=riscv64 -mattr=+v -passes=asan \
+; RUN: -asan-instrumentation-with-call-threshold=0 -S | FileCheck %s
+
+declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ i64)
+define <vscale x 1 x i32> @intrinsic_vle_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* align 4 %0, i64 %1) sanitize_address {
+; CHECK-LABEL: @intrinsic_vle_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[TMP1:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]
+; CHECK: 4:
+; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 [[TMP5]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr <vscale x 1 x i32>, ptr [[TMP0:%.*]], i64 0, i64 [[IV]]
+; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP10]])
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, ptr [[TMP0]], i64 [[TMP1]])
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32(
+ <vscale x 1 x i32> undef,
+ <vscale x 1 x i32>* %0,
+ i64 %1)
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i1>,
+ i64,
+ i64)
+define <vscale x 1 x i32> @intrinsic_vle_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* align 4 %1, <vscale x 1 x i1> %2, i64 %3) sanitize_address {
+; CHECK-LABEL: @intrinsic_vle_mask_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP3:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP14:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP7]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> [[TMP2:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr <vscale x 1 x i32>, ptr [[TMP1:%.*]], i64 0, i64 [[IV]]
+; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP12]])
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i1> [[TMP2]], i64 [[TMP3]], i64 1)
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i1> %2,
+ i64 %3, i64 1)
+ ret <vscale x 1 x i32> %a
+}
+
+declare void @llvm.riscv.vse.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ i64)
+define void @intrinsic_vse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* align 4 %1, i64 %2) sanitize_address {
+; CHECK-LABEL: @intrinsic_vse_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP2:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP13:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr <vscale x 1 x i32>, ptr [[TMP1:%.*]], i64 0, i64 [[IV]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP11]])
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: call void @llvm.riscv.vse.nxv1i32.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vse.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ i64 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vse.mask.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i1>,
+ i64)
+define void @intrinsic_vse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* align 4 %1, <vscale x 1 x i1> %2, i64 %3) sanitize_address {
+; CHECK-LABEL: @intrinsic_vse_mask_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP3:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP14:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP7]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> [[TMP2:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr <vscale x 1 x i32>, ptr [[TMP1:%.*]], i64 0, i64 [[IV]]
+; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP12]])
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i1> [[TMP2]], i64 [[TMP3]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vse.mask.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i1> %2,
+ i64 %3)
+ ret void
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg2_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg2_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 8
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 8
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP25]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg2_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg2_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 8
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 8
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP25]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg3_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg3_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 12
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 12
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 12
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP36]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP37]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg3_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg3_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 12
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 12
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 12
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP36]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP37]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg4_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg4_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 16
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 16
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 16
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 16
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: [[TMP49:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP48]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP49]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg4_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg4_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 16
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 16
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 16
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 16
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP49:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP48]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP49]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg5_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg5_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 20
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 20
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 20
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 20
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 20
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: [[TMP61:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP60]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP61]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg5_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg5_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 20
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 20
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 20
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 20
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 20
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP61:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP60]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP61]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg6_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg6_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 24
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 24
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 24
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 24
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 24
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], 24
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP69]])
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: [[TMP73:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP72]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP73]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg6_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg6_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 24
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 24
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 24
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 24
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 24
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], 24
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP69]])
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP73:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP72]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP73]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg7_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg7_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 28
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 28
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 28
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 28
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 28
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], 28
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP69]])
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], 28
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP81]])
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[TMP84:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: [[TMP85:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP84]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP85]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg7_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg7_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 28
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 28
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 28
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 28
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 28
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], 28
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP69]])
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], 28
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP81]])
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[TMP84:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP85:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP84]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP85]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg8_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg8_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 32
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 32
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 32
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 32
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 32
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], 32
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP69]])
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], 32
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP81]])
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[TMP84:%.*]] = getelementptr i8, ptr [[BASE]], i64 28
+; CHECK-NEXT: [[TMP85:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP85]], label [[TMP86:%.*]], label [[TMP95:%.*]]
+; CHECK: 86:
+; CHECK-NEXT: [[TMP87:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP88:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP87]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP86]] ], [ [[IV14_NEXT:%.*]], [[TMP94:%.*]] ]
+; CHECK-NEXT: [[TMP89:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP89]], label [[TMP90:%.*]], label [[TMP94]]
+; CHECK: 90:
+; CHECK-NEXT: [[TMP91:%.*]] = mul i64 [[IV14]], 32
+; CHECK-NEXT: [[TMP92:%.*]] = getelementptr i8, ptr [[TMP84]], i64 [[TMP91]]
+; CHECK-NEXT: [[TMP93:%.*]] = ptrtoint ptr [[TMP92]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP93]])
+; CHECK-NEXT: br label [[TMP94]]
+; CHECK: 94:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP88]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[TMP96:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: [[TMP97:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP96]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP97]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg8_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg8_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 32
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 32
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 32
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 32
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 32
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], 32
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP69]])
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], 32
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP81]])
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[TMP84:%.*]] = getelementptr i8, ptr [[BASE]], i64 28
+; CHECK-NEXT: [[TMP85:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP85]], label [[TMP86:%.*]], label [[TMP95:%.*]]
+; CHECK: 86:
+; CHECK-NEXT: [[TMP87:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP88:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP87]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP86]] ], [ [[IV14_NEXT:%.*]], [[TMP94:%.*]] ]
+; CHECK-NEXT: [[TMP89:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP89]], label [[TMP90:%.*]], label [[TMP94]]
+; CHECK: 90:
+; CHECK-NEXT: [[TMP91:%.*]] = mul i64 [[IV14]], 32
+; CHECK-NEXT: [[TMP92:%.*]] = getelementptr i8, ptr [[TMP84]], i64 [[TMP91]]
+; CHECK-NEXT: [[TMP93:%.*]] = ptrtoint ptr [[TMP92]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP93]])
+; CHECK-NEXT: br label [[TMP94]]
+; CHECK: 94:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP88]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[TMP96:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP97:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP96]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP97]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg2_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg2_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 8
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 8
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg2.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg2_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 8
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 8
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg2.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg3_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg3_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 12
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 12
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 12
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg3.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg3_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 12
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 12
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 12
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg3.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg4_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg4_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 16
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 16
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 16
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 16
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg4.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg4_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 16
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 16
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 16
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 16
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg4.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg5_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg5_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 20
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 20
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 20
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 20
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 20
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg5.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg5_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 20
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 20
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 20
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 20
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 20
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg5.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg6_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg6_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 24
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 24
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 24
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 24
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 24
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], 24
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP69]])
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg6.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg6_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 24
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 24
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 24
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 24
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 24
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], 24
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP69]])
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg6.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg7_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg7_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 28
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 28
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 28
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 28
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 28
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], 28
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP69]])
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], 28
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP81]])
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg7.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg7_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 28
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 28
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 28
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 28
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 28
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], 28
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP69]])
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], 28
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP81]])
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg7.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg8_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg8_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 32
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 32
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 32
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 32
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 32
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], 32
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP69]])
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], 32
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP81]])
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[TMP84:%.*]] = getelementptr i8, ptr [[BASE]], i64 28
+; CHECK-NEXT: [[TMP85:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP85]], label [[TMP86:%.*]], label [[TMP95:%.*]]
+; CHECK: 86:
+; CHECK-NEXT: [[TMP87:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP88:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP87]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP86]] ], [ [[IV14_NEXT:%.*]], [[TMP94:%.*]] ]
+; CHECK-NEXT: [[TMP89:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP89]], label [[TMP90:%.*]], label [[TMP94]]
+; CHECK: 90:
+; CHECK-NEXT: [[TMP91:%.*]] = mul i64 [[IV14]], 32
+; CHECK-NEXT: [[TMP92:%.*]] = getelementptr i8, ptr [[TMP84]], i64 [[TMP91]]
+; CHECK-NEXT: [[TMP93:%.*]] = ptrtoint ptr [[TMP92]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP93]])
+; CHECK-NEXT: br label [[TMP94]]
+; CHECK: 94:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP88]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg8.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg8_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], 32
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], 32
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP21]])
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], 32
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP33]])
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], 32
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP45]])
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], 32
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP57]])
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], 32
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP69]])
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], 32
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP81]])
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[TMP84:%.*]] = getelementptr i8, ptr [[BASE]], i64 28
+; CHECK-NEXT: [[TMP85:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP85]], label [[TMP86:%.*]], label [[TMP95:%.*]]
+; CHECK: 86:
+; CHECK-NEXT: [[TMP87:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP88:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP87]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP86]] ], [ [[IV14_NEXT:%.*]], [[TMP94:%.*]] ]
+; CHECK-NEXT: [[TMP89:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP89]], label [[TMP90:%.*]], label [[TMP94]]
+; CHECK: 90:
+; CHECK-NEXT: [[TMP91:%.*]] = mul i64 [[IV14]], 32
+; CHECK-NEXT: [[TMP92:%.*]] = getelementptr i8, ptr [[TMP84]], i64 [[TMP91]]
+; CHECK-NEXT: [[TMP93:%.*]] = ptrtoint ptr [[TMP92]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP93]])
+; CHECK-NEXT: br label [[TMP94]]
+; CHECK: 94:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP88]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg8.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+; Test stride load
+declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ i64,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* align 4 %0, i64 %1, i64 %2) sanitize_address {
+; CHECK-LABEL: @intrinsic_vlse_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP2:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP14:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP13]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[IV]], [[TMP1:%.*]]
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], i64 [[TMP10]]
+; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP12]], i64 4)
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> undef, ptr [[TMP0]], i64 [[TMP1]], i64 [[TMP2]])
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(
+ <vscale x 1 x i32> undef,
+ <vscale x 1 x i32>* %0,
+ i64 %1,
+ i64 %2)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ i64,
+ <vscale x 1 x i1>,
+ i64,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vlse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {
+; CHECK-LABEL: @intrinsic_vlse_mask_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP4:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP16:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP8]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP15]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[IV]], [[TMP2:%.*]]
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], i64 [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP14]], i64 4)
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]], i64 1)
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ i64 %2,
+ <vscale x 1 x i1> %3,
+ i64 %4, i64 1)
+
+ ret <vscale x 1 x i32> %a
+}
+
+; Test stride store
+declare void @llvm.riscv.vsse.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ i64,
+ i64);
+
+define void @intrinsic_vsse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i64 %2, i64 %3) sanitize_address {
+; CHECK-LABEL: @intrinsic_vsse_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP3:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP15:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP7]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP14]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[IV]], [[TMP2:%.*]]
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], i64 [[TMP11]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: call void @llvm.riscv.vsse.nxv1i32.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]], i64 [[TMP3]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vsse.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ i64 %2,
+ i64 %3)
+
+ ret void
+}
+
+declare void @llvm.riscv.vsse.mask.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ i64,
+ <vscale x 1 x i1>,
+ i64);
+
+define void @intrinsic_vsse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {
+; CHECK-LABEL: @intrinsic_vsse_mask_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP4:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP16:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP8]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP15]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[IV]], [[TMP2:%.*]]
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], i64 [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP14]], i64 4)
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: call void @llvm.riscv.vsse.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vsse.mask.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ i64 %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret void
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg2_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg2_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg2.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP25]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg2_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg2_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg2.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 0
+; CHECK-NEXT: [[TMP26:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP26]], label [[TMP27:%.*]], label [[TMP36:%.*]]
+; CHECK: 27:
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP29:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP28]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP27]] ], [ [[IV4_NEXT:%.*]], [[TMP35:%.*]] ]
+; CHECK-NEXT: [[TMP30:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP35]]
+; CHECK: 31:
+; CHECK-NEXT: [[TMP32:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP33:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP32]]
+; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP33]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP34]], i64 4)
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP29]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: [[TMP37:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP38:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP38]], label [[TMP39:%.*]], label [[TMP48:%.*]]
+; CHECK: 39:
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP41:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP40]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP39]] ], [ [[IV6_NEXT:%.*]], [[TMP47:%.*]] ]
+; CHECK-NEXT: [[TMP42:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP42]], label [[TMP43:%.*]], label [[TMP47]]
+; CHECK: 43:
+; CHECK-NEXT: [[TMP44:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP45:%.*]] = getelementptr i8, ptr [[TMP37]], i64 [[TMP44]]
+; CHECK-NEXT: [[TMP46:%.*]] = ptrtoint ptr [[TMP45]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP46]], i64 4)
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP41]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg2.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP25]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP50:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP49]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP50]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg3_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg3_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg3.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP36]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP37]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg3_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg3_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg3.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP36]], 0
+; CHECK-NEXT: [[TMP38:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP38]], label [[TMP39:%.*]], label [[TMP48:%.*]]
+; CHECK: 39:
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP41:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP40]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP39]] ], [ [[IV6_NEXT:%.*]], [[TMP47:%.*]] ]
+; CHECK-NEXT: [[TMP42:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP42]], label [[TMP43:%.*]], label [[TMP47]]
+; CHECK: 43:
+; CHECK-NEXT: [[TMP44:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP45:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP44]]
+; CHECK-NEXT: [[TMP46:%.*]] = ptrtoint ptr [[TMP45]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP46]], i64 4)
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP41]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP50:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP50]], label [[TMP51:%.*]], label [[TMP60:%.*]]
+; CHECK: 51:
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP53:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP52]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP51]] ], [ [[IV8_NEXT:%.*]], [[TMP59:%.*]] ]
+; CHECK-NEXT: [[TMP54:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP54]], label [[TMP55:%.*]], label [[TMP59]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP57:%.*]] = getelementptr i8, ptr [[TMP49]], i64 [[TMP56]]
+; CHECK-NEXT: [[TMP58:%.*]] = ptrtoint ptr [[TMP57]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP58]], i64 4)
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP53]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[TMP61:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP62:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP62]], label [[TMP63:%.*]], label [[TMP72:%.*]]
+; CHECK: 63:
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP65:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP64]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP63]] ], [ [[IV10_NEXT:%.*]], [[TMP71:%.*]] ]
+; CHECK-NEXT: [[TMP66:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP66]], label [[TMP67:%.*]], label [[TMP71]]
+; CHECK: 67:
+; CHECK-NEXT: [[TMP68:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i8, ptr [[TMP61]], i64 [[TMP68]]
+; CHECK-NEXT: [[TMP70:%.*]] = ptrtoint ptr [[TMP69]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP70]], i64 4)
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP65]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[TMP73:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg3.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP37]], <vscale x 1 x i32> [[TMP37]], <vscale x 1 x i32> [[TMP37]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP74:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP73]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP74]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg4_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg4_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg4.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP49:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP48]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP49]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg4_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg4_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg4.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP49:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP48]], 0
+; CHECK-NEXT: [[TMP50:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP50]], label [[TMP51:%.*]], label [[TMP60:%.*]]
+; CHECK: 51:
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP53:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP52]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP51]] ], [ [[IV8_NEXT:%.*]], [[TMP59:%.*]] ]
+; CHECK-NEXT: [[TMP54:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP54]], label [[TMP55:%.*]], label [[TMP59]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP57:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP56]]
+; CHECK-NEXT: [[TMP58:%.*]] = ptrtoint ptr [[TMP57]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP58]], i64 4)
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP53]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[TMP61:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP62:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP62]], label [[TMP63:%.*]], label [[TMP72:%.*]]
+; CHECK: 63:
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP65:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP64]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP63]] ], [ [[IV10_NEXT:%.*]], [[TMP71:%.*]] ]
+; CHECK-NEXT: [[TMP66:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP66]], label [[TMP67:%.*]], label [[TMP71]]
+; CHECK: 67:
+; CHECK-NEXT: [[TMP68:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i8, ptr [[TMP61]], i64 [[TMP68]]
+; CHECK-NEXT: [[TMP70:%.*]] = ptrtoint ptr [[TMP69]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP70]], i64 4)
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP65]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[TMP73:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP74:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP74]], label [[TMP75:%.*]], label [[TMP84:%.*]]
+; CHECK: 75:
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP77:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP76]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP75]] ], [ [[IV12_NEXT:%.*]], [[TMP83:%.*]] ]
+; CHECK-NEXT: [[TMP78:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP78]], label [[TMP79:%.*]], label [[TMP83]]
+; CHECK: 79:
+; CHECK-NEXT: [[TMP80:%.*]] = mul i64 [[IV12]], [[OFFSET]]
+; CHECK-NEXT: [[TMP81:%.*]] = getelementptr i8, ptr [[TMP73]], i64 [[TMP80]]
+; CHECK-NEXT: [[TMP82:%.*]] = ptrtoint ptr [[TMP81]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP82]], i64 4)
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP77]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[TMP85:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP86:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP86]], label [[TMP87:%.*]], label [[TMP96:%.*]]
+; CHECK: 87:
+; CHECK-NEXT: [[TMP88:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP88]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP87]] ], [ [[IV14_NEXT:%.*]], [[TMP95:%.*]] ]
+; CHECK-NEXT: [[TMP90:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP90]], label [[TMP91:%.*]], label [[TMP95]]
+; CHECK: 91:
+; CHECK-NEXT: [[TMP92:%.*]] = mul i64 [[IV14]], [[OFFSET]]
+; CHECK-NEXT: [[TMP93:%.*]] = getelementptr i8, ptr [[TMP85]], i64 [[TMP92]]
+; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr [[TMP93]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP94]], i64 4)
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP89]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP96]]
+; CHECK: 96:
+; CHECK-NEXT: [[TMP97:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg4.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP49]], <vscale x 1 x i32> [[TMP49]], <vscale x 1 x i32> [[TMP49]], <vscale x 1 x i32> [[TMP49]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP98:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP97]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP98]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg5_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg5_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg5.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP61:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP60]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP61]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg5_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg5_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg5.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP61:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP60]], 0
+; CHECK-NEXT: [[TMP62:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP62]], label [[TMP63:%.*]], label [[TMP72:%.*]]
+; CHECK: 63:
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP65:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP64]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP63]] ], [ [[IV10_NEXT:%.*]], [[TMP71:%.*]] ]
+; CHECK-NEXT: [[TMP66:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP66]], label [[TMP67:%.*]], label [[TMP71]]
+; CHECK: 67:
+; CHECK-NEXT: [[TMP68:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP68]]
+; CHECK-NEXT: [[TMP70:%.*]] = ptrtoint ptr [[TMP69]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP70]], i64 4)
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP65]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[TMP73:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP74:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP74]], label [[TMP75:%.*]], label [[TMP84:%.*]]
+; CHECK: 75:
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP77:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP76]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP75]] ], [ [[IV12_NEXT:%.*]], [[TMP83:%.*]] ]
+; CHECK-NEXT: [[TMP78:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP78]], label [[TMP79:%.*]], label [[TMP83]]
+; CHECK: 79:
+; CHECK-NEXT: [[TMP80:%.*]] = mul i64 [[IV12]], [[OFFSET]]
+; CHECK-NEXT: [[TMP81:%.*]] = getelementptr i8, ptr [[TMP73]], i64 [[TMP80]]
+; CHECK-NEXT: [[TMP82:%.*]] = ptrtoint ptr [[TMP81]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP82]], i64 4)
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP77]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[TMP85:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP86:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP86]], label [[TMP87:%.*]], label [[TMP96:%.*]]
+; CHECK: 87:
+; CHECK-NEXT: [[TMP88:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP88]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP87]] ], [ [[IV14_NEXT:%.*]], [[TMP95:%.*]] ]
+; CHECK-NEXT: [[TMP90:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP90]], label [[TMP91:%.*]], label [[TMP95]]
+; CHECK: 91:
+; CHECK-NEXT: [[TMP92:%.*]] = mul i64 [[IV14]], [[OFFSET]]
+; CHECK-NEXT: [[TMP93:%.*]] = getelementptr i8, ptr [[TMP85]], i64 [[TMP92]]
+; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr [[TMP93]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP94]], i64 4)
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP89]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP96]]
+; CHECK: 96:
+; CHECK-NEXT: [[TMP97:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP98:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP98]], label [[TMP99:%.*]], label [[TMP108:%.*]]
+; CHECK: 99:
+; CHECK-NEXT: [[TMP100:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP101:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP100]])
+; CHECK-NEXT: br label [[DOTSPLIT15:%.*]]
+; CHECK: .split15:
+; CHECK-NEXT: [[IV16:%.*]] = phi i64 [ 0, [[TMP99]] ], [ [[IV16_NEXT:%.*]], [[TMP107:%.*]] ]
+; CHECK-NEXT: [[TMP102:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV16]]
+; CHECK-NEXT: br i1 [[TMP102]], label [[TMP103:%.*]], label [[TMP107]]
+; CHECK: 103:
+; CHECK-NEXT: [[TMP104:%.*]] = mul i64 [[IV16]], [[OFFSET]]
+; CHECK-NEXT: [[TMP105:%.*]] = getelementptr i8, ptr [[TMP97]], i64 [[TMP104]]
+; CHECK-NEXT: [[TMP106:%.*]] = ptrtoint ptr [[TMP105]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP106]], i64 4)
+; CHECK-NEXT: br label [[TMP107]]
+; CHECK: 107:
+; CHECK-NEXT: [[IV16_NEXT]] = add nuw nsw i64 [[IV16]], 1
+; CHECK-NEXT: [[IV16_CHECK:%.*]] = icmp eq i64 [[IV16_NEXT]], [[TMP101]]
+; CHECK-NEXT: br i1 [[IV16_CHECK]], label [[DOTSPLIT15_SPLIT:%.*]], label [[DOTSPLIT15]]
+; CHECK: .split15.split:
+; CHECK-NEXT: br label [[TMP108]]
+; CHECK: 108:
+; CHECK-NEXT: [[TMP109:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP110:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP110]], label [[TMP111:%.*]], label [[TMP120:%.*]]
+; CHECK: 111:
+; CHECK-NEXT: [[TMP112:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP113:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP112]])
+; CHECK-NEXT: br label [[DOTSPLIT17:%.*]]
+; CHECK: .split17:
+; CHECK-NEXT: [[IV18:%.*]] = phi i64 [ 0, [[TMP111]] ], [ [[IV18_NEXT:%.*]], [[TMP119:%.*]] ]
+; CHECK-NEXT: [[TMP114:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV18]]
+; CHECK-NEXT: br i1 [[TMP114]], label [[TMP115:%.*]], label [[TMP119]]
+; CHECK: 115:
+; CHECK-NEXT: [[TMP116:%.*]] = mul i64 [[IV18]], [[OFFSET]]
+; CHECK-NEXT: [[TMP117:%.*]] = getelementptr i8, ptr [[TMP109]], i64 [[TMP116]]
+; CHECK-NEXT: [[TMP118:%.*]] = ptrtoint ptr [[TMP117]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP118]], i64 4)
+; CHECK-NEXT: br label [[TMP119]]
+; CHECK: 119:
+; CHECK-NEXT: [[IV18_NEXT]] = add nuw nsw i64 [[IV18]], 1
+; CHECK-NEXT: [[IV18_CHECK:%.*]] = icmp eq i64 [[IV18_NEXT]], [[TMP113]]
+; CHECK-NEXT: br i1 [[IV18_CHECK]], label [[DOTSPLIT17_SPLIT:%.*]], label [[DOTSPLIT17]]
+; CHECK: .split17.split:
+; CHECK-NEXT: br label [[TMP120]]
+; CHECK: 120:
+; CHECK-NEXT: [[TMP121:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg5.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP61]], <vscale x 1 x i32> [[TMP61]], <vscale x 1 x i32> [[TMP61]], <vscale x 1 x i32> [[TMP61]], <vscale x 1 x i32> [[TMP61]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP122:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP121]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP122]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg6_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg6_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP69]], i64 4)
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg6.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP73:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP72]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP73]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg6_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg6_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP69]], i64 4)
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg6.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP73:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP72]], 0
+; CHECK-NEXT: [[TMP74:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP74]], label [[TMP75:%.*]], label [[TMP84:%.*]]
+; CHECK: 75:
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP77:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP76]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP75]] ], [ [[IV12_NEXT:%.*]], [[TMP83:%.*]] ]
+; CHECK-NEXT: [[TMP78:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP78]], label [[TMP79:%.*]], label [[TMP83]]
+; CHECK: 79:
+; CHECK-NEXT: [[TMP80:%.*]] = mul i64 [[IV12]], [[OFFSET]]
+; CHECK-NEXT: [[TMP81:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP80]]
+; CHECK-NEXT: [[TMP82:%.*]] = ptrtoint ptr [[TMP81]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP82]], i64 4)
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP77]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[TMP85:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP86:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP86]], label [[TMP87:%.*]], label [[TMP96:%.*]]
+; CHECK: 87:
+; CHECK-NEXT: [[TMP88:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP88]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP87]] ], [ [[IV14_NEXT:%.*]], [[TMP95:%.*]] ]
+; CHECK-NEXT: [[TMP90:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP90]], label [[TMP91:%.*]], label [[TMP95]]
+; CHECK: 91:
+; CHECK-NEXT: [[TMP92:%.*]] = mul i64 [[IV14]], [[OFFSET]]
+; CHECK-NEXT: [[TMP93:%.*]] = getelementptr i8, ptr [[TMP85]], i64 [[TMP92]]
+; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr [[TMP93]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP94]], i64 4)
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP89]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP96]]
+; CHECK: 96:
+; CHECK-NEXT: [[TMP97:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP98:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP98]], label [[TMP99:%.*]], label [[TMP108:%.*]]
+; CHECK: 99:
+; CHECK-NEXT: [[TMP100:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP101:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP100]])
+; CHECK-NEXT: br label [[DOTSPLIT15:%.*]]
+; CHECK: .split15:
+; CHECK-NEXT: [[IV16:%.*]] = phi i64 [ 0, [[TMP99]] ], [ [[IV16_NEXT:%.*]], [[TMP107:%.*]] ]
+; CHECK-NEXT: [[TMP102:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV16]]
+; CHECK-NEXT: br i1 [[TMP102]], label [[TMP103:%.*]], label [[TMP107]]
+; CHECK: 103:
+; CHECK-NEXT: [[TMP104:%.*]] = mul i64 [[IV16]], [[OFFSET]]
+; CHECK-NEXT: [[TMP105:%.*]] = getelementptr i8, ptr [[TMP97]], i64 [[TMP104]]
+; CHECK-NEXT: [[TMP106:%.*]] = ptrtoint ptr [[TMP105]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP106]], i64 4)
+; CHECK-NEXT: br label [[TMP107]]
+; CHECK: 107:
+; CHECK-NEXT: [[IV16_NEXT]] = add nuw nsw i64 [[IV16]], 1
+; CHECK-NEXT: [[IV16_CHECK:%.*]] = icmp eq i64 [[IV16_NEXT]], [[TMP101]]
+; CHECK-NEXT: br i1 [[IV16_CHECK]], label [[DOTSPLIT15_SPLIT:%.*]], label [[DOTSPLIT15]]
+; CHECK: .split15.split:
+; CHECK-NEXT: br label [[TMP108]]
+; CHECK: 108:
+; CHECK-NEXT: [[TMP109:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP110:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP110]], label [[TMP111:%.*]], label [[TMP120:%.*]]
+; CHECK: 111:
+; CHECK-NEXT: [[TMP112:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP113:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP112]])
+; CHECK-NEXT: br label [[DOTSPLIT17:%.*]]
+; CHECK: .split17:
+; CHECK-NEXT: [[IV18:%.*]] = phi i64 [ 0, [[TMP111]] ], [ [[IV18_NEXT:%.*]], [[TMP119:%.*]] ]
+; CHECK-NEXT: [[TMP114:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV18]]
+; CHECK-NEXT: br i1 [[TMP114]], label [[TMP115:%.*]], label [[TMP119]]
+; CHECK: 115:
+; CHECK-NEXT: [[TMP116:%.*]] = mul i64 [[IV18]], [[OFFSET]]
+; CHECK-NEXT: [[TMP117:%.*]] = getelementptr i8, ptr [[TMP109]], i64 [[TMP116]]
+; CHECK-NEXT: [[TMP118:%.*]] = ptrtoint ptr [[TMP117]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP118]], i64 4)
+; CHECK-NEXT: br label [[TMP119]]
+; CHECK: 119:
+; CHECK-NEXT: [[IV18_NEXT]] = add nuw nsw i64 [[IV18]], 1
+; CHECK-NEXT: [[IV18_CHECK:%.*]] = icmp eq i64 [[IV18_NEXT]], [[TMP113]]
+; CHECK-NEXT: br i1 [[IV18_CHECK]], label [[DOTSPLIT17_SPLIT:%.*]], label [[DOTSPLIT17]]
+; CHECK: .split17.split:
+; CHECK-NEXT: br label [[TMP120]]
+; CHECK: 120:
+; CHECK-NEXT: [[TMP121:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP122:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP122]], label [[TMP123:%.*]], label [[TMP132:%.*]]
+; CHECK: 123:
+; CHECK-NEXT: [[TMP124:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP125:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP124]])
+; CHECK-NEXT: br label [[DOTSPLIT19:%.*]]
+; CHECK: .split19:
+; CHECK-NEXT: [[IV20:%.*]] = phi i64 [ 0, [[TMP123]] ], [ [[IV20_NEXT:%.*]], [[TMP131:%.*]] ]
+; CHECK-NEXT: [[TMP126:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV20]]
+; CHECK-NEXT: br i1 [[TMP126]], label [[TMP127:%.*]], label [[TMP131]]
+; CHECK: 127:
+; CHECK-NEXT: [[TMP128:%.*]] = mul i64 [[IV20]], [[OFFSET]]
+; CHECK-NEXT: [[TMP129:%.*]] = getelementptr i8, ptr [[TMP121]], i64 [[TMP128]]
+; CHECK-NEXT: [[TMP130:%.*]] = ptrtoint ptr [[TMP129]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP130]], i64 4)
+; CHECK-NEXT: br label [[TMP131]]
+; CHECK: 131:
+; CHECK-NEXT: [[IV20_NEXT]] = add nuw nsw i64 [[IV20]], 1
+; CHECK-NEXT: [[IV20_CHECK:%.*]] = icmp eq i64 [[IV20_NEXT]], [[TMP125]]
+; CHECK-NEXT: br i1 [[IV20_CHECK]], label [[DOTSPLIT19_SPLIT:%.*]], label [[DOTSPLIT19]]
+; CHECK: .split19.split:
+; CHECK-NEXT: br label [[TMP132]]
+; CHECK: 132:
+; CHECK-NEXT: [[TMP133:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP134:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP134]], label [[TMP135:%.*]], label [[TMP144:%.*]]
+; CHECK: 135:
+; CHECK-NEXT: [[TMP136:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP137:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP136]])
+; CHECK-NEXT: br label [[DOTSPLIT21:%.*]]
+; CHECK: .split21:
+; CHECK-NEXT: [[IV22:%.*]] = phi i64 [ 0, [[TMP135]] ], [ [[IV22_NEXT:%.*]], [[TMP143:%.*]] ]
+; CHECK-NEXT: [[TMP138:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV22]]
+; CHECK-NEXT: br i1 [[TMP138]], label [[TMP139:%.*]], label [[TMP143]]
+; CHECK: 139:
+; CHECK-NEXT: [[TMP140:%.*]] = mul i64 [[IV22]], [[OFFSET]]
+; CHECK-NEXT: [[TMP141:%.*]] = getelementptr i8, ptr [[TMP133]], i64 [[TMP140]]
+; CHECK-NEXT: [[TMP142:%.*]] = ptrtoint ptr [[TMP141]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP142]], i64 4)
+; CHECK-NEXT: br label [[TMP143]]
+; CHECK: 143:
+; CHECK-NEXT: [[IV22_NEXT]] = add nuw nsw i64 [[IV22]], 1
+; CHECK-NEXT: [[IV22_CHECK:%.*]] = icmp eq i64 [[IV22_NEXT]], [[TMP137]]
+; CHECK-NEXT: br i1 [[IV22_CHECK]], label [[DOTSPLIT21_SPLIT:%.*]], label [[DOTSPLIT21]]
+; CHECK: .split21.split:
+; CHECK-NEXT: br label [[TMP144]]
+; CHECK: 144:
+; CHECK-NEXT: [[TMP145:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg6.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP73]], <vscale x 1 x i32> [[TMP73]], <vscale x 1 x i32> [[TMP73]], <vscale x 1 x i32> [[TMP73]], <vscale x 1 x i32> [[TMP73]], <vscale x 1 x i32> [[TMP73]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP146:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP145]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP146]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg7_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg7_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP69]], i64 4)
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], [[OFFSET]]
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP81]], i64 4)
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[TMP84:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg7.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP85:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP84]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP85]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg7_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg7_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP69]], i64 4)
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], [[OFFSET]]
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP81]], i64 4)
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[TMP84:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg7.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP85:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP84]], 0
+; CHECK-NEXT: [[TMP86:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP86]], label [[TMP87:%.*]], label [[TMP96:%.*]]
+; CHECK: 87:
+; CHECK-NEXT: [[TMP88:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP88]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP87]] ], [ [[IV14_NEXT:%.*]], [[TMP95:%.*]] ]
+; CHECK-NEXT: [[TMP90:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP90]], label [[TMP91:%.*]], label [[TMP95]]
+; CHECK: 91:
+; CHECK-NEXT: [[TMP92:%.*]] = mul i64 [[IV14]], [[OFFSET]]
+; CHECK-NEXT: [[TMP93:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP92]]
+; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr [[TMP93]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP94]], i64 4)
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP89]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP96]]
+; CHECK: 96:
+; CHECK-NEXT: [[TMP97:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP98:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP98]], label [[TMP99:%.*]], label [[TMP108:%.*]]
+; CHECK: 99:
+; CHECK-NEXT: [[TMP100:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP101:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP100]])
+; CHECK-NEXT: br label [[DOTSPLIT15:%.*]]
+; CHECK: .split15:
+; CHECK-NEXT: [[IV16:%.*]] = phi i64 [ 0, [[TMP99]] ], [ [[IV16_NEXT:%.*]], [[TMP107:%.*]] ]
+; CHECK-NEXT: [[TMP102:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV16]]
+; CHECK-NEXT: br i1 [[TMP102]], label [[TMP103:%.*]], label [[TMP107]]
+; CHECK: 103:
+; CHECK-NEXT: [[TMP104:%.*]] = mul i64 [[IV16]], [[OFFSET]]
+; CHECK-NEXT: [[TMP105:%.*]] = getelementptr i8, ptr [[TMP97]], i64 [[TMP104]]
+; CHECK-NEXT: [[TMP106:%.*]] = ptrtoint ptr [[TMP105]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP106]], i64 4)
+; CHECK-NEXT: br label [[TMP107]]
+; CHECK: 107:
+; CHECK-NEXT: [[IV16_NEXT]] = add nuw nsw i64 [[IV16]], 1
+; CHECK-NEXT: [[IV16_CHECK:%.*]] = icmp eq i64 [[IV16_NEXT]], [[TMP101]]
+; CHECK-NEXT: br i1 [[IV16_CHECK]], label [[DOTSPLIT15_SPLIT:%.*]], label [[DOTSPLIT15]]
+; CHECK: .split15.split:
+; CHECK-NEXT: br label [[TMP108]]
+; CHECK: 108:
+; CHECK-NEXT: [[TMP109:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP110:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP110]], label [[TMP111:%.*]], label [[TMP120:%.*]]
+; CHECK: 111:
+; CHECK-NEXT: [[TMP112:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP113:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP112]])
+; CHECK-NEXT: br label [[DOTSPLIT17:%.*]]
+; CHECK: .split17:
+; CHECK-NEXT: [[IV18:%.*]] = phi i64 [ 0, [[TMP111]] ], [ [[IV18_NEXT:%.*]], [[TMP119:%.*]] ]
+; CHECK-NEXT: [[TMP114:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV18]]
+; CHECK-NEXT: br i1 [[TMP114]], label [[TMP115:%.*]], label [[TMP119]]
+; CHECK: 115:
+; CHECK-NEXT: [[TMP116:%.*]] = mul i64 [[IV18]], [[OFFSET]]
+; CHECK-NEXT: [[TMP117:%.*]] = getelementptr i8, ptr [[TMP109]], i64 [[TMP116]]
+; CHECK-NEXT: [[TMP118:%.*]] = ptrtoint ptr [[TMP117]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP118]], i64 4)
+; CHECK-NEXT: br label [[TMP119]]
+; CHECK: 119:
+; CHECK-NEXT: [[IV18_NEXT]] = add nuw nsw i64 [[IV18]], 1
+; CHECK-NEXT: [[IV18_CHECK:%.*]] = icmp eq i64 [[IV18_NEXT]], [[TMP113]]
+; CHECK-NEXT: br i1 [[IV18_CHECK]], label [[DOTSPLIT17_SPLIT:%.*]], label [[DOTSPLIT17]]
+; CHECK: .split17.split:
+; CHECK-NEXT: br label [[TMP120]]
+; CHECK: 120:
+; CHECK-NEXT: [[TMP121:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP122:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP122]], label [[TMP123:%.*]], label [[TMP132:%.*]]
+; CHECK: 123:
+; CHECK-NEXT: [[TMP124:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP125:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP124]])
+; CHECK-NEXT: br label [[DOTSPLIT19:%.*]]
+; CHECK: .split19:
+; CHECK-NEXT: [[IV20:%.*]] = phi i64 [ 0, [[TMP123]] ], [ [[IV20_NEXT:%.*]], [[TMP131:%.*]] ]
+; CHECK-NEXT: [[TMP126:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV20]]
+; CHECK-NEXT: br i1 [[TMP126]], label [[TMP127:%.*]], label [[TMP131]]
+; CHECK: 127:
+; CHECK-NEXT: [[TMP128:%.*]] = mul i64 [[IV20]], [[OFFSET]]
+; CHECK-NEXT: [[TMP129:%.*]] = getelementptr i8, ptr [[TMP121]], i64 [[TMP128]]
+; CHECK-NEXT: [[TMP130:%.*]] = ptrtoint ptr [[TMP129]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP130]], i64 4)
+; CHECK-NEXT: br label [[TMP131]]
+; CHECK: 131:
+; CHECK-NEXT: [[IV20_NEXT]] = add nuw nsw i64 [[IV20]], 1
+; CHECK-NEXT: [[IV20_CHECK:%.*]] = icmp eq i64 [[IV20_NEXT]], [[TMP125]]
+; CHECK-NEXT: br i1 [[IV20_CHECK]], label [[DOTSPLIT19_SPLIT:%.*]], label [[DOTSPLIT19]]
+; CHECK: .split19.split:
+; CHECK-NEXT: br label [[TMP132]]
+; CHECK: 132:
+; CHECK-NEXT: [[TMP133:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP134:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP134]], label [[TMP135:%.*]], label [[TMP144:%.*]]
+; CHECK: 135:
+; CHECK-NEXT: [[TMP136:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP137:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP136]])
+; CHECK-NEXT: br label [[DOTSPLIT21:%.*]]
+; CHECK: .split21:
+; CHECK-NEXT: [[IV22:%.*]] = phi i64 [ 0, [[TMP135]] ], [ [[IV22_NEXT:%.*]], [[TMP143:%.*]] ]
+; CHECK-NEXT: [[TMP138:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV22]]
+; CHECK-NEXT: br i1 [[TMP138]], label [[TMP139:%.*]], label [[TMP143]]
+; CHECK: 139:
+; CHECK-NEXT: [[TMP140:%.*]] = mul i64 [[IV22]], [[OFFSET]]
+; CHECK-NEXT: [[TMP141:%.*]] = getelementptr i8, ptr [[TMP133]], i64 [[TMP140]]
+; CHECK-NEXT: [[TMP142:%.*]] = ptrtoint ptr [[TMP141]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP142]], i64 4)
+; CHECK-NEXT: br label [[TMP143]]
+; CHECK: 143:
+; CHECK-NEXT: [[IV22_NEXT]] = add nuw nsw i64 [[IV22]], 1
+; CHECK-NEXT: [[IV22_CHECK:%.*]] = icmp eq i64 [[IV22_NEXT]], [[TMP137]]
+; CHECK-NEXT: br i1 [[IV22_CHECK]], label [[DOTSPLIT21_SPLIT:%.*]], label [[DOTSPLIT21]]
+; CHECK: .split21.split:
+; CHECK-NEXT: br label [[TMP144]]
+; CHECK: 144:
+; CHECK-NEXT: [[TMP145:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP146:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP146]], label [[TMP147:%.*]], label [[TMP156:%.*]]
+; CHECK: 147:
+; CHECK-NEXT: [[TMP148:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP149:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP148]])
+; CHECK-NEXT: br label [[DOTSPLIT23:%.*]]
+; CHECK: .split23:
+; CHECK-NEXT: [[IV24:%.*]] = phi i64 [ 0, [[TMP147]] ], [ [[IV24_NEXT:%.*]], [[TMP155:%.*]] ]
+; CHECK-NEXT: [[TMP150:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV24]]
+; CHECK-NEXT: br i1 [[TMP150]], label [[TMP151:%.*]], label [[TMP155]]
+; CHECK: 151:
+; CHECK-NEXT: [[TMP152:%.*]] = mul i64 [[IV24]], [[OFFSET]]
+; CHECK-NEXT: [[TMP153:%.*]] = getelementptr i8, ptr [[TMP145]], i64 [[TMP152]]
+; CHECK-NEXT: [[TMP154:%.*]] = ptrtoint ptr [[TMP153]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP154]], i64 4)
+; CHECK-NEXT: br label [[TMP155]]
+; CHECK: 155:
+; CHECK-NEXT: [[IV24_NEXT]] = add nuw nsw i64 [[IV24]], 1
+; CHECK-NEXT: [[IV24_CHECK:%.*]] = icmp eq i64 [[IV24_NEXT]], [[TMP149]]
+; CHECK-NEXT: br i1 [[IV24_CHECK]], label [[DOTSPLIT23_SPLIT:%.*]], label [[DOTSPLIT23]]
+; CHECK: .split23.split:
+; CHECK-NEXT: br label [[TMP156]]
+; CHECK: 156:
+; CHECK-NEXT: [[TMP157:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP158:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP158]], label [[TMP159:%.*]], label [[TMP168:%.*]]
+; CHECK: 159:
+; CHECK-NEXT: [[TMP160:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP161:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP160]])
+; CHECK-NEXT: br label [[DOTSPLIT25:%.*]]
+; CHECK: .split25:
+; CHECK-NEXT: [[IV26:%.*]] = phi i64 [ 0, [[TMP159]] ], [ [[IV26_NEXT:%.*]], [[TMP167:%.*]] ]
+; CHECK-NEXT: [[TMP162:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV26]]
+; CHECK-NEXT: br i1 [[TMP162]], label [[TMP163:%.*]], label [[TMP167]]
+; CHECK: 163:
+; CHECK-NEXT: [[TMP164:%.*]] = mul i64 [[IV26]], [[OFFSET]]
+; CHECK-NEXT: [[TMP165:%.*]] = getelementptr i8, ptr [[TMP157]], i64 [[TMP164]]
+; CHECK-NEXT: [[TMP166:%.*]] = ptrtoint ptr [[TMP165]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP166]], i64 4)
+; CHECK-NEXT: br label [[TMP167]]
+; CHECK: 167:
+; CHECK-NEXT: [[IV26_NEXT]] = add nuw nsw i64 [[IV26]], 1
+; CHECK-NEXT: [[IV26_CHECK:%.*]] = icmp eq i64 [[IV26_NEXT]], [[TMP161]]
+; CHECK-NEXT: br i1 [[IV26_CHECK]], label [[DOTSPLIT25_SPLIT:%.*]], label [[DOTSPLIT25]]
+; CHECK: .split25.split:
+; CHECK-NEXT: br label [[TMP168]]
+; CHECK: 168:
+; CHECK-NEXT: [[TMP169:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg7.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP85]], <vscale x 1 x i32> [[TMP85]], <vscale x 1 x i32> [[TMP85]], <vscale x 1 x i32> [[TMP85]], <vscale x 1 x i32> [[TMP85]], <vscale x 1 x i32> [[TMP85]], <vscale x 1 x i32> [[TMP85]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP170:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP169]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP170]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg8_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg8_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP69]], i64 4)
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], [[OFFSET]]
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP81]], i64 4)
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[TMP84:%.*]] = getelementptr i8, ptr [[BASE]], i64 28
+; CHECK-NEXT: [[TMP85:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP85]], label [[TMP86:%.*]], label [[TMP95:%.*]]
+; CHECK: 86:
+; CHECK-NEXT: [[TMP87:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP88:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP87]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP86]] ], [ [[IV14_NEXT:%.*]], [[TMP94:%.*]] ]
+; CHECK-NEXT: [[TMP89:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP89]], label [[TMP90:%.*]], label [[TMP94]]
+; CHECK: 90:
+; CHECK-NEXT: [[TMP91:%.*]] = mul i64 [[IV14]], [[OFFSET]]
+; CHECK-NEXT: [[TMP92:%.*]] = getelementptr i8, ptr [[TMP84]], i64 [[TMP91]]
+; CHECK-NEXT: [[TMP93:%.*]] = ptrtoint ptr [[TMP92]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP93]], i64 4)
+; CHECK-NEXT: br label [[TMP94]]
+; CHECK: 94:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP88]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[TMP96:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg8.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP97:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP96]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP97]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg8_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg8_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP69]], i64 4)
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], [[OFFSET]]
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP81]], i64 4)
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[TMP84:%.*]] = getelementptr i8, ptr [[BASE]], i64 28
+; CHECK-NEXT: [[TMP85:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP85]], label [[TMP86:%.*]], label [[TMP95:%.*]]
+; CHECK: 86:
+; CHECK-NEXT: [[TMP87:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP88:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP87]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP86]] ], [ [[IV14_NEXT:%.*]], [[TMP94:%.*]] ]
+; CHECK-NEXT: [[TMP89:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP89]], label [[TMP90:%.*]], label [[TMP94]]
+; CHECK: 90:
+; CHECK-NEXT: [[TMP91:%.*]] = mul i64 [[IV14]], [[OFFSET]]
+; CHECK-NEXT: [[TMP92:%.*]] = getelementptr i8, ptr [[TMP84]], i64 [[TMP91]]
+; CHECK-NEXT: [[TMP93:%.*]] = ptrtoint ptr [[TMP92]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP93]], i64 4)
+; CHECK-NEXT: br label [[TMP94]]
+; CHECK: 94:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP88]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[TMP96:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg8.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: [[TMP97:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP96]], 0
+; CHECK-NEXT: [[TMP98:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP98]], label [[TMP99:%.*]], label [[TMP108:%.*]]
+; CHECK: 99:
+; CHECK-NEXT: [[TMP100:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP101:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP100]])
+; CHECK-NEXT: br label [[DOTSPLIT15:%.*]]
+; CHECK: .split15:
+; CHECK-NEXT: [[IV16:%.*]] = phi i64 [ 0, [[TMP99]] ], [ [[IV16_NEXT:%.*]], [[TMP107:%.*]] ]
+; CHECK-NEXT: [[TMP102:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV16]]
+; CHECK-NEXT: br i1 [[TMP102]], label [[TMP103:%.*]], label [[TMP107]]
+; CHECK: 103:
+; CHECK-NEXT: [[TMP104:%.*]] = mul i64 [[IV16]], [[OFFSET]]
+; CHECK-NEXT: [[TMP105:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP104]]
+; CHECK-NEXT: [[TMP106:%.*]] = ptrtoint ptr [[TMP105]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP106]], i64 4)
+; CHECK-NEXT: br label [[TMP107]]
+; CHECK: 107:
+; CHECK-NEXT: [[IV16_NEXT]] = add nuw nsw i64 [[IV16]], 1
+; CHECK-NEXT: [[IV16_CHECK:%.*]] = icmp eq i64 [[IV16_NEXT]], [[TMP101]]
+; CHECK-NEXT: br i1 [[IV16_CHECK]], label [[DOTSPLIT15_SPLIT:%.*]], label [[DOTSPLIT15]]
+; CHECK: .split15.split:
+; CHECK-NEXT: br label [[TMP108]]
+; CHECK: 108:
+; CHECK-NEXT: [[TMP109:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP110:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP110]], label [[TMP111:%.*]], label [[TMP120:%.*]]
+; CHECK: 111:
+; CHECK-NEXT: [[TMP112:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP113:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP112]])
+; CHECK-NEXT: br label [[DOTSPLIT17:%.*]]
+; CHECK: .split17:
+; CHECK-NEXT: [[IV18:%.*]] = phi i64 [ 0, [[TMP111]] ], [ [[IV18_NEXT:%.*]], [[TMP119:%.*]] ]
+; CHECK-NEXT: [[TMP114:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV18]]
+; CHECK-NEXT: br i1 [[TMP114]], label [[TMP115:%.*]], label [[TMP119]]
+; CHECK: 115:
+; CHECK-NEXT: [[TMP116:%.*]] = mul i64 [[IV18]], [[OFFSET]]
+; CHECK-NEXT: [[TMP117:%.*]] = getelementptr i8, ptr [[TMP109]], i64 [[TMP116]]
+; CHECK-NEXT: [[TMP118:%.*]] = ptrtoint ptr [[TMP117]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP118]], i64 4)
+; CHECK-NEXT: br label [[TMP119]]
+; CHECK: 119:
+; CHECK-NEXT: [[IV18_NEXT]] = add nuw nsw i64 [[IV18]], 1
+; CHECK-NEXT: [[IV18_CHECK:%.*]] = icmp eq i64 [[IV18_NEXT]], [[TMP113]]
+; CHECK-NEXT: br i1 [[IV18_CHECK]], label [[DOTSPLIT17_SPLIT:%.*]], label [[DOTSPLIT17]]
+; CHECK: .split17.split:
+; CHECK-NEXT: br label [[TMP120]]
+; CHECK: 120:
+; CHECK-NEXT: [[TMP121:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP122:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP122]], label [[TMP123:%.*]], label [[TMP132:%.*]]
+; CHECK: 123:
+; CHECK-NEXT: [[TMP124:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP125:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP124]])
+; CHECK-NEXT: br label [[DOTSPLIT19:%.*]]
+; CHECK: .split19:
+; CHECK-NEXT: [[IV20:%.*]] = phi i64 [ 0, [[TMP123]] ], [ [[IV20_NEXT:%.*]], [[TMP131:%.*]] ]
+; CHECK-NEXT: [[TMP126:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV20]]
+; CHECK-NEXT: br i1 [[TMP126]], label [[TMP127:%.*]], label [[TMP131]]
+; CHECK: 127:
+; CHECK-NEXT: [[TMP128:%.*]] = mul i64 [[IV20]], [[OFFSET]]
+; CHECK-NEXT: [[TMP129:%.*]] = getelementptr i8, ptr [[TMP121]], i64 [[TMP128]]
+; CHECK-NEXT: [[TMP130:%.*]] = ptrtoint ptr [[TMP129]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP130]], i64 4)
+; CHECK-NEXT: br label [[TMP131]]
+; CHECK: 131:
+; CHECK-NEXT: [[IV20_NEXT]] = add nuw nsw i64 [[IV20]], 1
+; CHECK-NEXT: [[IV20_CHECK:%.*]] = icmp eq i64 [[IV20_NEXT]], [[TMP125]]
+; CHECK-NEXT: br i1 [[IV20_CHECK]], label [[DOTSPLIT19_SPLIT:%.*]], label [[DOTSPLIT19]]
+; CHECK: .split19.split:
+; CHECK-NEXT: br label [[TMP132]]
+; CHECK: 132:
+; CHECK-NEXT: [[TMP133:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP134:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP134]], label [[TMP135:%.*]], label [[TMP144:%.*]]
+; CHECK: 135:
+; CHECK-NEXT: [[TMP136:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP137:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP136]])
+; CHECK-NEXT: br label [[DOTSPLIT21:%.*]]
+; CHECK: .split21:
+; CHECK-NEXT: [[IV22:%.*]] = phi i64 [ 0, [[TMP135]] ], [ [[IV22_NEXT:%.*]], [[TMP143:%.*]] ]
+; CHECK-NEXT: [[TMP138:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV22]]
+; CHECK-NEXT: br i1 [[TMP138]], label [[TMP139:%.*]], label [[TMP143]]
+; CHECK: 139:
+; CHECK-NEXT: [[TMP140:%.*]] = mul i64 [[IV22]], [[OFFSET]]
+; CHECK-NEXT: [[TMP141:%.*]] = getelementptr i8, ptr [[TMP133]], i64 [[TMP140]]
+; CHECK-NEXT: [[TMP142:%.*]] = ptrtoint ptr [[TMP141]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP142]], i64 4)
+; CHECK-NEXT: br label [[TMP143]]
+; CHECK: 143:
+; CHECK-NEXT: [[IV22_NEXT]] = add nuw nsw i64 [[IV22]], 1
+; CHECK-NEXT: [[IV22_CHECK:%.*]] = icmp eq i64 [[IV22_NEXT]], [[TMP137]]
+; CHECK-NEXT: br i1 [[IV22_CHECK]], label [[DOTSPLIT21_SPLIT:%.*]], label [[DOTSPLIT21]]
+; CHECK: .split21.split:
+; CHECK-NEXT: br label [[TMP144]]
+; CHECK: 144:
+; CHECK-NEXT: [[TMP145:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP146:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP146]], label [[TMP147:%.*]], label [[TMP156:%.*]]
+; CHECK: 147:
+; CHECK-NEXT: [[TMP148:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP149:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP148]])
+; CHECK-NEXT: br label [[DOTSPLIT23:%.*]]
+; CHECK: .split23:
+; CHECK-NEXT: [[IV24:%.*]] = phi i64 [ 0, [[TMP147]] ], [ [[IV24_NEXT:%.*]], [[TMP155:%.*]] ]
+; CHECK-NEXT: [[TMP150:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV24]]
+; CHECK-NEXT: br i1 [[TMP150]], label [[TMP151:%.*]], label [[TMP155]]
+; CHECK: 151:
+; CHECK-NEXT: [[TMP152:%.*]] = mul i64 [[IV24]], [[OFFSET]]
+; CHECK-NEXT: [[TMP153:%.*]] = getelementptr i8, ptr [[TMP145]], i64 [[TMP152]]
+; CHECK-NEXT: [[TMP154:%.*]] = ptrtoint ptr [[TMP153]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP154]], i64 4)
+; CHECK-NEXT: br label [[TMP155]]
+; CHECK: 155:
+; CHECK-NEXT: [[IV24_NEXT]] = add nuw nsw i64 [[IV24]], 1
+; CHECK-NEXT: [[IV24_CHECK:%.*]] = icmp eq i64 [[IV24_NEXT]], [[TMP149]]
+; CHECK-NEXT: br i1 [[IV24_CHECK]], label [[DOTSPLIT23_SPLIT:%.*]], label [[DOTSPLIT23]]
+; CHECK: .split23.split:
+; CHECK-NEXT: br label [[TMP156]]
+; CHECK: 156:
+; CHECK-NEXT: [[TMP157:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP158:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP158]], label [[TMP159:%.*]], label [[TMP168:%.*]]
+; CHECK: 159:
+; CHECK-NEXT: [[TMP160:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP161:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP160]])
+; CHECK-NEXT: br label [[DOTSPLIT25:%.*]]
+; CHECK: .split25:
+; CHECK-NEXT: [[IV26:%.*]] = phi i64 [ 0, [[TMP159]] ], [ [[IV26_NEXT:%.*]], [[TMP167:%.*]] ]
+; CHECK-NEXT: [[TMP162:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV26]]
+; CHECK-NEXT: br i1 [[TMP162]], label [[TMP163:%.*]], label [[TMP167]]
+; CHECK: 163:
+; CHECK-NEXT: [[TMP164:%.*]] = mul i64 [[IV26]], [[OFFSET]]
+; CHECK-NEXT: [[TMP165:%.*]] = getelementptr i8, ptr [[TMP157]], i64 [[TMP164]]
+; CHECK-NEXT: [[TMP166:%.*]] = ptrtoint ptr [[TMP165]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP166]], i64 4)
+; CHECK-NEXT: br label [[TMP167]]
+; CHECK: 167:
+; CHECK-NEXT: [[IV26_NEXT]] = add nuw nsw i64 [[IV26]], 1
+; CHECK-NEXT: [[IV26_CHECK:%.*]] = icmp eq i64 [[IV26_NEXT]], [[TMP161]]
+; CHECK-NEXT: br i1 [[IV26_CHECK]], label [[DOTSPLIT25_SPLIT:%.*]], label [[DOTSPLIT25]]
+; CHECK: .split25.split:
+; CHECK-NEXT: br label [[TMP168]]
+; CHECK: 168:
+; CHECK-NEXT: [[TMP169:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP170:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP170]], label [[TMP171:%.*]], label [[TMP180:%.*]]
+; CHECK: 171:
+; CHECK-NEXT: [[TMP172:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP173:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP172]])
+; CHECK-NEXT: br label [[DOTSPLIT27:%.*]]
+; CHECK: .split27:
+; CHECK-NEXT: [[IV28:%.*]] = phi i64 [ 0, [[TMP171]] ], [ [[IV28_NEXT:%.*]], [[TMP179:%.*]] ]
+; CHECK-NEXT: [[TMP174:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV28]]
+; CHECK-NEXT: br i1 [[TMP174]], label [[TMP175:%.*]], label [[TMP179]]
+; CHECK: 175:
+; CHECK-NEXT: [[TMP176:%.*]] = mul i64 [[IV28]], [[OFFSET]]
+; CHECK-NEXT: [[TMP177:%.*]] = getelementptr i8, ptr [[TMP169]], i64 [[TMP176]]
+; CHECK-NEXT: [[TMP178:%.*]] = ptrtoint ptr [[TMP177]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP178]], i64 4)
+; CHECK-NEXT: br label [[TMP179]]
+; CHECK: 179:
+; CHECK-NEXT: [[IV28_NEXT]] = add nuw nsw i64 [[IV28]], 1
+; CHECK-NEXT: [[IV28_CHECK:%.*]] = icmp eq i64 [[IV28_NEXT]], [[TMP173]]
+; CHECK-NEXT: br i1 [[IV28_CHECK]], label [[DOTSPLIT27_SPLIT:%.*]], label [[DOTSPLIT27]]
+; CHECK: .split27.split:
+; CHECK-NEXT: br label [[TMP180]]
+; CHECK: 180:
+; CHECK-NEXT: [[TMP181:%.*]] = getelementptr i8, ptr [[BASE]], i64 28
+; CHECK-NEXT: [[TMP182:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP182]], label [[TMP183:%.*]], label [[TMP192:%.*]]
+; CHECK: 183:
+; CHECK-NEXT: [[TMP184:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP185:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP184]])
+; CHECK-NEXT: br label [[DOTSPLIT29:%.*]]
+; CHECK: .split29:
+; CHECK-NEXT: [[IV30:%.*]] = phi i64 [ 0, [[TMP183]] ], [ [[IV30_NEXT:%.*]], [[TMP191:%.*]] ]
+; CHECK-NEXT: [[TMP186:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV30]]
+; CHECK-NEXT: br i1 [[TMP186]], label [[TMP187:%.*]], label [[TMP191]]
+; CHECK: 187:
+; CHECK-NEXT: [[TMP188:%.*]] = mul i64 [[IV30]], [[OFFSET]]
+; CHECK-NEXT: [[TMP189:%.*]] = getelementptr i8, ptr [[TMP181]], i64 [[TMP188]]
+; CHECK-NEXT: [[TMP190:%.*]] = ptrtoint ptr [[TMP189]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP190]], i64 4)
+; CHECK-NEXT: br label [[TMP191]]
+; CHECK: 191:
+; CHECK-NEXT: [[IV30_NEXT]] = add nuw nsw i64 [[IV30]], 1
+; CHECK-NEXT: [[IV30_CHECK:%.*]] = icmp eq i64 [[IV30_NEXT]], [[TMP185]]
+; CHECK-NEXT: br i1 [[IV30_CHECK]], label [[DOTSPLIT29_SPLIT:%.*]], label [[DOTSPLIT29]]
+; CHECK: .split29.split:
+; CHECK-NEXT: br label [[TMP192]]
+; CHECK: 192:
+; CHECK-NEXT: [[TMP193:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg8.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP97]], <vscale x 1 x i32> [[TMP97]], <vscale x 1 x i32> [[TMP97]], <vscale x 1 x i32> [[TMP97]], <vscale x 1 x i32> [[TMP97]], <vscale x 1 x i32> [[TMP97]], <vscale x 1 x i32> [[TMP97]], <vscale x 1 x i32> [[TMP97]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP194:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP193]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP194]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare void @llvm.riscv.vssseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg2_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg2_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg2.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg2_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg2_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg2.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vssseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg3_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg3_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg3.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg3_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg3_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg3.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vssseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg4_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg4_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg4.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg4_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg4_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg4.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vssseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg5_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg5_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg5.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg5_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg5_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg5.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vssseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg6_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg6_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP69]], i64 4)
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg6.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg6_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg6_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP69]], i64 4)
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg6.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vssseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg7_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg7_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP69]], i64 4)
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], [[OFFSET]]
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP81]], i64 4)
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg7.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg7_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg7_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP69]], i64 4)
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], [[OFFSET]]
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP81]], i64 4)
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg7.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vssseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg8_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg8_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP69]], i64 4)
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], [[OFFSET]]
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP81]], i64 4)
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[TMP84:%.*]] = getelementptr i8, ptr [[BASE]], i64 28
+; CHECK-NEXT: [[TMP85:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP85]], label [[TMP86:%.*]], label [[TMP95:%.*]]
+; CHECK: 86:
+; CHECK-NEXT: [[TMP87:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP88:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP87]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP86]] ], [ [[IV14_NEXT:%.*]], [[TMP94:%.*]] ]
+; CHECK-NEXT: [[TMP89:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP89]], label [[TMP90:%.*]], label [[TMP94]]
+; CHECK: 90:
+; CHECK-NEXT: [[TMP91:%.*]] = mul i64 [[IV14]], [[OFFSET]]
+; CHECK-NEXT: [[TMP92:%.*]] = getelementptr i8, ptr [[TMP84]], i64 [[TMP91]]
+; CHECK-NEXT: [[TMP93:%.*]] = ptrtoint ptr [[TMP92]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP93]], i64 4)
+; CHECK-NEXT: br label [[TMP94]]
+; CHECK: 94:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP88]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg8.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg8_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg8_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 4)
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[BASE]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP23:%.*]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP15]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV2_NEXT:%.*]], [[TMP22:%.*]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP22]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[IV2]], [[OFFSET]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP21]], i64 4)
+; CHECK-NEXT: br label [[TMP22]]
+; CHECK: 22:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP16]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BASE]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP35:%.*]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP28:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP27]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP26]] ], [ [[IV4_NEXT:%.*]], [[TMP34:%.*]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP34]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[IV4]], [[OFFSET]]
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP33]], i64 4)
+; CHECK-NEXT: br label [[TMP34]]
+; CHECK: 34:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP28]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[BASE]], i64 12
+; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[TMP38:%.*]], label [[TMP47:%.*]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP39]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP38]] ], [ [[IV6_NEXT:%.*]], [[TMP46:%.*]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP46]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[IV6]], [[OFFSET]]
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP36]], i64 [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP45]], i64 4)
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP40]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr [[BASE]], i64 16
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[TMP50:%.*]], label [[TMP59:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP51]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP50]] ], [ [[IV8_NEXT:%.*]], [[TMP58:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP58]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[IV8]], [[OFFSET]]
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[TMP48]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr [[TMP56]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP57]], i64 4)
+; CHECK-NEXT: br label [[TMP58]]
+; CHECK: 58:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP52]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[BASE]], i64 20
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP71:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP63]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP62]] ], [ [[IV10_NEXT:%.*]], [[TMP70:%.*]] ]
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP70]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[IV10]], [[OFFSET]]
+; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[TMP60]], i64 [[TMP67]]
+; CHECK-NEXT: [[TMP69:%.*]] = ptrtoint ptr [[TMP68]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP69]], i64 4)
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP64]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i8, ptr [[BASE]], i64 24
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[TMP74:%.*]], label [[TMP83:%.*]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP76:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP75]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP74]] ], [ [[IV12_NEXT:%.*]], [[TMP82:%.*]] ]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP77]], label [[TMP78:%.*]], label [[TMP82]]
+; CHECK: 78:
+; CHECK-NEXT: [[TMP79:%.*]] = mul i64 [[IV12]], [[OFFSET]]
+; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP72]], i64 [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = ptrtoint ptr [[TMP80]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP81]], i64 4)
+; CHECK-NEXT: br label [[TMP82]]
+; CHECK: 82:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP76]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[TMP84:%.*]] = getelementptr i8, ptr [[BASE]], i64 28
+; CHECK-NEXT: [[TMP85:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP85]], label [[TMP86:%.*]], label [[TMP95:%.*]]
+; CHECK: 86:
+; CHECK-NEXT: [[TMP87:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP88:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP87]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP86]] ], [ [[IV14_NEXT:%.*]], [[TMP94:%.*]] ]
+; CHECK-NEXT: [[TMP89:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP89]], label [[TMP90:%.*]], label [[TMP94]]
+; CHECK: 90:
+; CHECK-NEXT: [[TMP91:%.*]] = mul i64 [[IV14]], [[OFFSET]]
+; CHECK-NEXT: [[TMP92:%.*]] = getelementptr i8, ptr [[TMP84]], i64 [[TMP91]]
+; CHECK-NEXT: [[TMP93:%.*]] = ptrtoint ptr [[TMP92]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP93]], i64 4)
+; CHECK-NEXT: br label [[TMP94]]
+; CHECK: 94:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP88]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg8.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+; Test stride value is a multiple of pointer alignment.
+define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32_align(<vscale x 1 x i32>* align 4 %0, i64 %1, i64 %2) sanitize_address {
+; CHECK-LABEL: @intrinsic_vlse_v_nxv1i32_nxv1i32_align(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP2:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP14:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP13]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[IV]], 4
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], i64 [[TMP10]]
+; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP12]])
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> undef, ptr [[TMP0]], i64 4, i64 [[TMP2]])
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(
+ <vscale x 1 x i32> undef,
+ <vscale x 1 x i32>* %0,
+ i64 4,
+ i64 %2)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i64 %2) sanitize_address {
+; CHECK-LABEL: @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP4:%.*]] = zext <vscale x 1 x i16> [[TMP1:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP2:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP8]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, ptr [[TMP0]], <vscale x 1 x i16> [[TMP1]], i64 [[TMP2]])
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> undef,
+ <vscale x 1 x i32>* %0,
+ <vscale x 1 x i16> %1,
+ i64 %2)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i1>,
+ i64,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {
+; CHECK-LABEL: @intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP6:%.*]] = zext <vscale x 1 x i16> [[TMP2:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[TMP4:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP10]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP15]], i64 4)
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]], i64 1)
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i16> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4, i64 1)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
+ <vscale x 1 x float>,
+ <vscale x 1 x float>*,
+ <vscale x 1 x i16>,
+ i64);
+
+define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i64 %2) sanitize_address {
+; CHECK-LABEL: @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP4:%.*]] = zext <vscale x 1 x i16> [[TMP1:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP2:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP8]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16.i64(<vscale x 1 x float> undef, ptr [[TMP0]], <vscale x 1 x i16> [[TMP1]], i64 [[TMP2]])
+; CHECK-NEXT: ret <vscale x 1 x float> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
+ <vscale x 1 x float> undef,
+ <vscale x 1 x float>* %0,
+ <vscale x 1 x i16> %1,
+ i64 %2)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i64 %2) sanitize_address {
+; CHECK-LABEL: @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP4:%.*]] = zext <vscale x 1 x i16> [[TMP1:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP2:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP8]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, ptr [[TMP0]], <vscale x 1 x i16> [[TMP1]], i64 [[TMP2]])
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> undef,
+ <vscale x 1 x i32>* %0,
+ <vscale x 1 x i16> %1,
+ i64 %2)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i1>,
+ i64,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {
+; CHECK-LABEL: @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP6:%.*]] = zext <vscale x 1 x i16> [[TMP2:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[TMP4:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP10]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP15]], i64 4)
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]], i64 1)
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i16> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4, i64 1)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare void @llvm.riscv.vsoxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ i64);
+
+define void @intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, i64 %3) sanitize_address {
+; CHECK-LABEL: @intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP5:%.*]] = zext <vscale x 1 x i16> [[TMP2:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP3:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP16:%.*]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP9]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]
+; CHECK: 12:
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x ptr> [[TMP6]], i64 [[IV]]
+; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP14]], i64 4)
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: call void @llvm.riscv.vsoxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], i64 [[TMP3]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vsoxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i16> %2,
+ i64 %3)
+
+ ret void
+}
+
+declare void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i1>,
+ i64);
+
+define void @intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {
+; CHECK-LABEL: @intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP6:%.*]] = zext <vscale x 1 x i16> [[TMP2:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[TMP4:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP10]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP15]], i64 4)
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i16> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret void
+}
+
+declare void @llvm.riscv.vsuxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ i64);
+
+define void @intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, i64 %3) sanitize_address {
+; CHECK-LABEL: @intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP5:%.*]] = zext <vscale x 1 x i16> [[TMP2:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP3:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP16:%.*]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP9]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]
+; CHECK: 12:
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x ptr> [[TMP6]], i64 [[IV]]
+; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP14]], i64 4)
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: call void @llvm.riscv.vsuxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], i64 [[TMP3]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vsuxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i16> %2,
+ i64 %3)
+
+ ret void
+}
+
+declare void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i1>,
+ i64);
+
+define void @intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {
+; CHECK-LABEL: @intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP6:%.*]] = zext <vscale x 1 x i16> [[TMP2:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[TMP4:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP10]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP15]], i64 4)
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i16> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret void
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg2_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg2_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP13:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x ptr> [[TMP3]], i64 [[IV]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP11]], i64 4)
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP24:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP17]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP16]] ], [ [[IV2_NEXT:%.*]], [[TMP23:%.*]] ]
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP23]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x ptr> [[TMP14]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP22]], i64 4)
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP18]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: [[TMP25:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg2.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP26:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP25]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP26]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg2_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP13:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x ptr> [[TMP3]], i64 [[IV]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP11]], i64 4)
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP24:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP17]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP16]] ], [ [[IV2_NEXT:%.*]], [[TMP23:%.*]] ]
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP23]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x ptr> [[TMP14]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP22]], i64 4)
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP18]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: [[TMP25:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg2.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP26:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP25]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP26]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg3_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg3_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP14:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP7]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x ptr> [[TMP4]], i64 [[IV]]
+; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP12]], i64 4)
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP16]], label [[TMP17:%.*]], label [[TMP25:%.*]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP18]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP17]] ], [ [[IV2_NEXT:%.*]], [[TMP24:%.*]] ]
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP24]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x ptr> [[TMP15]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[TMP22]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP23]], i64 4)
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP19]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP36:%.*]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP29]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP28]] ], [ [[IV4_NEXT:%.*]], [[TMP35:%.*]] ]
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP35]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x ptr> [[TMP26]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP33]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP34]], i64 4)
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP30]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: [[TMP37:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg3.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP38:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP37]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP38]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg3_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP14:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP7]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x ptr> [[TMP4]], i64 [[IV]]
+; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP12]], i64 4)
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP16]], label [[TMP17:%.*]], label [[TMP25:%.*]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP18]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP17]] ], [ [[IV2_NEXT:%.*]], [[TMP24:%.*]] ]
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP24]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x ptr> [[TMP15]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[TMP22]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP23]], i64 4)
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP19]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP36:%.*]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP29]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP28]] ], [ [[IV4_NEXT:%.*]], [[TMP35:%.*]] ]
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP35]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x ptr> [[TMP26]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP33]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP34]], i64 4)
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP30]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: [[TMP37:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg3.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP38:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP37]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP38]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg4_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg4_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP8]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP26:%.*]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP19]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP18]] ], [ [[IV2_NEXT:%.*]], [[TMP25:%.*]] ]
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP25]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x ptr> [[TMP16]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[TMP23]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP24]], i64 4)
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP20]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP28:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP37:%.*]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP30]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP29]] ], [ [[IV4_NEXT:%.*]], [[TMP36:%.*]] ]
+; CHECK-NEXT: [[TMP32:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP36]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x ptr> [[TMP27]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr [[TMP34]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP35]], i64 4)
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP31]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP39:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP39]], label [[TMP40:%.*]], label [[TMP48:%.*]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP41]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP40]] ], [ [[IV6_NEXT:%.*]], [[TMP47:%.*]] ]
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP47]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x ptr> [[TMP38]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP46:%.*]] = ptrtoint ptr [[TMP45]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP46]], i64 4)
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP42]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg4.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP50:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP49]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP50]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg4_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP8]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP26:%.*]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP19]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP18]] ], [ [[IV2_NEXT:%.*]], [[TMP25:%.*]] ]
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP25]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x ptr> [[TMP16]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[TMP23]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP24]], i64 4)
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP20]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP28:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP37:%.*]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP30]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP29]] ], [ [[IV4_NEXT:%.*]], [[TMP36:%.*]] ]
+; CHECK-NEXT: [[TMP32:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP36]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x ptr> [[TMP27]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr [[TMP34]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP35]], i64 4)
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP31]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP39:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP39]], label [[TMP40:%.*]], label [[TMP48:%.*]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP41]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP40]] ], [ [[IV6_NEXT:%.*]], [[TMP47:%.*]] ]
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP47]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x ptr> [[TMP38]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP46:%.*]] = ptrtoint ptr [[TMP45]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP46]], i64 4)
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP42]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg4.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP50:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP49]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP50]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg5_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg5_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP16:%.*]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP9]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]
+; CHECK: 12:
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x ptr> [[TMP6]], i64 [[IV]]
+; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP14]], i64 4)
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP18]], label [[TMP19:%.*]], label [[TMP27:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP20]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP19]] ], [ [[IV2_NEXT:%.*]], [[TMP26:%.*]] ]
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP22]], label [[TMP23:%.*]], label [[TMP26]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x ptr> [[TMP17]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP24]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP25]], i64 4)
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP21]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP29:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP38:%.*]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP31]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP30]] ], [ [[IV4_NEXT:%.*]], [[TMP37:%.*]] ]
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP33]], label [[TMP34:%.*]], label [[TMP37]]
+; CHECK: 34:
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x ptr> [[TMP28]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP36:%.*]] = ptrtoint ptr [[TMP35]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP36]], i64 4)
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP32]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP40:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP40]], label [[TMP41:%.*]], label [[TMP49:%.*]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP42]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP41]] ], [ [[IV6_NEXT:%.*]], [[TMP48:%.*]] ]
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP44]], label [[TMP45:%.*]], label [[TMP48]]
+; CHECK: 45:
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x ptr> [[TMP39]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP47:%.*]] = ptrtoint ptr [[TMP46]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP47]], i64 4)
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP43]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP51]], label [[TMP52:%.*]], label [[TMP60:%.*]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP53]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP52]] ], [ [[IV8_NEXT:%.*]], [[TMP59:%.*]] ]
+; CHECK-NEXT: [[TMP55:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP55]], label [[TMP56:%.*]], label [[TMP59]]
+; CHECK: 56:
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x ptr> [[TMP50]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP58:%.*]] = ptrtoint ptr [[TMP57]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP58]], i64 4)
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP54]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[TMP61:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg5.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP62:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP61]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP62]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg5_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP16:%.*]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP9]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]
+; CHECK: 12:
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x ptr> [[TMP6]], i64 [[IV]]
+; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP14]], i64 4)
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP18]], label [[TMP19:%.*]], label [[TMP27:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP20]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP19]] ], [ [[IV2_NEXT:%.*]], [[TMP26:%.*]] ]
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP22]], label [[TMP23:%.*]], label [[TMP26]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x ptr> [[TMP17]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP24]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP25]], i64 4)
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP21]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP29:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP38:%.*]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP31]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP30]] ], [ [[IV4_NEXT:%.*]], [[TMP37:%.*]] ]
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP33]], label [[TMP34:%.*]], label [[TMP37]]
+; CHECK: 34:
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x ptr> [[TMP28]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP36:%.*]] = ptrtoint ptr [[TMP35]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP36]], i64 4)
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP32]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP40:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP40]], label [[TMP41:%.*]], label [[TMP49:%.*]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP42]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP41]] ], [ [[IV6_NEXT:%.*]], [[TMP48:%.*]] ]
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP44]], label [[TMP45:%.*]], label [[TMP48]]
+; CHECK: 45:
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x ptr> [[TMP39]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP47:%.*]] = ptrtoint ptr [[TMP46]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP47]], i64 4)
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP43]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP51]], label [[TMP52:%.*]], label [[TMP60:%.*]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP53]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP52]] ], [ [[IV8_NEXT:%.*]], [[TMP59:%.*]] ]
+; CHECK-NEXT: [[TMP55:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP55]], label [[TMP56:%.*]], label [[TMP59]]
+; CHECK: 56:
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x ptr> [[TMP50]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP58:%.*]] = ptrtoint ptr [[TMP57]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP58]], i64 4)
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP54]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[TMP61:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg5.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP62:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP61]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP62]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg6_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg6_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP10]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP15]], i64 4)
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP28:%.*]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP21]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP20]] ], [ [[IV2_NEXT:%.*]], [[TMP27:%.*]] ]
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP23]], label [[TMP24:%.*]], label [[TMP27]]
+; CHECK: 24:
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x ptr> [[TMP18]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[TMP25]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP26]], i64 4)
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP22]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP30:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP39:%.*]]
+; CHECK: 31:
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP32]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP31]] ], [ [[IV4_NEXT:%.*]], [[TMP38:%.*]] ]
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP34]], label [[TMP35:%.*]], label [[TMP38]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x ptr> [[TMP29]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP37:%.*]] = ptrtoint ptr [[TMP36]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP37]], i64 4)
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP33]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[TMP40:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP41:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP50:%.*]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP43]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP42]] ], [ [[IV6_NEXT:%.*]], [[TMP49:%.*]] ]
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP45]], label [[TMP46:%.*]], label [[TMP49]]
+; CHECK: 46:
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x ptr> [[TMP40]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr [[TMP47]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP48]], i64 4)
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP44]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP52:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP52]], label [[TMP53:%.*]], label [[TMP61:%.*]]
+; CHECK: 53:
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP54]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP53]] ], [ [[IV8_NEXT:%.*]], [[TMP60:%.*]] ]
+; CHECK-NEXT: [[TMP56:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP56]], label [[TMP57:%.*]], label [[TMP60]]
+; CHECK: 57:
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x ptr> [[TMP51]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP59:%.*]] = ptrtoint ptr [[TMP58]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP59]], i64 4)
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP55]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[TMP62:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP63:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP63]], label [[TMP64:%.*]], label [[TMP72:%.*]]
+; CHECK: 64:
+; CHECK-NEXT: [[TMP65:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP65]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP64]] ], [ [[IV10_NEXT:%.*]], [[TMP71:%.*]] ]
+; CHECK-NEXT: [[TMP67:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP67]], label [[TMP68:%.*]], label [[TMP71]]
+; CHECK: 68:
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x ptr> [[TMP62]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP70:%.*]] = ptrtoint ptr [[TMP69]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP70]], i64 4)
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP66]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[TMP73:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg6.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP74:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP73]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP74]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg6_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP10]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP15]], i64 4)
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP28:%.*]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP21]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP20]] ], [ [[IV2_NEXT:%.*]], [[TMP27:%.*]] ]
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP23]], label [[TMP24:%.*]], label [[TMP27]]
+; CHECK: 24:
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x ptr> [[TMP18]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[TMP25]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP26]], i64 4)
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP22]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP30:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP39:%.*]]
+; CHECK: 31:
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP32]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP31]] ], [ [[IV4_NEXT:%.*]], [[TMP38:%.*]] ]
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP34]], label [[TMP35:%.*]], label [[TMP38]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x ptr> [[TMP29]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP37:%.*]] = ptrtoint ptr [[TMP36]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP37]], i64 4)
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP33]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[TMP40:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP41:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP50:%.*]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP43]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP42]] ], [ [[IV6_NEXT:%.*]], [[TMP49:%.*]] ]
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP45]], label [[TMP46:%.*]], label [[TMP49]]
+; CHECK: 46:
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x ptr> [[TMP40]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr [[TMP47]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP48]], i64 4)
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP44]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP52:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP52]], label [[TMP53:%.*]], label [[TMP61:%.*]]
+; CHECK: 53:
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP54]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP53]] ], [ [[IV8_NEXT:%.*]], [[TMP60:%.*]] ]
+; CHECK-NEXT: [[TMP56:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP56]], label [[TMP57:%.*]], label [[TMP60]]
+; CHECK: 57:
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x ptr> [[TMP51]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP59:%.*]] = ptrtoint ptr [[TMP58]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP59]], i64 4)
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP55]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[TMP62:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP63:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP63]], label [[TMP64:%.*]], label [[TMP72:%.*]]
+; CHECK: 64:
+; CHECK-NEXT: [[TMP65:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP65]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP64]] ], [ [[IV10_NEXT:%.*]], [[TMP71:%.*]] ]
+; CHECK-NEXT: [[TMP67:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP67]], label [[TMP68:%.*]], label [[TMP71]]
+; CHECK: 68:
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x ptr> [[TMP62]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP70:%.*]] = ptrtoint ptr [[TMP69]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP70]], i64 4)
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP66]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[TMP73:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg6.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP74:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP73]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP74]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg7_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg7_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP18:%.*]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP11]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP10]] ], [ [[IV_NEXT:%.*]], [[TMP17:%.*]] ]
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP17]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <vscale x 1 x ptr> [[TMP8]], i64 [[IV]]
+; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP15]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP16]], i64 4)
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP12]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP29:%.*]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP22]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP21]] ], [ [[IV2_NEXT:%.*]], [[TMP28:%.*]] ]
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP24]], label [[TMP25:%.*]], label [[TMP28]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <vscale x 1 x ptr> [[TMP19]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP27:%.*]] = ptrtoint ptr [[TMP26]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP27]], i64 4)
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP23]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP31:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP40:%.*]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP33]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP32]] ], [ [[IV4_NEXT:%.*]], [[TMP39:%.*]] ]
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP35]], label [[TMP36:%.*]], label [[TMP39]]
+; CHECK: 36:
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <vscale x 1 x ptr> [[TMP30]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr [[TMP37]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP38]], i64 4)
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP34]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP42:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP42]], label [[TMP43:%.*]], label [[TMP51:%.*]]
+; CHECK: 43:
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP44]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP43]] ], [ [[IV6_NEXT:%.*]], [[TMP50:%.*]] ]
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP46]], label [[TMP47:%.*]], label [[TMP50]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = extractelement <vscale x 1 x ptr> [[TMP41]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP49:%.*]] = ptrtoint ptr [[TMP48]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP49]], i64 4)
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP45]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[TMP52:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP53:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP62:%.*]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP55]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP54]] ], [ [[IV8_NEXT:%.*]], [[TMP61:%.*]] ]
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP57]], label [[TMP58:%.*]], label [[TMP61]]
+; CHECK: 58:
+; CHECK-NEXT: [[TMP59:%.*]] = extractelement <vscale x 1 x ptr> [[TMP52]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr [[TMP59]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP60]], i64 4)
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP56]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP64:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP64]], label [[TMP65:%.*]], label [[TMP73:%.*]]
+; CHECK: 65:
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP66]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP65]] ], [ [[IV10_NEXT:%.*]], [[TMP72:%.*]] ]
+; CHECK-NEXT: [[TMP68:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP68]], label [[TMP69:%.*]], label [[TMP72]]
+; CHECK: 69:
+; CHECK-NEXT: [[TMP70:%.*]] = extractelement <vscale x 1 x ptr> [[TMP63]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP71:%.*]] = ptrtoint ptr [[TMP70]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP71]], i64 4)
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP67]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[TMP74:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP75:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP75]], label [[TMP76:%.*]], label [[TMP84:%.*]]
+; CHECK: 76:
+; CHECK-NEXT: [[TMP77:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP77]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP76]] ], [ [[IV12_NEXT:%.*]], [[TMP83:%.*]] ]
+; CHECK-NEXT: [[TMP79:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP79]], label [[TMP80:%.*]], label [[TMP83]]
+; CHECK: 80:
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <vscale x 1 x ptr> [[TMP74]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP82:%.*]] = ptrtoint ptr [[TMP81]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP82]], i64 4)
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP78]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[TMP85:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg7.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP86:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP85]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP86]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg7_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP18:%.*]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP11]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP10]] ], [ [[IV_NEXT:%.*]], [[TMP17:%.*]] ]
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP17]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <vscale x 1 x ptr> [[TMP8]], i64 [[IV]]
+; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP15]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP16]], i64 4)
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP12]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP29:%.*]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP22]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP21]] ], [ [[IV2_NEXT:%.*]], [[TMP28:%.*]] ]
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP24]], label [[TMP25:%.*]], label [[TMP28]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <vscale x 1 x ptr> [[TMP19]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP27:%.*]] = ptrtoint ptr [[TMP26]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP27]], i64 4)
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP23]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP31:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP40:%.*]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP33]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP32]] ], [ [[IV4_NEXT:%.*]], [[TMP39:%.*]] ]
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP35]], label [[TMP36:%.*]], label [[TMP39]]
+; CHECK: 36:
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <vscale x 1 x ptr> [[TMP30]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr [[TMP37]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP38]], i64 4)
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP34]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP42:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP42]], label [[TMP43:%.*]], label [[TMP51:%.*]]
+; CHECK: 43:
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP44]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP43]] ], [ [[IV6_NEXT:%.*]], [[TMP50:%.*]] ]
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP46]], label [[TMP47:%.*]], label [[TMP50]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = extractelement <vscale x 1 x ptr> [[TMP41]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP49:%.*]] = ptrtoint ptr [[TMP48]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP49]], i64 4)
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP45]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[TMP52:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP53:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP62:%.*]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP55]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP54]] ], [ [[IV8_NEXT:%.*]], [[TMP61:%.*]] ]
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP57]], label [[TMP58:%.*]], label [[TMP61]]
+; CHECK: 58:
+; CHECK-NEXT: [[TMP59:%.*]] = extractelement <vscale x 1 x ptr> [[TMP52]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr [[TMP59]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP60]], i64 4)
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP56]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP64:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP64]], label [[TMP65:%.*]], label [[TMP73:%.*]]
+; CHECK: 65:
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP66]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP65]] ], [ [[IV10_NEXT:%.*]], [[TMP72:%.*]] ]
+; CHECK-NEXT: [[TMP68:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP68]], label [[TMP69:%.*]], label [[TMP72]]
+; CHECK: 69:
+; CHECK-NEXT: [[TMP70:%.*]] = extractelement <vscale x 1 x ptr> [[TMP63]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP71:%.*]] = ptrtoint ptr [[TMP70]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP71]], i64 4)
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP67]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[TMP74:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP75:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP75]], label [[TMP76:%.*]], label [[TMP84:%.*]]
+; CHECK: 76:
+; CHECK-NEXT: [[TMP77:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP77]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP76]] ], [ [[IV12_NEXT:%.*]], [[TMP83:%.*]] ]
+; CHECK-NEXT: [[TMP79:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP79]], label [[TMP80:%.*]], label [[TMP83]]
+; CHECK: 80:
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <vscale x 1 x ptr> [[TMP74]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP82:%.*]] = ptrtoint ptr [[TMP81]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP82]], i64 4)
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP78]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[TMP85:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg7.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP86:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP85]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP86]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg8_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg8_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 28, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP19:%.*]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP12]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP11]] ], [ [[IV_NEXT:%.*]], [[TMP18:%.*]] ]
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP14]], label [[TMP15:%.*]], label [[TMP18]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <vscale x 1 x ptr> [[TMP9]], i64 [[IV]]
+; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[TMP16]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP17]], i64 4)
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP13]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP19]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP30:%.*]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP24:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP23]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP22]] ], [ [[IV2_NEXT:%.*]], [[TMP29:%.*]] ]
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP29]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <vscale x 1 x ptr> [[TMP20]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[TMP27]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP28]], i64 4)
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP24]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP30]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP32:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP41:%.*]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP35:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP34]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP33]] ], [ [[IV4_NEXT:%.*]], [[TMP40:%.*]] ]
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP36]], label [[TMP37:%.*]], label [[TMP40]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = extractelement <vscale x 1 x ptr> [[TMP31]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP39:%.*]] = ptrtoint ptr [[TMP38]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP39]], i64 4)
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP35]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP41]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP52:%.*]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP46:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP45]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP44]] ], [ [[IV6_NEXT:%.*]], [[TMP51:%.*]] ]
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP47]], label [[TMP48:%.*]], label [[TMP51]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = extractelement <vscale x 1 x ptr> [[TMP42]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP50:%.*]] = ptrtoint ptr [[TMP49]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP50]], i64 4)
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP46]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP52]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP54:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP54]], label [[TMP55:%.*]], label [[TMP63:%.*]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP57:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP56]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP55]] ], [ [[IV8_NEXT:%.*]], [[TMP62:%.*]] ]
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP58]], label [[TMP59:%.*]], label [[TMP62]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = extractelement <vscale x 1 x ptr> [[TMP53]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP61:%.*]] = ptrtoint ptr [[TMP60]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP61]], i64 4)
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP57]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP63]]
+; CHECK: 63:
+; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP65:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP74:%.*]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP68:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP67]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP66]] ], [ [[IV10_NEXT:%.*]], [[TMP73:%.*]] ]
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP69]], label [[TMP70:%.*]], label [[TMP73]]
+; CHECK: 70:
+; CHECK-NEXT: [[TMP71:%.*]] = extractelement <vscale x 1 x ptr> [[TMP64]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP72:%.*]] = ptrtoint ptr [[TMP71]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP72]], i64 4)
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP68]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP76:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP76]], label [[TMP77:%.*]], label [[TMP85:%.*]]
+; CHECK: 77:
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP79:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP78]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP77]] ], [ [[IV12_NEXT:%.*]], [[TMP84:%.*]] ]
+; CHECK-NEXT: [[TMP80:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP80]], label [[TMP81:%.*]], label [[TMP84]]
+; CHECK: 81:
+; CHECK-NEXT: [[TMP82:%.*]] = extractelement <vscale x 1 x ptr> [[TMP75]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP83:%.*]] = ptrtoint ptr [[TMP82]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP83]], i64 4)
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP79]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP85]]
+; CHECK: 85:
+; CHECK-NEXT: [[TMP86:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP8]]
+; CHECK-NEXT: [[TMP87:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP87]], label [[TMP88:%.*]], label [[TMP96:%.*]]
+; CHECK: 88:
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP90:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP89]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP88]] ], [ [[IV14_NEXT:%.*]], [[TMP95:%.*]] ]
+; CHECK-NEXT: [[TMP91:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP91]], label [[TMP92:%.*]], label [[TMP95]]
+; CHECK: 92:
+; CHECK-NEXT: [[TMP93:%.*]] = extractelement <vscale x 1 x ptr> [[TMP86]], i64 [[IV14]]
+; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr [[TMP93]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP94]], i64 4)
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP90]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP96]]
+; CHECK: 96:
+; CHECK-NEXT: [[TMP97:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg8.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP98:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP97]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP98]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg8_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 28, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP19:%.*]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP12]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP11]] ], [ [[IV_NEXT:%.*]], [[TMP18:%.*]] ]
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP14]], label [[TMP15:%.*]], label [[TMP18]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <vscale x 1 x ptr> [[TMP9]], i64 [[IV]]
+; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[TMP16]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP17]], i64 4)
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP13]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP19]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP30:%.*]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP24:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP23]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP22]] ], [ [[IV2_NEXT:%.*]], [[TMP29:%.*]] ]
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP29]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <vscale x 1 x ptr> [[TMP20]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[TMP27]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP28]], i64 4)
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP24]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP30]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP32:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP41:%.*]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP35:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP34]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP33]] ], [ [[IV4_NEXT:%.*]], [[TMP40:%.*]] ]
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP36]], label [[TMP37:%.*]], label [[TMP40]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = extractelement <vscale x 1 x ptr> [[TMP31]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP39:%.*]] = ptrtoint ptr [[TMP38]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP39]], i64 4)
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP35]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP41]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP52:%.*]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP46:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP45]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP44]] ], [ [[IV6_NEXT:%.*]], [[TMP51:%.*]] ]
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP47]], label [[TMP48:%.*]], label [[TMP51]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = extractelement <vscale x 1 x ptr> [[TMP42]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP50:%.*]] = ptrtoint ptr [[TMP49]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP50]], i64 4)
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP46]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP52]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP54:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP54]], label [[TMP55:%.*]], label [[TMP63:%.*]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP57:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP56]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP55]] ], [ [[IV8_NEXT:%.*]], [[TMP62:%.*]] ]
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP58]], label [[TMP59:%.*]], label [[TMP62]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = extractelement <vscale x 1 x ptr> [[TMP53]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP61:%.*]] = ptrtoint ptr [[TMP60]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP61]], i64 4)
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP57]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP63]]
+; CHECK: 63:
+; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP65:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP74:%.*]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP68:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP67]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP66]] ], [ [[IV10_NEXT:%.*]], [[TMP73:%.*]] ]
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP69]], label [[TMP70:%.*]], label [[TMP73]]
+; CHECK: 70:
+; CHECK-NEXT: [[TMP71:%.*]] = extractelement <vscale x 1 x ptr> [[TMP64]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP72:%.*]] = ptrtoint ptr [[TMP71]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP72]], i64 4)
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP68]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP76:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP76]], label [[TMP77:%.*]], label [[TMP85:%.*]]
+; CHECK: 77:
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP79:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP78]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP77]] ], [ [[IV12_NEXT:%.*]], [[TMP84:%.*]] ]
+; CHECK-NEXT: [[TMP80:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP80]], label [[TMP81:%.*]], label [[TMP84]]
+; CHECK: 81:
+; CHECK-NEXT: [[TMP82:%.*]] = extractelement <vscale x 1 x ptr> [[TMP75]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP83:%.*]] = ptrtoint ptr [[TMP82]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP83]], i64 4)
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP79]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP85]]
+; CHECK: 85:
+; CHECK-NEXT: [[TMP86:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP8]]
+; CHECK-NEXT: [[TMP87:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP87]], label [[TMP88:%.*]], label [[TMP96:%.*]]
+; CHECK: 88:
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP90:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP89]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP88]] ], [ [[IV14_NEXT:%.*]], [[TMP95:%.*]] ]
+; CHECK-NEXT: [[TMP91:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP91]], label [[TMP92:%.*]], label [[TMP95]]
+; CHECK: 92:
+; CHECK-NEXT: [[TMP93:%.*]] = extractelement <vscale x 1 x ptr> [[TMP86]], i64 [[IV14]]
+; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr [[TMP93]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP94]], i64 4)
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP90]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP96]]
+; CHECK: 96:
+; CHECK-NEXT: [[TMP97:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg8.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP98:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP97]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP98]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg2_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg2_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP13:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x ptr> [[TMP3]], i64 [[IV]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP11]], i64 4)
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP24:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP17]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP16]] ], [ [[IV2_NEXT:%.*]], [[TMP23:%.*]] ]
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP23]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x ptr> [[TMP14]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP22]], i64 4)
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP18]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: [[TMP25:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg2.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP26:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP25]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP26]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg2_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP13:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x ptr> [[TMP3]], i64 [[IV]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP11]], i64 4)
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP24:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP17]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP16]] ], [ [[IV2_NEXT:%.*]], [[TMP23:%.*]] ]
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP23]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x ptr> [[TMP14]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP22]], i64 4)
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP18]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: [[TMP25:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP26:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP25]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP26]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg3_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg3_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP14:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP7]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x ptr> [[TMP4]], i64 [[IV]]
+; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP12]], i64 4)
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP16]], label [[TMP17:%.*]], label [[TMP25:%.*]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP18]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP17]] ], [ [[IV2_NEXT:%.*]], [[TMP24:%.*]] ]
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP24]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x ptr> [[TMP15]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[TMP22]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP23]], i64 4)
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP19]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP36:%.*]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP29]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP28]] ], [ [[IV4_NEXT:%.*]], [[TMP35:%.*]] ]
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP35]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x ptr> [[TMP26]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP33]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP34]], i64 4)
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP30]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: [[TMP37:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg3.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP38:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP37]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP38]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg3_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP14:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP7]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x ptr> [[TMP4]], i64 [[IV]]
+; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP12]], i64 4)
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP16]], label [[TMP17:%.*]], label [[TMP25:%.*]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP18]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP17]] ], [ [[IV2_NEXT:%.*]], [[TMP24:%.*]] ]
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP24]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x ptr> [[TMP15]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[TMP22]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP23]], i64 4)
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP19]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP36:%.*]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP29]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP28]] ], [ [[IV4_NEXT:%.*]], [[TMP35:%.*]] ]
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP35]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x ptr> [[TMP26]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP33]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP34]], i64 4)
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP30]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: [[TMP37:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg3.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP38:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP37]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP38]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg4_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg4_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP8]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP26:%.*]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP19]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP18]] ], [ [[IV2_NEXT:%.*]], [[TMP25:%.*]] ]
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP25]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x ptr> [[TMP16]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[TMP23]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP24]], i64 4)
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP20]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP28:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP37:%.*]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP30]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP29]] ], [ [[IV4_NEXT:%.*]], [[TMP36:%.*]] ]
+; CHECK-NEXT: [[TMP32:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP36]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x ptr> [[TMP27]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr [[TMP34]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP35]], i64 4)
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP31]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP39:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP39]], label [[TMP40:%.*]], label [[TMP48:%.*]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP41]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP40]] ], [ [[IV6_NEXT:%.*]], [[TMP47:%.*]] ]
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP47]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x ptr> [[TMP38]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP46:%.*]] = ptrtoint ptr [[TMP45]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP46]], i64 4)
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP42]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg4.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP50:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP49]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP50]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg4_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP8]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP26:%.*]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP19]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP18]] ], [ [[IV2_NEXT:%.*]], [[TMP25:%.*]] ]
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP25]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x ptr> [[TMP16]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[TMP23]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP24]], i64 4)
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP20]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP28:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP37:%.*]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP30]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP29]] ], [ [[IV4_NEXT:%.*]], [[TMP36:%.*]] ]
+; CHECK-NEXT: [[TMP32:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP36]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x ptr> [[TMP27]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr [[TMP34]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP35]], i64 4)
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP31]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP39:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP39]], label [[TMP40:%.*]], label [[TMP48:%.*]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP41]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP40]] ], [ [[IV6_NEXT:%.*]], [[TMP47:%.*]] ]
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP47]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x ptr> [[TMP38]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP46:%.*]] = ptrtoint ptr [[TMP45]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP46]], i64 4)
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP42]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg4.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP50:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP49]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP50]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg5_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg5_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP16:%.*]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP9]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]
+; CHECK: 12:
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x ptr> [[TMP6]], i64 [[IV]]
+; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP14]], i64 4)
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP18]], label [[TMP19:%.*]], label [[TMP27:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP20]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP19]] ], [ [[IV2_NEXT:%.*]], [[TMP26:%.*]] ]
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP22]], label [[TMP23:%.*]], label [[TMP26]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x ptr> [[TMP17]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP24]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP25]], i64 4)
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP21]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP29:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP38:%.*]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP31]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP30]] ], [ [[IV4_NEXT:%.*]], [[TMP37:%.*]] ]
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP33]], label [[TMP34:%.*]], label [[TMP37]]
+; CHECK: 34:
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x ptr> [[TMP28]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP36:%.*]] = ptrtoint ptr [[TMP35]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP36]], i64 4)
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP32]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP40:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP40]], label [[TMP41:%.*]], label [[TMP49:%.*]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP42]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP41]] ], [ [[IV6_NEXT:%.*]], [[TMP48:%.*]] ]
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP44]], label [[TMP45:%.*]], label [[TMP48]]
+; CHECK: 45:
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x ptr> [[TMP39]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP47:%.*]] = ptrtoint ptr [[TMP46]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP47]], i64 4)
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP43]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP51]], label [[TMP52:%.*]], label [[TMP60:%.*]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP53]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP52]] ], [ [[IV8_NEXT:%.*]], [[TMP59:%.*]] ]
+; CHECK-NEXT: [[TMP55:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP55]], label [[TMP56:%.*]], label [[TMP59]]
+; CHECK: 56:
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x ptr> [[TMP50]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP58:%.*]] = ptrtoint ptr [[TMP57]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP58]], i64 4)
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP54]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[TMP61:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg5.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP62:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP61]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP62]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg5_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP16:%.*]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP9]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]
+; CHECK: 12:
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x ptr> [[TMP6]], i64 [[IV]]
+; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP14]], i64 4)
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP18]], label [[TMP19:%.*]], label [[TMP27:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP20]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP19]] ], [ [[IV2_NEXT:%.*]], [[TMP26:%.*]] ]
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP22]], label [[TMP23:%.*]], label [[TMP26]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x ptr> [[TMP17]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP24]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP25]], i64 4)
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP21]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP29:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP38:%.*]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP31]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP30]] ], [ [[IV4_NEXT:%.*]], [[TMP37:%.*]] ]
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP33]], label [[TMP34:%.*]], label [[TMP37]]
+; CHECK: 34:
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x ptr> [[TMP28]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP36:%.*]] = ptrtoint ptr [[TMP35]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP36]], i64 4)
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP32]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP40:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP40]], label [[TMP41:%.*]], label [[TMP49:%.*]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP42]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP41]] ], [ [[IV6_NEXT:%.*]], [[TMP48:%.*]] ]
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP44]], label [[TMP45:%.*]], label [[TMP48]]
+; CHECK: 45:
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x ptr> [[TMP39]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP47:%.*]] = ptrtoint ptr [[TMP46]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP47]], i64 4)
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP43]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP51]], label [[TMP52:%.*]], label [[TMP60:%.*]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP53]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP52]] ], [ [[IV8_NEXT:%.*]], [[TMP59:%.*]] ]
+; CHECK-NEXT: [[TMP55:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP55]], label [[TMP56:%.*]], label [[TMP59]]
+; CHECK: 56:
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x ptr> [[TMP50]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP58:%.*]] = ptrtoint ptr [[TMP57]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP58]], i64 4)
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP54]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[TMP61:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg5.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP62:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP61]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP62]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg6_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg6_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP10]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP15]], i64 4)
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP28:%.*]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP21]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP20]] ], [ [[IV2_NEXT:%.*]], [[TMP27:%.*]] ]
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP23]], label [[TMP24:%.*]], label [[TMP27]]
+; CHECK: 24:
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x ptr> [[TMP18]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[TMP25]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP26]], i64 4)
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP22]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP30:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP39:%.*]]
+; CHECK: 31:
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP32]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP31]] ], [ [[IV4_NEXT:%.*]], [[TMP38:%.*]] ]
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP34]], label [[TMP35:%.*]], label [[TMP38]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x ptr> [[TMP29]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP37:%.*]] = ptrtoint ptr [[TMP36]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP37]], i64 4)
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP33]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[TMP40:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP41:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP50:%.*]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP43]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP42]] ], [ [[IV6_NEXT:%.*]], [[TMP49:%.*]] ]
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP45]], label [[TMP46:%.*]], label [[TMP49]]
+; CHECK: 46:
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x ptr> [[TMP40]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr [[TMP47]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP48]], i64 4)
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP44]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP52:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP52]], label [[TMP53:%.*]], label [[TMP61:%.*]]
+; CHECK: 53:
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP54]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP53]] ], [ [[IV8_NEXT:%.*]], [[TMP60:%.*]] ]
+; CHECK-NEXT: [[TMP56:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP56]], label [[TMP57:%.*]], label [[TMP60]]
+; CHECK: 57:
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x ptr> [[TMP51]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP59:%.*]] = ptrtoint ptr [[TMP58]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP59]], i64 4)
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP55]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[TMP62:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP63:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP63]], label [[TMP64:%.*]], label [[TMP72:%.*]]
+; CHECK: 64:
+; CHECK-NEXT: [[TMP65:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP65]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP64]] ], [ [[IV10_NEXT:%.*]], [[TMP71:%.*]] ]
+; CHECK-NEXT: [[TMP67:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP67]], label [[TMP68:%.*]], label [[TMP71]]
+; CHECK: 68:
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x ptr> [[TMP62]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP70:%.*]] = ptrtoint ptr [[TMP69]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP70]], i64 4)
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP66]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[TMP73:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg6.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP74:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP73]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP74]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg6_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP10]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP15]], i64 4)
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP28:%.*]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP21]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP20]] ], [ [[IV2_NEXT:%.*]], [[TMP27:%.*]] ]
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP23]], label [[TMP24:%.*]], label [[TMP27]]
+; CHECK: 24:
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x ptr> [[TMP18]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[TMP25]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP26]], i64 4)
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP22]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP30:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP39:%.*]]
+; CHECK: 31:
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP32]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP31]] ], [ [[IV4_NEXT:%.*]], [[TMP38:%.*]] ]
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP34]], label [[TMP35:%.*]], label [[TMP38]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x ptr> [[TMP29]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP37:%.*]] = ptrtoint ptr [[TMP36]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP37]], i64 4)
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP33]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[TMP40:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP41:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP50:%.*]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP43]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP42]] ], [ [[IV6_NEXT:%.*]], [[TMP49:%.*]] ]
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP45]], label [[TMP46:%.*]], label [[TMP49]]
+; CHECK: 46:
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x ptr> [[TMP40]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr [[TMP47]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP48]], i64 4)
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP44]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP52:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP52]], label [[TMP53:%.*]], label [[TMP61:%.*]]
+; CHECK: 53:
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP54]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP53]] ], [ [[IV8_NEXT:%.*]], [[TMP60:%.*]] ]
+; CHECK-NEXT: [[TMP56:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP56]], label [[TMP57:%.*]], label [[TMP60]]
+; CHECK: 57:
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x ptr> [[TMP51]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP59:%.*]] = ptrtoint ptr [[TMP58]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP59]], i64 4)
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP55]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[TMP62:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP63:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP63]], label [[TMP64:%.*]], label [[TMP72:%.*]]
+; CHECK: 64:
+; CHECK-NEXT: [[TMP65:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP65]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP64]] ], [ [[IV10_NEXT:%.*]], [[TMP71:%.*]] ]
+; CHECK-NEXT: [[TMP67:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP67]], label [[TMP68:%.*]], label [[TMP71]]
+; CHECK: 68:
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x ptr> [[TMP62]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP70:%.*]] = ptrtoint ptr [[TMP69]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP70]], i64 4)
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP66]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[TMP73:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg6.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP74:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP73]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP74]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg7_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg7_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP18:%.*]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP11]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP10]] ], [ [[IV_NEXT:%.*]], [[TMP17:%.*]] ]
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP17]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <vscale x 1 x ptr> [[TMP8]], i64 [[IV]]
+; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP15]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP16]], i64 4)
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP12]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP29:%.*]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP22]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP21]] ], [ [[IV2_NEXT:%.*]], [[TMP28:%.*]] ]
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP24]], label [[TMP25:%.*]], label [[TMP28]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <vscale x 1 x ptr> [[TMP19]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP27:%.*]] = ptrtoint ptr [[TMP26]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP27]], i64 4)
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP23]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP31:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP40:%.*]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP33]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP32]] ], [ [[IV4_NEXT:%.*]], [[TMP39:%.*]] ]
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP35]], label [[TMP36:%.*]], label [[TMP39]]
+; CHECK: 36:
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <vscale x 1 x ptr> [[TMP30]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr [[TMP37]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP38]], i64 4)
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP34]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP42:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP42]], label [[TMP43:%.*]], label [[TMP51:%.*]]
+; CHECK: 43:
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP44]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP43]] ], [ [[IV6_NEXT:%.*]], [[TMP50:%.*]] ]
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP46]], label [[TMP47:%.*]], label [[TMP50]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = extractelement <vscale x 1 x ptr> [[TMP41]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP49:%.*]] = ptrtoint ptr [[TMP48]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP49]], i64 4)
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP45]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[TMP52:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP53:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP62:%.*]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP55]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP54]] ], [ [[IV8_NEXT:%.*]], [[TMP61:%.*]] ]
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP57]], label [[TMP58:%.*]], label [[TMP61]]
+; CHECK: 58:
+; CHECK-NEXT: [[TMP59:%.*]] = extractelement <vscale x 1 x ptr> [[TMP52]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr [[TMP59]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP60]], i64 4)
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP56]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP64:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP64]], label [[TMP65:%.*]], label [[TMP73:%.*]]
+; CHECK: 65:
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP66]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP65]] ], [ [[IV10_NEXT:%.*]], [[TMP72:%.*]] ]
+; CHECK-NEXT: [[TMP68:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP68]], label [[TMP69:%.*]], label [[TMP72]]
+; CHECK: 69:
+; CHECK-NEXT: [[TMP70:%.*]] = extractelement <vscale x 1 x ptr> [[TMP63]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP71:%.*]] = ptrtoint ptr [[TMP70]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP71]], i64 4)
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP67]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[TMP74:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP75:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP75]], label [[TMP76:%.*]], label [[TMP84:%.*]]
+; CHECK: 76:
+; CHECK-NEXT: [[TMP77:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP77]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP76]] ], [ [[IV12_NEXT:%.*]], [[TMP83:%.*]] ]
+; CHECK-NEXT: [[TMP79:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP79]], label [[TMP80:%.*]], label [[TMP83]]
+; CHECK: 80:
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <vscale x 1 x ptr> [[TMP74]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP82:%.*]] = ptrtoint ptr [[TMP81]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP82]], i64 4)
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP78]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[TMP85:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg7.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP86:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP85]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP86]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg7_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP18:%.*]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP11]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP10]] ], [ [[IV_NEXT:%.*]], [[TMP17:%.*]] ]
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP17]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <vscale x 1 x ptr> [[TMP8]], i64 [[IV]]
+; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP15]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP16]], i64 4)
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP12]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP29:%.*]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP22]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP21]] ], [ [[IV2_NEXT:%.*]], [[TMP28:%.*]] ]
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP24]], label [[TMP25:%.*]], label [[TMP28]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <vscale x 1 x ptr> [[TMP19]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP27:%.*]] = ptrtoint ptr [[TMP26]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP27]], i64 4)
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP23]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP31:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP40:%.*]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP33]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP32]] ], [ [[IV4_NEXT:%.*]], [[TMP39:%.*]] ]
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP35]], label [[TMP36:%.*]], label [[TMP39]]
+; CHECK: 36:
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <vscale x 1 x ptr> [[TMP30]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr [[TMP37]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP38]], i64 4)
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP34]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP42:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP42]], label [[TMP43:%.*]], label [[TMP51:%.*]]
+; CHECK: 43:
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP44]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP43]] ], [ [[IV6_NEXT:%.*]], [[TMP50:%.*]] ]
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP46]], label [[TMP47:%.*]], label [[TMP50]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = extractelement <vscale x 1 x ptr> [[TMP41]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP49:%.*]] = ptrtoint ptr [[TMP48]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP49]], i64 4)
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP45]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[TMP52:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP53:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP62:%.*]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP55]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP54]] ], [ [[IV8_NEXT:%.*]], [[TMP61:%.*]] ]
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP57]], label [[TMP58:%.*]], label [[TMP61]]
+; CHECK: 58:
+; CHECK-NEXT: [[TMP59:%.*]] = extractelement <vscale x 1 x ptr> [[TMP52]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr [[TMP59]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP60]], i64 4)
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP56]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP64:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP64]], label [[TMP65:%.*]], label [[TMP73:%.*]]
+; CHECK: 65:
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP66]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP65]] ], [ [[IV10_NEXT:%.*]], [[TMP72:%.*]] ]
+; CHECK-NEXT: [[TMP68:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP68]], label [[TMP69:%.*]], label [[TMP72]]
+; CHECK: 69:
+; CHECK-NEXT: [[TMP70:%.*]] = extractelement <vscale x 1 x ptr> [[TMP63]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP71:%.*]] = ptrtoint ptr [[TMP70]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP71]], i64 4)
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP67]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[TMP74:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP75:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP75]], label [[TMP76:%.*]], label [[TMP84:%.*]]
+; CHECK: 76:
+; CHECK-NEXT: [[TMP77:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP77]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP76]] ], [ [[IV12_NEXT:%.*]], [[TMP83:%.*]] ]
+; CHECK-NEXT: [[TMP79:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP79]], label [[TMP80:%.*]], label [[TMP83]]
+; CHECK: 80:
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <vscale x 1 x ptr> [[TMP74]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP82:%.*]] = ptrtoint ptr [[TMP81]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP82]], i64 4)
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP78]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[TMP85:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg7.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP86:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP85]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP86]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg8_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg8_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 28, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP19:%.*]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP12]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP11]] ], [ [[IV_NEXT:%.*]], [[TMP18:%.*]] ]
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP14]], label [[TMP15:%.*]], label [[TMP18]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <vscale x 1 x ptr> [[TMP9]], i64 [[IV]]
+; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[TMP16]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP17]], i64 4)
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP13]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP19]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP30:%.*]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP24:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP23]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP22]] ], [ [[IV2_NEXT:%.*]], [[TMP29:%.*]] ]
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP29]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <vscale x 1 x ptr> [[TMP20]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[TMP27]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP28]], i64 4)
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP24]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP30]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP32:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP41:%.*]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP35:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP34]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP33]] ], [ [[IV4_NEXT:%.*]], [[TMP40:%.*]] ]
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP36]], label [[TMP37:%.*]], label [[TMP40]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = extractelement <vscale x 1 x ptr> [[TMP31]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP39:%.*]] = ptrtoint ptr [[TMP38]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP39]], i64 4)
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP35]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP41]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP52:%.*]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP46:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP45]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP44]] ], [ [[IV6_NEXT:%.*]], [[TMP51:%.*]] ]
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP47]], label [[TMP48:%.*]], label [[TMP51]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = extractelement <vscale x 1 x ptr> [[TMP42]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP50:%.*]] = ptrtoint ptr [[TMP49]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP50]], i64 4)
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP46]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP52]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP54:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP54]], label [[TMP55:%.*]], label [[TMP63:%.*]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP57:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP56]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP55]] ], [ [[IV8_NEXT:%.*]], [[TMP62:%.*]] ]
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP58]], label [[TMP59:%.*]], label [[TMP62]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = extractelement <vscale x 1 x ptr> [[TMP53]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP61:%.*]] = ptrtoint ptr [[TMP60]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP61]], i64 4)
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP57]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP63]]
+; CHECK: 63:
+; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP65:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP74:%.*]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP68:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP67]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP66]] ], [ [[IV10_NEXT:%.*]], [[TMP73:%.*]] ]
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP69]], label [[TMP70:%.*]], label [[TMP73]]
+; CHECK: 70:
+; CHECK-NEXT: [[TMP71:%.*]] = extractelement <vscale x 1 x ptr> [[TMP64]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP72:%.*]] = ptrtoint ptr [[TMP71]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP72]], i64 4)
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP68]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP76:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP76]], label [[TMP77:%.*]], label [[TMP85:%.*]]
+; CHECK: 77:
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP79:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP78]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP77]] ], [ [[IV12_NEXT:%.*]], [[TMP84:%.*]] ]
+; CHECK-NEXT: [[TMP80:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP80]], label [[TMP81:%.*]], label [[TMP84]]
+; CHECK: 81:
+; CHECK-NEXT: [[TMP82:%.*]] = extractelement <vscale x 1 x ptr> [[TMP75]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP83:%.*]] = ptrtoint ptr [[TMP82]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP83]], i64 4)
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP79]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP85]]
+; CHECK: 85:
+; CHECK-NEXT: [[TMP86:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP8]]
+; CHECK-NEXT: [[TMP87:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP87]], label [[TMP88:%.*]], label [[TMP96:%.*]]
+; CHECK: 88:
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP90:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP89]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP88]] ], [ [[IV14_NEXT:%.*]], [[TMP95:%.*]] ]
+; CHECK-NEXT: [[TMP91:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP91]], label [[TMP92:%.*]], label [[TMP95]]
+; CHECK: 92:
+; CHECK-NEXT: [[TMP93:%.*]] = extractelement <vscale x 1 x ptr> [[TMP86]], i64 [[IV14]]
+; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr [[TMP93]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP94]], i64 4)
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP90]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP96]]
+; CHECK: 96:
+; CHECK-NEXT: [[TMP97:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg8.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: [[TMP98:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP97]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP98]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg8_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 28, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP19:%.*]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP12]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP11]] ], [ [[IV_NEXT:%.*]], [[TMP18:%.*]] ]
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP14]], label [[TMP15:%.*]], label [[TMP18]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <vscale x 1 x ptr> [[TMP9]], i64 [[IV]]
+; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[TMP16]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP17]], i64 4)
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP13]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP19]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP30:%.*]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP24:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP23]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP22]] ], [ [[IV2_NEXT:%.*]], [[TMP29:%.*]] ]
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP29]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <vscale x 1 x ptr> [[TMP20]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[TMP27]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP28]], i64 4)
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP24]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP30]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP32:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP41:%.*]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP35:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP34]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP33]] ], [ [[IV4_NEXT:%.*]], [[TMP40:%.*]] ]
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP36]], label [[TMP37:%.*]], label [[TMP40]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = extractelement <vscale x 1 x ptr> [[TMP31]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP39:%.*]] = ptrtoint ptr [[TMP38]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP39]], i64 4)
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP35]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP41]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP52:%.*]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP46:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP45]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP44]] ], [ [[IV6_NEXT:%.*]], [[TMP51:%.*]] ]
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP47]], label [[TMP48:%.*]], label [[TMP51]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = extractelement <vscale x 1 x ptr> [[TMP42]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP50:%.*]] = ptrtoint ptr [[TMP49]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP50]], i64 4)
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP46]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP52]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP54:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP54]], label [[TMP55:%.*]], label [[TMP63:%.*]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP57:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP56]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP55]] ], [ [[IV8_NEXT:%.*]], [[TMP62:%.*]] ]
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP58]], label [[TMP59:%.*]], label [[TMP62]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = extractelement <vscale x 1 x ptr> [[TMP53]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP61:%.*]] = ptrtoint ptr [[TMP60]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP61]], i64 4)
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP57]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP63]]
+; CHECK: 63:
+; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP65:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP74:%.*]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP68:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP67]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP66]] ], [ [[IV10_NEXT:%.*]], [[TMP73:%.*]] ]
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP69]], label [[TMP70:%.*]], label [[TMP73]]
+; CHECK: 70:
+; CHECK-NEXT: [[TMP71:%.*]] = extractelement <vscale x 1 x ptr> [[TMP64]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP72:%.*]] = ptrtoint ptr [[TMP71]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP72]], i64 4)
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP68]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP76:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP76]], label [[TMP77:%.*]], label [[TMP85:%.*]]
+; CHECK: 77:
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP79:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP78]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP77]] ], [ [[IV12_NEXT:%.*]], [[TMP84:%.*]] ]
+; CHECK-NEXT: [[TMP80:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP80]], label [[TMP81:%.*]], label [[TMP84]]
+; CHECK: 81:
+; CHECK-NEXT: [[TMP82:%.*]] = extractelement <vscale x 1 x ptr> [[TMP75]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP83:%.*]] = ptrtoint ptr [[TMP82]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP83]], i64 4)
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP79]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP85]]
+; CHECK: 85:
+; CHECK-NEXT: [[TMP86:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP8]]
+; CHECK-NEXT: [[TMP87:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP87]], label [[TMP88:%.*]], label [[TMP96:%.*]]
+; CHECK: 88:
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP90:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP89]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP88]] ], [ [[IV14_NEXT:%.*]], [[TMP95:%.*]] ]
+; CHECK-NEXT: [[TMP91:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP91]], label [[TMP92:%.*]], label [[TMP95]]
+; CHECK: 92:
+; CHECK-NEXT: [[TMP93:%.*]] = extractelement <vscale x 1 x ptr> [[TMP86]], i64 [[IV14]]
+; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr [[TMP93]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP94]], i64 4)
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP90]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP96]]
+; CHECK: 96:
+; CHECK-NEXT: [[TMP97:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg8.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP98:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP97]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP98]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg2_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP13:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x ptr> [[TMP3]], i64 [[IV]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP11]], i64 4)
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP24:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP17]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP16]] ], [ [[IV2_NEXT:%.*]], [[TMP23:%.*]] ]
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP23]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x ptr> [[TMP14]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP22]], i64 4)
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP18]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg2_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP13:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x ptr> [[TMP3]], i64 [[IV]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP11]], i64 4)
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP24:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP17]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP16]] ], [ [[IV2_NEXT:%.*]], [[TMP23:%.*]] ]
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP23]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x ptr> [[TMP14]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP22]], i64 4)
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP18]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg3_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg3_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP14:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP7]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x ptr> [[TMP4]], i64 [[IV]]
+; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP12]], i64 4)
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP16]], label [[TMP17:%.*]], label [[TMP25:%.*]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP18]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP17]] ], [ [[IV2_NEXT:%.*]], [[TMP24:%.*]] ]
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP24]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x ptr> [[TMP15]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[TMP22]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP23]], i64 4)
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP19]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP36:%.*]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP29]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP28]] ], [ [[IV4_NEXT:%.*]], [[TMP35:%.*]] ]
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP35]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x ptr> [[TMP26]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP33]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP34]], i64 4)
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP30]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg3_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP14:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP7]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x ptr> [[TMP4]], i64 [[IV]]
+; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP12]], i64 4)
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP16]], label [[TMP17:%.*]], label [[TMP25:%.*]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP18]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP17]] ], [ [[IV2_NEXT:%.*]], [[TMP24:%.*]] ]
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP24]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x ptr> [[TMP15]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[TMP22]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP23]], i64 4)
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP19]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP36:%.*]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP29]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP28]] ], [ [[IV4_NEXT:%.*]], [[TMP35:%.*]] ]
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP35]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x ptr> [[TMP26]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP33]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP34]], i64 4)
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP30]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg4_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg4_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP8]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP26:%.*]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP19]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP18]] ], [ [[IV2_NEXT:%.*]], [[TMP25:%.*]] ]
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP25]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x ptr> [[TMP16]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[TMP23]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP24]], i64 4)
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP20]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP28:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP37:%.*]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP30]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP29]] ], [ [[IV4_NEXT:%.*]], [[TMP36:%.*]] ]
+; CHECK-NEXT: [[TMP32:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP36]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x ptr> [[TMP27]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr [[TMP34]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP35]], i64 4)
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP31]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP39:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP39]], label [[TMP40:%.*]], label [[TMP48:%.*]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP41]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP40]] ], [ [[IV6_NEXT:%.*]], [[TMP47:%.*]] ]
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP47]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x ptr> [[TMP38]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP46:%.*]] = ptrtoint ptr [[TMP45]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP46]], i64 4)
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP42]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg4_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP8]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP26:%.*]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP19]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP18]] ], [ [[IV2_NEXT:%.*]], [[TMP25:%.*]] ]
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP25]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x ptr> [[TMP16]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[TMP23]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP24]], i64 4)
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP20]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP28:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP37:%.*]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP30]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP29]] ], [ [[IV4_NEXT:%.*]], [[TMP36:%.*]] ]
+; CHECK-NEXT: [[TMP32:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP36]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x ptr> [[TMP27]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr [[TMP34]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP35]], i64 4)
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP31]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP39:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP39]], label [[TMP40:%.*]], label [[TMP48:%.*]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP41]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP40]] ], [ [[IV6_NEXT:%.*]], [[TMP47:%.*]] ]
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP47]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x ptr> [[TMP38]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP46:%.*]] = ptrtoint ptr [[TMP45]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP46]], i64 4)
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP42]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg5_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg5_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP16:%.*]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP9]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]
+; CHECK: 12:
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x ptr> [[TMP6]], i64 [[IV]]
+; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP14]], i64 4)
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP18]], label [[TMP19:%.*]], label [[TMP27:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP20]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP19]] ], [ [[IV2_NEXT:%.*]], [[TMP26:%.*]] ]
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP22]], label [[TMP23:%.*]], label [[TMP26]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x ptr> [[TMP17]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP24]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP25]], i64 4)
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP21]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP29:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP38:%.*]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP31]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP30]] ], [ [[IV4_NEXT:%.*]], [[TMP37:%.*]] ]
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP33]], label [[TMP34:%.*]], label [[TMP37]]
+; CHECK: 34:
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x ptr> [[TMP28]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP36:%.*]] = ptrtoint ptr [[TMP35]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP36]], i64 4)
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP32]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP40:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP40]], label [[TMP41:%.*]], label [[TMP49:%.*]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP42]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP41]] ], [ [[IV6_NEXT:%.*]], [[TMP48:%.*]] ]
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP44]], label [[TMP45:%.*]], label [[TMP48]]
+; CHECK: 45:
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x ptr> [[TMP39]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP47:%.*]] = ptrtoint ptr [[TMP46]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP47]], i64 4)
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP43]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP51]], label [[TMP52:%.*]], label [[TMP60:%.*]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP53]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP52]] ], [ [[IV8_NEXT:%.*]], [[TMP59:%.*]] ]
+; CHECK-NEXT: [[TMP55:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP55]], label [[TMP56:%.*]], label [[TMP59]]
+; CHECK: 56:
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x ptr> [[TMP50]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP58:%.*]] = ptrtoint ptr [[TMP57]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP58]], i64 4)
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP54]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg5_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP16:%.*]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP9]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]
+; CHECK: 12:
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x ptr> [[TMP6]], i64 [[IV]]
+; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP14]], i64 4)
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP18]], label [[TMP19:%.*]], label [[TMP27:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP20]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP19]] ], [ [[IV2_NEXT:%.*]], [[TMP26:%.*]] ]
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP22]], label [[TMP23:%.*]], label [[TMP26]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x ptr> [[TMP17]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP24]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP25]], i64 4)
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP21]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP29:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP38:%.*]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP31]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP30]] ], [ [[IV4_NEXT:%.*]], [[TMP37:%.*]] ]
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP33]], label [[TMP34:%.*]], label [[TMP37]]
+; CHECK: 34:
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x ptr> [[TMP28]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP36:%.*]] = ptrtoint ptr [[TMP35]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP36]], i64 4)
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP32]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP40:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP40]], label [[TMP41:%.*]], label [[TMP49:%.*]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP42]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP41]] ], [ [[IV6_NEXT:%.*]], [[TMP48:%.*]] ]
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP44]], label [[TMP45:%.*]], label [[TMP48]]
+; CHECK: 45:
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x ptr> [[TMP39]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP47:%.*]] = ptrtoint ptr [[TMP46]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP47]], i64 4)
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP43]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP51]], label [[TMP52:%.*]], label [[TMP60:%.*]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP53]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP52]] ], [ [[IV8_NEXT:%.*]], [[TMP59:%.*]] ]
+; CHECK-NEXT: [[TMP55:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP55]], label [[TMP56:%.*]], label [[TMP59]]
+; CHECK: 56:
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x ptr> [[TMP50]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP58:%.*]] = ptrtoint ptr [[TMP57]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP58]], i64 4)
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP54]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg6_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg6_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP10]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP15]], i64 4)
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP28:%.*]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP21]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP20]] ], [ [[IV2_NEXT:%.*]], [[TMP27:%.*]] ]
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP23]], label [[TMP24:%.*]], label [[TMP27]]
+; CHECK: 24:
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x ptr> [[TMP18]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[TMP25]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP26]], i64 4)
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP22]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP30:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP39:%.*]]
+; CHECK: 31:
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP32]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP31]] ], [ [[IV4_NEXT:%.*]], [[TMP38:%.*]] ]
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP34]], label [[TMP35:%.*]], label [[TMP38]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x ptr> [[TMP29]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP37:%.*]] = ptrtoint ptr [[TMP36]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP37]], i64 4)
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP33]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[TMP40:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP41:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP50:%.*]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP43]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP42]] ], [ [[IV6_NEXT:%.*]], [[TMP49:%.*]] ]
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP45]], label [[TMP46:%.*]], label [[TMP49]]
+; CHECK: 46:
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x ptr> [[TMP40]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr [[TMP47]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP48]], i64 4)
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP44]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP52:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP52]], label [[TMP53:%.*]], label [[TMP61:%.*]]
+; CHECK: 53:
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP54]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP53]] ], [ [[IV8_NEXT:%.*]], [[TMP60:%.*]] ]
+; CHECK-NEXT: [[TMP56:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP56]], label [[TMP57:%.*]], label [[TMP60]]
+; CHECK: 57:
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x ptr> [[TMP51]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP59:%.*]] = ptrtoint ptr [[TMP58]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP59]], i64 4)
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP55]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[TMP62:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP63:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP63]], label [[TMP64:%.*]], label [[TMP72:%.*]]
+; CHECK: 64:
+; CHECK-NEXT: [[TMP65:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP65]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP64]] ], [ [[IV10_NEXT:%.*]], [[TMP71:%.*]] ]
+; CHECK-NEXT: [[TMP67:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP67]], label [[TMP68:%.*]], label [[TMP71]]
+; CHECK: 68:
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x ptr> [[TMP62]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP70:%.*]] = ptrtoint ptr [[TMP69]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP70]], i64 4)
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP66]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg6_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP10]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP15]], i64 4)
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP28:%.*]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP21]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP20]] ], [ [[IV2_NEXT:%.*]], [[TMP27:%.*]] ]
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP23]], label [[TMP24:%.*]], label [[TMP27]]
+; CHECK: 24:
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x ptr> [[TMP18]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[TMP25]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP26]], i64 4)
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP22]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP30:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP39:%.*]]
+; CHECK: 31:
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP32]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP31]] ], [ [[IV4_NEXT:%.*]], [[TMP38:%.*]] ]
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP34]], label [[TMP35:%.*]], label [[TMP38]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x ptr> [[TMP29]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP37:%.*]] = ptrtoint ptr [[TMP36]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP37]], i64 4)
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP33]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[TMP40:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP41:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP50:%.*]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP43]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP42]] ], [ [[IV6_NEXT:%.*]], [[TMP49:%.*]] ]
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP45]], label [[TMP46:%.*]], label [[TMP49]]
+; CHECK: 46:
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x ptr> [[TMP40]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr [[TMP47]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP48]], i64 4)
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP44]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP52:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP52]], label [[TMP53:%.*]], label [[TMP61:%.*]]
+; CHECK: 53:
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP54]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP53]] ], [ [[IV8_NEXT:%.*]], [[TMP60:%.*]] ]
+; CHECK-NEXT: [[TMP56:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP56]], label [[TMP57:%.*]], label [[TMP60]]
+; CHECK: 57:
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x ptr> [[TMP51]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP59:%.*]] = ptrtoint ptr [[TMP58]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP59]], i64 4)
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP55]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[TMP62:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP63:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP63]], label [[TMP64:%.*]], label [[TMP72:%.*]]
+; CHECK: 64:
+; CHECK-NEXT: [[TMP65:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP65]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP64]] ], [ [[IV10_NEXT:%.*]], [[TMP71:%.*]] ]
+; CHECK-NEXT: [[TMP67:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP67]], label [[TMP68:%.*]], label [[TMP71]]
+; CHECK: 68:
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x ptr> [[TMP62]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP70:%.*]] = ptrtoint ptr [[TMP69]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP70]], i64 4)
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP66]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg7_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg7_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP18:%.*]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP11]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP10]] ], [ [[IV_NEXT:%.*]], [[TMP17:%.*]] ]
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP17]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <vscale x 1 x ptr> [[TMP8]], i64 [[IV]]
+; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP15]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP16]], i64 4)
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP12]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP29:%.*]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP22]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP21]] ], [ [[IV2_NEXT:%.*]], [[TMP28:%.*]] ]
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP24]], label [[TMP25:%.*]], label [[TMP28]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <vscale x 1 x ptr> [[TMP19]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP27:%.*]] = ptrtoint ptr [[TMP26]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP27]], i64 4)
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP23]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP31:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP40:%.*]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP33]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP32]] ], [ [[IV4_NEXT:%.*]], [[TMP39:%.*]] ]
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP35]], label [[TMP36:%.*]], label [[TMP39]]
+; CHECK: 36:
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <vscale x 1 x ptr> [[TMP30]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr [[TMP37]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP38]], i64 4)
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP34]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP42:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP42]], label [[TMP43:%.*]], label [[TMP51:%.*]]
+; CHECK: 43:
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP44]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP43]] ], [ [[IV6_NEXT:%.*]], [[TMP50:%.*]] ]
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP46]], label [[TMP47:%.*]], label [[TMP50]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = extractelement <vscale x 1 x ptr> [[TMP41]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP49:%.*]] = ptrtoint ptr [[TMP48]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP49]], i64 4)
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP45]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[TMP52:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP53:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP62:%.*]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP55]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP54]] ], [ [[IV8_NEXT:%.*]], [[TMP61:%.*]] ]
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP57]], label [[TMP58:%.*]], label [[TMP61]]
+; CHECK: 58:
+; CHECK-NEXT: [[TMP59:%.*]] = extractelement <vscale x 1 x ptr> [[TMP52]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr [[TMP59]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP60]], i64 4)
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP56]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP64:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP64]], label [[TMP65:%.*]], label [[TMP73:%.*]]
+; CHECK: 65:
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP66]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP65]] ], [ [[IV10_NEXT:%.*]], [[TMP72:%.*]] ]
+; CHECK-NEXT: [[TMP68:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP68]], label [[TMP69:%.*]], label [[TMP72]]
+; CHECK: 69:
+; CHECK-NEXT: [[TMP70:%.*]] = extractelement <vscale x 1 x ptr> [[TMP63]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP71:%.*]] = ptrtoint ptr [[TMP70]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP71]], i64 4)
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP67]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[TMP74:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP75:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP75]], label [[TMP76:%.*]], label [[TMP84:%.*]]
+; CHECK: 76:
+; CHECK-NEXT: [[TMP77:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP77]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP76]] ], [ [[IV12_NEXT:%.*]], [[TMP83:%.*]] ]
+; CHECK-NEXT: [[TMP79:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP79]], label [[TMP80:%.*]], label [[TMP83]]
+; CHECK: 80:
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <vscale x 1 x ptr> [[TMP74]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP82:%.*]] = ptrtoint ptr [[TMP81]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP82]], i64 4)
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP78]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg7_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP18:%.*]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP11]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP10]] ], [ [[IV_NEXT:%.*]], [[TMP17:%.*]] ]
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP17]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <vscale x 1 x ptr> [[TMP8]], i64 [[IV]]
+; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP15]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP16]], i64 4)
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP12]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP29:%.*]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP22]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP21]] ], [ [[IV2_NEXT:%.*]], [[TMP28:%.*]] ]
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP24]], label [[TMP25:%.*]], label [[TMP28]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <vscale x 1 x ptr> [[TMP19]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP27:%.*]] = ptrtoint ptr [[TMP26]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP27]], i64 4)
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP23]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP31:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP40:%.*]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP33]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP32]] ], [ [[IV4_NEXT:%.*]], [[TMP39:%.*]] ]
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP35]], label [[TMP36:%.*]], label [[TMP39]]
+; CHECK: 36:
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <vscale x 1 x ptr> [[TMP30]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr [[TMP37]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP38]], i64 4)
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP34]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP42:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP42]], label [[TMP43:%.*]], label [[TMP51:%.*]]
+; CHECK: 43:
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP44]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP43]] ], [ [[IV6_NEXT:%.*]], [[TMP50:%.*]] ]
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP46]], label [[TMP47:%.*]], label [[TMP50]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = extractelement <vscale x 1 x ptr> [[TMP41]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP49:%.*]] = ptrtoint ptr [[TMP48]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP49]], i64 4)
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP45]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[TMP52:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP53:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP62:%.*]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP55]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP54]] ], [ [[IV8_NEXT:%.*]], [[TMP61:%.*]] ]
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP57]], label [[TMP58:%.*]], label [[TMP61]]
+; CHECK: 58:
+; CHECK-NEXT: [[TMP59:%.*]] = extractelement <vscale x 1 x ptr> [[TMP52]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr [[TMP59]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP60]], i64 4)
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP56]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP64:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP64]], label [[TMP65:%.*]], label [[TMP73:%.*]]
+; CHECK: 65:
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP66]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP65]] ], [ [[IV10_NEXT:%.*]], [[TMP72:%.*]] ]
+; CHECK-NEXT: [[TMP68:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP68]], label [[TMP69:%.*]], label [[TMP72]]
+; CHECK: 69:
+; CHECK-NEXT: [[TMP70:%.*]] = extractelement <vscale x 1 x ptr> [[TMP63]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP71:%.*]] = ptrtoint ptr [[TMP70]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP71]], i64 4)
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP67]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[TMP74:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP75:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP75]], label [[TMP76:%.*]], label [[TMP84:%.*]]
+; CHECK: 76:
+; CHECK-NEXT: [[TMP77:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP77]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP76]] ], [ [[IV12_NEXT:%.*]], [[TMP83:%.*]] ]
+; CHECK-NEXT: [[TMP79:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP79]], label [[TMP80:%.*]], label [[TMP83]]
+; CHECK: 80:
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <vscale x 1 x ptr> [[TMP74]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP82:%.*]] = ptrtoint ptr [[TMP81]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP82]], i64 4)
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP78]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg8_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg8_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 28, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP19:%.*]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP12]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP11]] ], [ [[IV_NEXT:%.*]], [[TMP18:%.*]] ]
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP14]], label [[TMP15:%.*]], label [[TMP18]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <vscale x 1 x ptr> [[TMP9]], i64 [[IV]]
+; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[TMP16]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP17]], i64 4)
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP13]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP19]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP30:%.*]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP24:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP23]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP22]] ], [ [[IV2_NEXT:%.*]], [[TMP29:%.*]] ]
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP29]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <vscale x 1 x ptr> [[TMP20]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[TMP27]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP28]], i64 4)
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP24]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP30]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP32:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP41:%.*]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP35:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP34]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP33]] ], [ [[IV4_NEXT:%.*]], [[TMP40:%.*]] ]
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP36]], label [[TMP37:%.*]], label [[TMP40]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = extractelement <vscale x 1 x ptr> [[TMP31]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP39:%.*]] = ptrtoint ptr [[TMP38]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP39]], i64 4)
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP35]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP41]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP52:%.*]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP46:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP45]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP44]] ], [ [[IV6_NEXT:%.*]], [[TMP51:%.*]] ]
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP47]], label [[TMP48:%.*]], label [[TMP51]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = extractelement <vscale x 1 x ptr> [[TMP42]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP50:%.*]] = ptrtoint ptr [[TMP49]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP50]], i64 4)
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP46]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP52]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP54:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP54]], label [[TMP55:%.*]], label [[TMP63:%.*]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP57:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP56]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP55]] ], [ [[IV8_NEXT:%.*]], [[TMP62:%.*]] ]
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP58]], label [[TMP59:%.*]], label [[TMP62]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = extractelement <vscale x 1 x ptr> [[TMP53]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP61:%.*]] = ptrtoint ptr [[TMP60]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP61]], i64 4)
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP57]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP63]]
+; CHECK: 63:
+; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP65:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP74:%.*]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP68:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP67]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP66]] ], [ [[IV10_NEXT:%.*]], [[TMP73:%.*]] ]
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP69]], label [[TMP70:%.*]], label [[TMP73]]
+; CHECK: 70:
+; CHECK-NEXT: [[TMP71:%.*]] = extractelement <vscale x 1 x ptr> [[TMP64]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP72:%.*]] = ptrtoint ptr [[TMP71]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP72]], i64 4)
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP68]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP76:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP76]], label [[TMP77:%.*]], label [[TMP85:%.*]]
+; CHECK: 77:
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP79:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP78]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP77]] ], [ [[IV12_NEXT:%.*]], [[TMP84:%.*]] ]
+; CHECK-NEXT: [[TMP80:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP80]], label [[TMP81:%.*]], label [[TMP84]]
+; CHECK: 81:
+; CHECK-NEXT: [[TMP82:%.*]] = extractelement <vscale x 1 x ptr> [[TMP75]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP83:%.*]] = ptrtoint ptr [[TMP82]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP83]], i64 4)
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP79]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP85]]
+; CHECK: 85:
+; CHECK-NEXT: [[TMP86:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP8]]
+; CHECK-NEXT: [[TMP87:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP87]], label [[TMP88:%.*]], label [[TMP96:%.*]]
+; CHECK: 88:
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP90:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP89]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP88]] ], [ [[IV14_NEXT:%.*]], [[TMP95:%.*]] ]
+; CHECK-NEXT: [[TMP91:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP91]], label [[TMP92:%.*]], label [[TMP95]]
+; CHECK: 92:
+; CHECK-NEXT: [[TMP93:%.*]] = extractelement <vscale x 1 x ptr> [[TMP86]], i64 [[IV14]]
+; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr [[TMP93]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP94]], i64 4)
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP90]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP96]]
+; CHECK: 96:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg8_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 28, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP19:%.*]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP12]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP11]] ], [ [[IV_NEXT:%.*]], [[TMP18:%.*]] ]
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP14]], label [[TMP15:%.*]], label [[TMP18]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <vscale x 1 x ptr> [[TMP9]], i64 [[IV]]
+; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[TMP16]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP17]], i64 4)
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP13]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP19]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP30:%.*]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP24:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP23]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP22]] ], [ [[IV2_NEXT:%.*]], [[TMP29:%.*]] ]
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP29]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <vscale x 1 x ptr> [[TMP20]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[TMP27]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP28]], i64 4)
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP24]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP30]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP32:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP41:%.*]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP35:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP34]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP33]] ], [ [[IV4_NEXT:%.*]], [[TMP40:%.*]] ]
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP36]], label [[TMP37:%.*]], label [[TMP40]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = extractelement <vscale x 1 x ptr> [[TMP31]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP39:%.*]] = ptrtoint ptr [[TMP38]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP39]], i64 4)
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP35]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP41]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP52:%.*]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP46:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP45]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP44]] ], [ [[IV6_NEXT:%.*]], [[TMP51:%.*]] ]
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP47]], label [[TMP48:%.*]], label [[TMP51]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = extractelement <vscale x 1 x ptr> [[TMP42]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP50:%.*]] = ptrtoint ptr [[TMP49]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP50]], i64 4)
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP46]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP52]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP54:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP54]], label [[TMP55:%.*]], label [[TMP63:%.*]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP57:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP56]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP55]] ], [ [[IV8_NEXT:%.*]], [[TMP62:%.*]] ]
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP58]], label [[TMP59:%.*]], label [[TMP62]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = extractelement <vscale x 1 x ptr> [[TMP53]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP61:%.*]] = ptrtoint ptr [[TMP60]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP61]], i64 4)
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP57]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP63]]
+; CHECK: 63:
+; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP65:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP74:%.*]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP68:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP67]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP66]] ], [ [[IV10_NEXT:%.*]], [[TMP73:%.*]] ]
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP69]], label [[TMP70:%.*]], label [[TMP73]]
+; CHECK: 70:
+; CHECK-NEXT: [[TMP71:%.*]] = extractelement <vscale x 1 x ptr> [[TMP64]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP72:%.*]] = ptrtoint ptr [[TMP71]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP72]], i64 4)
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP68]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP76:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP76]], label [[TMP77:%.*]], label [[TMP85:%.*]]
+; CHECK: 77:
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP79:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP78]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP77]] ], [ [[IV12_NEXT:%.*]], [[TMP84:%.*]] ]
+; CHECK-NEXT: [[TMP80:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP80]], label [[TMP81:%.*]], label [[TMP84]]
+; CHECK: 81:
+; CHECK-NEXT: [[TMP82:%.*]] = extractelement <vscale x 1 x ptr> [[TMP75]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP83:%.*]] = ptrtoint ptr [[TMP82]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP83]], i64 4)
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP79]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP85]]
+; CHECK: 85:
+; CHECK-NEXT: [[TMP86:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP8]]
+; CHECK-NEXT: [[TMP87:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP87]], label [[TMP88:%.*]], label [[TMP96:%.*]]
+; CHECK: 88:
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP90:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP89]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP88]] ], [ [[IV14_NEXT:%.*]], [[TMP95:%.*]] ]
+; CHECK-NEXT: [[TMP91:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP91]], label [[TMP92:%.*]], label [[TMP95]]
+; CHECK: 92:
+; CHECK-NEXT: [[TMP93:%.*]] = extractelement <vscale x 1 x ptr> [[TMP86]], i64 [[IV14]]
+; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr [[TMP93]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP94]], i64 4)
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP90]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP96]]
+; CHECK: 96:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg2_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP13:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x ptr> [[TMP3]], i64 [[IV]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP11]], i64 4)
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP24:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP17]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP16]] ], [ [[IV2_NEXT:%.*]], [[TMP23:%.*]] ]
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP23]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x ptr> [[TMP14]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP22]], i64 4)
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP18]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg2_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP13:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x ptr> [[TMP3]], i64 [[IV]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP11]], i64 4)
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP24:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP17]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP16]] ], [ [[IV2_NEXT:%.*]], [[TMP23:%.*]] ]
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP23]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x ptr> [[TMP14]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP22]], i64 4)
+; CHECK-NEXT: br label [[TMP23]]
+; CHECK: 23:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP18]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg3_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg3_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP14:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP7]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x ptr> [[TMP4]], i64 [[IV]]
+; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP12]], i64 4)
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP16]], label [[TMP17:%.*]], label [[TMP25:%.*]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP18]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP17]] ], [ [[IV2_NEXT:%.*]], [[TMP24:%.*]] ]
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP24]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x ptr> [[TMP15]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[TMP22]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP23]], i64 4)
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP19]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP36:%.*]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP29]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP28]] ], [ [[IV4_NEXT:%.*]], [[TMP35:%.*]] ]
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP35]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x ptr> [[TMP26]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP33]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP34]], i64 4)
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP30]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg3_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP14:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP7]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x ptr> [[TMP4]], i64 [[IV]]
+; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP12]], i64 4)
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP16]], label [[TMP17:%.*]], label [[TMP25:%.*]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP18]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP17]] ], [ [[IV2_NEXT:%.*]], [[TMP24:%.*]] ]
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP24]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x ptr> [[TMP15]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[TMP22]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP23]], i64 4)
+; CHECK-NEXT: br label [[TMP24]]
+; CHECK: 24:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP19]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP36:%.*]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP29]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP28]] ], [ [[IV4_NEXT:%.*]], [[TMP35:%.*]] ]
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP35]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x ptr> [[TMP26]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP33]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP34]], i64 4)
+; CHECK-NEXT: br label [[TMP35]]
+; CHECK: 35:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP30]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg4_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg4_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP8]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP26:%.*]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP19]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP18]] ], [ [[IV2_NEXT:%.*]], [[TMP25:%.*]] ]
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP25]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x ptr> [[TMP16]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[TMP23]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP24]], i64 4)
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP20]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP28:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP37:%.*]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP30]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP29]] ], [ [[IV4_NEXT:%.*]], [[TMP36:%.*]] ]
+; CHECK-NEXT: [[TMP32:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP36]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x ptr> [[TMP27]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr [[TMP34]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP35]], i64 4)
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP31]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP39:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP39]], label [[TMP40:%.*]], label [[TMP48:%.*]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP41]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP40]] ], [ [[IV6_NEXT:%.*]], [[TMP47:%.*]] ]
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP47]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x ptr> [[TMP38]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP46:%.*]] = ptrtoint ptr [[TMP45]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP46]], i64 4)
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP42]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg4_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP8]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP26:%.*]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP19]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP18]] ], [ [[IV2_NEXT:%.*]], [[TMP25:%.*]] ]
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP25]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x ptr> [[TMP16]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[TMP23]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP24]], i64 4)
+; CHECK-NEXT: br label [[TMP25]]
+; CHECK: 25:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP20]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP28:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP37:%.*]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP30]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP29]] ], [ [[IV4_NEXT:%.*]], [[TMP36:%.*]] ]
+; CHECK-NEXT: [[TMP32:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP36]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x ptr> [[TMP27]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr [[TMP34]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP35]], i64 4)
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP31]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP39:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP39]], label [[TMP40:%.*]], label [[TMP48:%.*]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP41]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP40]] ], [ [[IV6_NEXT:%.*]], [[TMP47:%.*]] ]
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP47]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x ptr> [[TMP38]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP46:%.*]] = ptrtoint ptr [[TMP45]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP46]], i64 4)
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP42]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg5_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg5_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP16:%.*]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP9]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]
+; CHECK: 12:
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x ptr> [[TMP6]], i64 [[IV]]
+; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP14]], i64 4)
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP18]], label [[TMP19:%.*]], label [[TMP27:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP20]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP19]] ], [ [[IV2_NEXT:%.*]], [[TMP26:%.*]] ]
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP22]], label [[TMP23:%.*]], label [[TMP26]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x ptr> [[TMP17]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP24]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP25]], i64 4)
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP21]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP29:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP38:%.*]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP31]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP30]] ], [ [[IV4_NEXT:%.*]], [[TMP37:%.*]] ]
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP33]], label [[TMP34:%.*]], label [[TMP37]]
+; CHECK: 34:
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x ptr> [[TMP28]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP36:%.*]] = ptrtoint ptr [[TMP35]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP36]], i64 4)
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP32]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP40:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP40]], label [[TMP41:%.*]], label [[TMP49:%.*]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP42]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP41]] ], [ [[IV6_NEXT:%.*]], [[TMP48:%.*]] ]
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP44]], label [[TMP45:%.*]], label [[TMP48]]
+; CHECK: 45:
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x ptr> [[TMP39]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP47:%.*]] = ptrtoint ptr [[TMP46]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP47]], i64 4)
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP43]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP51]], label [[TMP52:%.*]], label [[TMP60:%.*]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP53]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP52]] ], [ [[IV8_NEXT:%.*]], [[TMP59:%.*]] ]
+; CHECK-NEXT: [[TMP55:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP55]], label [[TMP56:%.*]], label [[TMP59]]
+; CHECK: 56:
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x ptr> [[TMP50]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP58:%.*]] = ptrtoint ptr [[TMP57]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP58]], i64 4)
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP54]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg5_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP16:%.*]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP9]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]
+; CHECK: 12:
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x ptr> [[TMP6]], i64 [[IV]]
+; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP14]], i64 4)
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP18]], label [[TMP19:%.*]], label [[TMP27:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP20]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP19]] ], [ [[IV2_NEXT:%.*]], [[TMP26:%.*]] ]
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP22]], label [[TMP23:%.*]], label [[TMP26]]
+; CHECK: 23:
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x ptr> [[TMP17]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP24]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP25]], i64 4)
+; CHECK-NEXT: br label [[TMP26]]
+; CHECK: 26:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP21]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP29:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP38:%.*]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP31]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP30]] ], [ [[IV4_NEXT:%.*]], [[TMP37:%.*]] ]
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP33]], label [[TMP34:%.*]], label [[TMP37]]
+; CHECK: 34:
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x ptr> [[TMP28]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP36:%.*]] = ptrtoint ptr [[TMP35]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP36]], i64 4)
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP32]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP40:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP40]], label [[TMP41:%.*]], label [[TMP49:%.*]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP42]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP41]] ], [ [[IV6_NEXT:%.*]], [[TMP48:%.*]] ]
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP44]], label [[TMP45:%.*]], label [[TMP48]]
+; CHECK: 45:
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x ptr> [[TMP39]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP47:%.*]] = ptrtoint ptr [[TMP46]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP47]], i64 4)
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP43]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP51]], label [[TMP52:%.*]], label [[TMP60:%.*]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP53]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP52]] ], [ [[IV8_NEXT:%.*]], [[TMP59:%.*]] ]
+; CHECK-NEXT: [[TMP55:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP55]], label [[TMP56:%.*]], label [[TMP59]]
+; CHECK: 56:
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x ptr> [[TMP50]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP58:%.*]] = ptrtoint ptr [[TMP57]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP58]], i64 4)
+; CHECK-NEXT: br label [[TMP59]]
+; CHECK: 59:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP54]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg6_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg6_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP10]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP15]], i64 4)
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP28:%.*]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP21]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP20]] ], [ [[IV2_NEXT:%.*]], [[TMP27:%.*]] ]
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP23]], label [[TMP24:%.*]], label [[TMP27]]
+; CHECK: 24:
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x ptr> [[TMP18]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[TMP25]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP26]], i64 4)
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP22]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP30:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP39:%.*]]
+; CHECK: 31:
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP32]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP31]] ], [ [[IV4_NEXT:%.*]], [[TMP38:%.*]] ]
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP34]], label [[TMP35:%.*]], label [[TMP38]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x ptr> [[TMP29]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP37:%.*]] = ptrtoint ptr [[TMP36]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP37]], i64 4)
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP33]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[TMP40:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP41:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP50:%.*]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP43]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP42]] ], [ [[IV6_NEXT:%.*]], [[TMP49:%.*]] ]
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP45]], label [[TMP46:%.*]], label [[TMP49]]
+; CHECK: 46:
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x ptr> [[TMP40]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr [[TMP47]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP48]], i64 4)
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP44]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP52:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP52]], label [[TMP53:%.*]], label [[TMP61:%.*]]
+; CHECK: 53:
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP54]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP53]] ], [ [[IV8_NEXT:%.*]], [[TMP60:%.*]] ]
+; CHECK-NEXT: [[TMP56:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP56]], label [[TMP57:%.*]], label [[TMP60]]
+; CHECK: 57:
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x ptr> [[TMP51]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP59:%.*]] = ptrtoint ptr [[TMP58]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP59]], i64 4)
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP55]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[TMP62:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP63:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP63]], label [[TMP64:%.*]], label [[TMP72:%.*]]
+; CHECK: 64:
+; CHECK-NEXT: [[TMP65:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP65]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP64]] ], [ [[IV10_NEXT:%.*]], [[TMP71:%.*]] ]
+; CHECK-NEXT: [[TMP67:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP67]], label [[TMP68:%.*]], label [[TMP71]]
+; CHECK: 68:
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x ptr> [[TMP62]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP70:%.*]] = ptrtoint ptr [[TMP69]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP70]], i64 4)
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP66]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg6_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP10]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP15]], i64 4)
+; CHECK-NEXT: br label [[TMP16]]
+; CHECK: 16:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP19]], label [[TMP20:%.*]], label [[TMP28:%.*]]
+; CHECK: 20:
+; CHECK-NEXT: [[TMP21:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP21]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP20]] ], [ [[IV2_NEXT:%.*]], [[TMP27:%.*]] ]
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP23]], label [[TMP24:%.*]], label [[TMP27]]
+; CHECK: 24:
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x ptr> [[TMP18]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[TMP25]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP26]], i64 4)
+; CHECK-NEXT: br label [[TMP27]]
+; CHECK: 27:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP22]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP30:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP39:%.*]]
+; CHECK: 31:
+; CHECK-NEXT: [[TMP32:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP32]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP31]] ], [ [[IV4_NEXT:%.*]], [[TMP38:%.*]] ]
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP34]], label [[TMP35:%.*]], label [[TMP38]]
+; CHECK: 35:
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x ptr> [[TMP29]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP37:%.*]] = ptrtoint ptr [[TMP36]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP37]], i64 4)
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP33]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[TMP40:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP41:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP41]], label [[TMP42:%.*]], label [[TMP50:%.*]]
+; CHECK: 42:
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP43]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP42]] ], [ [[IV6_NEXT:%.*]], [[TMP49:%.*]] ]
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP45]], label [[TMP46:%.*]], label [[TMP49]]
+; CHECK: 46:
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x ptr> [[TMP40]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr [[TMP47]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP48]], i64 4)
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP44]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[TMP51:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP52:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP52]], label [[TMP53:%.*]], label [[TMP61:%.*]]
+; CHECK: 53:
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP54]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP53]] ], [ [[IV8_NEXT:%.*]], [[TMP60:%.*]] ]
+; CHECK-NEXT: [[TMP56:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP56]], label [[TMP57:%.*]], label [[TMP60]]
+; CHECK: 57:
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x ptr> [[TMP51]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP59:%.*]] = ptrtoint ptr [[TMP58]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP59]], i64 4)
+; CHECK-NEXT: br label [[TMP60]]
+; CHECK: 60:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP55]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[TMP62:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP63:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP63]], label [[TMP64:%.*]], label [[TMP72:%.*]]
+; CHECK: 64:
+; CHECK-NEXT: [[TMP65:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP65]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP64]] ], [ [[IV10_NEXT:%.*]], [[TMP71:%.*]] ]
+; CHECK-NEXT: [[TMP67:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP67]], label [[TMP68:%.*]], label [[TMP71]]
+; CHECK: 68:
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x ptr> [[TMP62]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP70:%.*]] = ptrtoint ptr [[TMP69]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP70]], i64 4)
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP66]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg7_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg7_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP18:%.*]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP11]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP10]] ], [ [[IV_NEXT:%.*]], [[TMP17:%.*]] ]
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP17]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <vscale x 1 x ptr> [[TMP8]], i64 [[IV]]
+; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP15]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP16]], i64 4)
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP12]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP29:%.*]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP22]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP21]] ], [ [[IV2_NEXT:%.*]], [[TMP28:%.*]] ]
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP24]], label [[TMP25:%.*]], label [[TMP28]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <vscale x 1 x ptr> [[TMP19]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP27:%.*]] = ptrtoint ptr [[TMP26]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP27]], i64 4)
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP23]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP31:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP40:%.*]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP33]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP32]] ], [ [[IV4_NEXT:%.*]], [[TMP39:%.*]] ]
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP35]], label [[TMP36:%.*]], label [[TMP39]]
+; CHECK: 36:
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <vscale x 1 x ptr> [[TMP30]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr [[TMP37]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP38]], i64 4)
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP34]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP42:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP42]], label [[TMP43:%.*]], label [[TMP51:%.*]]
+; CHECK: 43:
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP44]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP43]] ], [ [[IV6_NEXT:%.*]], [[TMP50:%.*]] ]
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP46]], label [[TMP47:%.*]], label [[TMP50]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = extractelement <vscale x 1 x ptr> [[TMP41]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP49:%.*]] = ptrtoint ptr [[TMP48]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP49]], i64 4)
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP45]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[TMP52:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP53:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP62:%.*]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP55]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP54]] ], [ [[IV8_NEXT:%.*]], [[TMP61:%.*]] ]
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP57]], label [[TMP58:%.*]], label [[TMP61]]
+; CHECK: 58:
+; CHECK-NEXT: [[TMP59:%.*]] = extractelement <vscale x 1 x ptr> [[TMP52]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr [[TMP59]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP60]], i64 4)
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP56]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP64:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP64]], label [[TMP65:%.*]], label [[TMP73:%.*]]
+; CHECK: 65:
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP66]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP65]] ], [ [[IV10_NEXT:%.*]], [[TMP72:%.*]] ]
+; CHECK-NEXT: [[TMP68:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP68]], label [[TMP69:%.*]], label [[TMP72]]
+; CHECK: 69:
+; CHECK-NEXT: [[TMP70:%.*]] = extractelement <vscale x 1 x ptr> [[TMP63]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP71:%.*]] = ptrtoint ptr [[TMP70]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP71]], i64 4)
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP67]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[TMP74:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP75:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP75]], label [[TMP76:%.*]], label [[TMP84:%.*]]
+; CHECK: 76:
+; CHECK-NEXT: [[TMP77:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP77]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP76]] ], [ [[IV12_NEXT:%.*]], [[TMP83:%.*]] ]
+; CHECK-NEXT: [[TMP79:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP79]], label [[TMP80:%.*]], label [[TMP83]]
+; CHECK: 80:
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <vscale x 1 x ptr> [[TMP74]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP82:%.*]] = ptrtoint ptr [[TMP81]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP82]], i64 4)
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP78]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg7_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP18:%.*]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP11]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP10]] ], [ [[IV_NEXT:%.*]], [[TMP17:%.*]] ]
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP17]]
+; CHECK: 14:
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <vscale x 1 x ptr> [[TMP8]], i64 [[IV]]
+; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP15]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP16]], i64 4)
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP12]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP20]], label [[TMP21:%.*]], label [[TMP29:%.*]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP22]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP21]] ], [ [[IV2_NEXT:%.*]], [[TMP28:%.*]] ]
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP24]], label [[TMP25:%.*]], label [[TMP28]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <vscale x 1 x ptr> [[TMP19]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP27:%.*]] = ptrtoint ptr [[TMP26]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP27]], i64 4)
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP23]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP31:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP40:%.*]]
+; CHECK: 32:
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP33]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP32]] ], [ [[IV4_NEXT:%.*]], [[TMP39:%.*]] ]
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP35]], label [[TMP36:%.*]], label [[TMP39]]
+; CHECK: 36:
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <vscale x 1 x ptr> [[TMP30]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr [[TMP37]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP38]], i64 4)
+; CHECK-NEXT: br label [[TMP39]]
+; CHECK: 39:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP34]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP42:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP42]], label [[TMP43:%.*]], label [[TMP51:%.*]]
+; CHECK: 43:
+; CHECK-NEXT: [[TMP44:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP44]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP43]] ], [ [[IV6_NEXT:%.*]], [[TMP50:%.*]] ]
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP46]], label [[TMP47:%.*]], label [[TMP50]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = extractelement <vscale x 1 x ptr> [[TMP41]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP49:%.*]] = ptrtoint ptr [[TMP48]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP49]], i64 4)
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP45]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[TMP52:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP53:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP53]], label [[TMP54:%.*]], label [[TMP62:%.*]]
+; CHECK: 54:
+; CHECK-NEXT: [[TMP55:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP55]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP54]] ], [ [[IV8_NEXT:%.*]], [[TMP61:%.*]] ]
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP57]], label [[TMP58:%.*]], label [[TMP61]]
+; CHECK: 58:
+; CHECK-NEXT: [[TMP59:%.*]] = extractelement <vscale x 1 x ptr> [[TMP52]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr [[TMP59]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP60]], i64 4)
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP56]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[TMP63:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP64:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP64]], label [[TMP65:%.*]], label [[TMP73:%.*]]
+; CHECK: 65:
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP66]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP65]] ], [ [[IV10_NEXT:%.*]], [[TMP72:%.*]] ]
+; CHECK-NEXT: [[TMP68:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP68]], label [[TMP69:%.*]], label [[TMP72]]
+; CHECK: 69:
+; CHECK-NEXT: [[TMP70:%.*]] = extractelement <vscale x 1 x ptr> [[TMP63]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP71:%.*]] = ptrtoint ptr [[TMP70]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP71]], i64 4)
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP67]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[TMP74:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP75:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP75]], label [[TMP76:%.*]], label [[TMP84:%.*]]
+; CHECK: 76:
+; CHECK-NEXT: [[TMP77:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP77]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP76]] ], [ [[IV12_NEXT:%.*]], [[TMP83:%.*]] ]
+; CHECK-NEXT: [[TMP79:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP79]], label [[TMP80:%.*]], label [[TMP83]]
+; CHECK: 80:
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <vscale x 1 x ptr> [[TMP74]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP82:%.*]] = ptrtoint ptr [[TMP81]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP82]], i64 4)
+; CHECK-NEXT: br label [[TMP83]]
+; CHECK: 83:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP78]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg8_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg8_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 28, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP19:%.*]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP12]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP11]] ], [ [[IV_NEXT:%.*]], [[TMP18:%.*]] ]
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP14]], label [[TMP15:%.*]], label [[TMP18]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <vscale x 1 x ptr> [[TMP9]], i64 [[IV]]
+; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[TMP16]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP17]], i64 4)
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP13]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP19]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP30:%.*]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP24:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP23]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP22]] ], [ [[IV2_NEXT:%.*]], [[TMP29:%.*]] ]
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP29]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <vscale x 1 x ptr> [[TMP20]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[TMP27]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP28]], i64 4)
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP24]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP30]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP32:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP41:%.*]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP35:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP34]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP33]] ], [ [[IV4_NEXT:%.*]], [[TMP40:%.*]] ]
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP36]], label [[TMP37:%.*]], label [[TMP40]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = extractelement <vscale x 1 x ptr> [[TMP31]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP39:%.*]] = ptrtoint ptr [[TMP38]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP39]], i64 4)
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP35]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP41]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP52:%.*]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP46:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP45]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP44]] ], [ [[IV6_NEXT:%.*]], [[TMP51:%.*]] ]
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP47]], label [[TMP48:%.*]], label [[TMP51]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = extractelement <vscale x 1 x ptr> [[TMP42]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP50:%.*]] = ptrtoint ptr [[TMP49]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP50]], i64 4)
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP46]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP52]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP54:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP54]], label [[TMP55:%.*]], label [[TMP63:%.*]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP57:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP56]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP55]] ], [ [[IV8_NEXT:%.*]], [[TMP62:%.*]] ]
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP58]], label [[TMP59:%.*]], label [[TMP62]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = extractelement <vscale x 1 x ptr> [[TMP53]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP61:%.*]] = ptrtoint ptr [[TMP60]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP61]], i64 4)
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP57]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP63]]
+; CHECK: 63:
+; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP65:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP74:%.*]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP68:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP67]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP66]] ], [ [[IV10_NEXT:%.*]], [[TMP73:%.*]] ]
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP69]], label [[TMP70:%.*]], label [[TMP73]]
+; CHECK: 70:
+; CHECK-NEXT: [[TMP71:%.*]] = extractelement <vscale x 1 x ptr> [[TMP64]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP72:%.*]] = ptrtoint ptr [[TMP71]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP72]], i64 4)
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP68]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP76:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP76]], label [[TMP77:%.*]], label [[TMP85:%.*]]
+; CHECK: 77:
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP79:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP78]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP77]] ], [ [[IV12_NEXT:%.*]], [[TMP84:%.*]] ]
+; CHECK-NEXT: [[TMP80:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP80]], label [[TMP81:%.*]], label [[TMP84]]
+; CHECK: 81:
+; CHECK-NEXT: [[TMP82:%.*]] = extractelement <vscale x 1 x ptr> [[TMP75]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP83:%.*]] = ptrtoint ptr [[TMP82]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP83]], i64 4)
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP79]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP85]]
+; CHECK: 85:
+; CHECK-NEXT: [[TMP86:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP8]]
+; CHECK-NEXT: [[TMP87:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP87]], label [[TMP88:%.*]], label [[TMP96:%.*]]
+; CHECK: 88:
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP90:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP89]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP88]] ], [ [[IV14_NEXT:%.*]], [[TMP95:%.*]] ]
+; CHECK-NEXT: [[TMP91:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP91]], label [[TMP92:%.*]], label [[TMP95]]
+; CHECK: 92:
+; CHECK-NEXT: [[TMP93:%.*]] = extractelement <vscale x 1 x ptr> [[TMP86]], i64 [[IV14]]
+; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr [[TMP93]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP94]], i64 4)
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP90]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP96]]
+; CHECK: 96:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg8_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>
+; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 4, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP3:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 8, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP4:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 12, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP5:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 16, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 20, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 24, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP8:%.*]] = add <vscale x 1 x i64> [[TMP1]], shufflevector (<vscale x 1 x i64> insertelement (<vscale x 1 x i64> poison, i64 28, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]
+; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i64 [[VL:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP19:%.*]]
+; CHECK: 11:
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP12]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP11]] ], [ [[IV_NEXT:%.*]], [[TMP18:%.*]] ]
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP14]], label [[TMP15:%.*]], label [[TMP18]]
+; CHECK: 15:
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <vscale x 1 x ptr> [[TMP9]], i64 [[IV]]
+; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[TMP16]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP17]], i64 4)
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP13]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP19]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP30:%.*]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP24:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP23]])
+; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
+; CHECK: .split1:
+; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP22]] ], [ [[IV2_NEXT:%.*]], [[TMP29:%.*]] ]
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV2]]
+; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP29]]
+; CHECK: 26:
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <vscale x 1 x ptr> [[TMP20]], i64 [[IV2]]
+; CHECK-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[TMP27]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP28]], i64 4)
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
+; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP24]]
+; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
+; CHECK: .split1.split:
+; CHECK-NEXT: br label [[TMP30]]
+; CHECK: 30:
+; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP32:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP41:%.*]]
+; CHECK: 33:
+; CHECK-NEXT: [[TMP34:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP35:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP34]])
+; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
+; CHECK: .split3:
+; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ 0, [[TMP33]] ], [ [[IV4_NEXT:%.*]], [[TMP40:%.*]] ]
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV4]]
+; CHECK-NEXT: br i1 [[TMP36]], label [[TMP37:%.*]], label [[TMP40]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = extractelement <vscale x 1 x ptr> [[TMP31]], i64 [[IV4]]
+; CHECK-NEXT: [[TMP39:%.*]] = ptrtoint ptr [[TMP38]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP39]], i64 4)
+; CHECK-NEXT: br label [[TMP40]]
+; CHECK: 40:
+; CHECK-NEXT: [[IV4_NEXT]] = add nuw nsw i64 [[IV4]], 1
+; CHECK-NEXT: [[IV4_CHECK:%.*]] = icmp eq i64 [[IV4_NEXT]], [[TMP35]]
+; CHECK-NEXT: br i1 [[IV4_CHECK]], label [[DOTSPLIT3_SPLIT:%.*]], label [[DOTSPLIT3]]
+; CHECK: .split3.split:
+; CHECK-NEXT: br label [[TMP41]]
+; CHECK: 41:
+; CHECK-NEXT: [[TMP42:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP4]]
+; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP43]], label [[TMP44:%.*]], label [[TMP52:%.*]]
+; CHECK: 44:
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP46:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP45]])
+; CHECK-NEXT: br label [[DOTSPLIT5:%.*]]
+; CHECK: .split5:
+; CHECK-NEXT: [[IV6:%.*]] = phi i64 [ 0, [[TMP44]] ], [ [[IV6_NEXT:%.*]], [[TMP51:%.*]] ]
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV6]]
+; CHECK-NEXT: br i1 [[TMP47]], label [[TMP48:%.*]], label [[TMP51]]
+; CHECK: 48:
+; CHECK-NEXT: [[TMP49:%.*]] = extractelement <vscale x 1 x ptr> [[TMP42]], i64 [[IV6]]
+; CHECK-NEXT: [[TMP50:%.*]] = ptrtoint ptr [[TMP49]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP50]], i64 4)
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: [[IV6_NEXT]] = add nuw nsw i64 [[IV6]], 1
+; CHECK-NEXT: [[IV6_CHECK:%.*]] = icmp eq i64 [[IV6_NEXT]], [[TMP46]]
+; CHECK-NEXT: br i1 [[IV6_CHECK]], label [[DOTSPLIT5_SPLIT:%.*]], label [[DOTSPLIT5]]
+; CHECK: .split5.split:
+; CHECK-NEXT: br label [[TMP52]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP5]]
+; CHECK-NEXT: [[TMP54:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP54]], label [[TMP55:%.*]], label [[TMP63:%.*]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP57:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP56]])
+; CHECK-NEXT: br label [[DOTSPLIT7:%.*]]
+; CHECK: .split7:
+; CHECK-NEXT: [[IV8:%.*]] = phi i64 [ 0, [[TMP55]] ], [ [[IV8_NEXT:%.*]], [[TMP62:%.*]] ]
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV8]]
+; CHECK-NEXT: br i1 [[TMP58]], label [[TMP59:%.*]], label [[TMP62]]
+; CHECK: 59:
+; CHECK-NEXT: [[TMP60:%.*]] = extractelement <vscale x 1 x ptr> [[TMP53]], i64 [[IV8]]
+; CHECK-NEXT: [[TMP61:%.*]] = ptrtoint ptr [[TMP60]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP61]], i64 4)
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: [[IV8_NEXT]] = add nuw nsw i64 [[IV8]], 1
+; CHECK-NEXT: [[IV8_CHECK:%.*]] = icmp eq i64 [[IV8_NEXT]], [[TMP57]]
+; CHECK-NEXT: br i1 [[IV8_CHECK]], label [[DOTSPLIT7_SPLIT:%.*]], label [[DOTSPLIT7]]
+; CHECK: .split7.split:
+; CHECK-NEXT: br label [[TMP63]]
+; CHECK: 63:
+; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP65:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP66:%.*]], label [[TMP74:%.*]]
+; CHECK: 66:
+; CHECK-NEXT: [[TMP67:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP68:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP67]])
+; CHECK-NEXT: br label [[DOTSPLIT9:%.*]]
+; CHECK: .split9:
+; CHECK-NEXT: [[IV10:%.*]] = phi i64 [ 0, [[TMP66]] ], [ [[IV10_NEXT:%.*]], [[TMP73:%.*]] ]
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV10]]
+; CHECK-NEXT: br i1 [[TMP69]], label [[TMP70:%.*]], label [[TMP73]]
+; CHECK: 70:
+; CHECK-NEXT: [[TMP71:%.*]] = extractelement <vscale x 1 x ptr> [[TMP64]], i64 [[IV10]]
+; CHECK-NEXT: [[TMP72:%.*]] = ptrtoint ptr [[TMP71]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP72]], i64 4)
+; CHECK-NEXT: br label [[TMP73]]
+; CHECK: 73:
+; CHECK-NEXT: [[IV10_NEXT]] = add nuw nsw i64 [[IV10]], 1
+; CHECK-NEXT: [[IV10_CHECK:%.*]] = icmp eq i64 [[IV10_NEXT]], [[TMP68]]
+; CHECK-NEXT: br i1 [[IV10_CHECK]], label [[DOTSPLIT9_SPLIT:%.*]], label [[DOTSPLIT9]]
+; CHECK: .split9.split:
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 74:
+; CHECK-NEXT: [[TMP75:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP76:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP76]], label [[TMP77:%.*]], label [[TMP85:%.*]]
+; CHECK: 77:
+; CHECK-NEXT: [[TMP78:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP79:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP78]])
+; CHECK-NEXT: br label [[DOTSPLIT11:%.*]]
+; CHECK: .split11:
+; CHECK-NEXT: [[IV12:%.*]] = phi i64 [ 0, [[TMP77]] ], [ [[IV12_NEXT:%.*]], [[TMP84:%.*]] ]
+; CHECK-NEXT: [[TMP80:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV12]]
+; CHECK-NEXT: br i1 [[TMP80]], label [[TMP81:%.*]], label [[TMP84]]
+; CHECK: 81:
+; CHECK-NEXT: [[TMP82:%.*]] = extractelement <vscale x 1 x ptr> [[TMP75]], i64 [[IV12]]
+; CHECK-NEXT: [[TMP83:%.*]] = ptrtoint ptr [[TMP82]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP83]], i64 4)
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: [[IV12_NEXT]] = add nuw nsw i64 [[IV12]], 1
+; CHECK-NEXT: [[IV12_CHECK:%.*]] = icmp eq i64 [[IV12_NEXT]], [[TMP79]]
+; CHECK-NEXT: br i1 [[IV12_CHECK]], label [[DOTSPLIT11_SPLIT:%.*]], label [[DOTSPLIT11]]
+; CHECK: .split11.split:
+; CHECK-NEXT: br label [[TMP85]]
+; CHECK: 85:
+; CHECK-NEXT: [[TMP86:%.*]] = getelementptr i8, ptr [[BASE]], <vscale x 1 x i64> [[TMP8]]
+; CHECK-NEXT: [[TMP87:%.*]] = icmp ne i64 [[VL]], 0
+; CHECK-NEXT: br i1 [[TMP87]], label [[TMP88:%.*]], label [[TMP96:%.*]]
+; CHECK: 88:
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP90:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP89]])
+; CHECK-NEXT: br label [[DOTSPLIT13:%.*]]
+; CHECK: .split13:
+; CHECK-NEXT: [[IV14:%.*]] = phi i64 [ 0, [[TMP88]] ], [ [[IV14_NEXT:%.*]], [[TMP95:%.*]] ]
+; CHECK-NEXT: [[TMP91:%.*]] = extractelement <vscale x 1 x i1> [[MASK]], i64 [[IV14]]
+; CHECK-NEXT: br i1 [[TMP91]], label [[TMP92:%.*]], label [[TMP95]]
+; CHECK: 92:
+; CHECK-NEXT: [[TMP93:%.*]] = extractelement <vscale x 1 x ptr> [[TMP86]], i64 [[IV14]]
+; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr [[TMP93]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP94]], i64 4)
+; CHECK-NEXT: br label [[TMP95]]
+; CHECK: 95:
+; CHECK-NEXT: [[IV14_NEXT]] = add nuw nsw i64 [[IV14]], 1
+; CHECK-NEXT: [[IV14_CHECK:%.*]] = icmp eq i64 [[IV14_NEXT]], [[TMP90]]
+; CHECK-NEXT: br i1 [[IV14_CHECK]], label [[DOTSPLIT13_SPLIT:%.*]], label [[DOTSPLIT13]]
+; CHECK: .split13.split:
+; CHECK-NEXT: br label [[TMP96]]
+; CHECK: 96:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.masked.strided.load.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr, i64,<vscale x 1 x i1>)
+define <vscale x 1 x i32> @intrinsic_masked_strided_load_nxv1i32(ptr align 4 %ptr, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @intrinsic_masked_strided_load_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: br label [[ENTRY_SPLIT:%.*]]
+; CHECK: entry.split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[TMP7:%.*]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP7]]
+; CHECK: 3:
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[IV]], 4
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP6]])
+; CHECK-NEXT: br label [[TMP7]]
+; CHECK: 7:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP1]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[ENTRY_SPLIT_SPLIT:%.*]], label [[ENTRY_SPLIT]]
+; CHECK: entry.split.split:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.masked.strided.load.nxv1i32.p0.i64(<vscale x 1 x i32> undef, ptr [[PTR]], i64 4, <vscale x 1 x i1> [[MASK]])
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.masked.strided.load.nxv1i32.p0.i64(
+ <vscale x 1 x i32> undef,
+ ptr %ptr,
+ i64 4,
+ <vscale x 1 x i1> %mask)
+ ret <vscale x 1 x i32> %a
+}
+
+declare void @llvm.riscv.masked.strided.store.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr, i64,<vscale x 1 x i1>)
+define void @intrinsic_masked_strided_store_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %ptr, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @intrinsic_masked_strided_store_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: br label [[ENTRY_SPLIT:%.*]]
+; CHECK: entry.split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[TMP7:%.*]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP7]]
+; CHECK: 3:
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[IV]], 4
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP6]])
+; CHECK-NEXT: br label [[TMP7]]
+; CHECK: 7:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP1]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[ENTRY_SPLIT_SPLIT:%.*]], label [[ENTRY_SPLIT]]
+; CHECK: entry.split.split:
+; CHECK-NEXT: call void @llvm.riscv.masked.strided.store.nxv1i32.p0.i64(<vscale x 1 x i32> [[VAL:%.*]], ptr [[PTR]], i64 4, <vscale x 1 x i1> [[MASK]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.masked.strided.store.nxv1i32.p0.i64(
+ <vscale x 1 x i32> %val,
+ ptr %ptr,
+ i64 4,
+ <vscale x 1 x i1> %mask)
+ ret void
+}
diff --git a/llvm/test/Instrumentation/AddressSanitizer/asan-rvv-intrinsics.ll b/llvm/test/Instrumentation/AddressSanitizer/asan-rvv-intrinsics.ll
new file mode 100644
index 0000000000000..566de87a95cda
--- /dev/null
+++ b/llvm/test/Instrumentation/AddressSanitizer/asan-rvv-intrinsics.ll
@@ -0,0 +1,2209 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=riscv64 -mattr=+v -passes=asan \
+; RUN: -asan-instrumentation-with-call-threshold=0 -S | FileCheck %s
+
+declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ i64)
+define <vscale x 1 x i32> @intrinsic_vle_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* align 4 %0, i64 %1) sanitize_address {
+; CHECK-LABEL: @intrinsic_vle_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP11:%.*]]
+; CHECK: 3:
+; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 [[TMP4]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP3]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP10]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr <vscale x 1 x i32>, ptr [[TMP0:%.*]], i64 0, i64 [[IV]]
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP9]])
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP5]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, ptr [[TMP0]], i64 [[TMP1]])
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32(
+ <vscale x 1 x i32> undef,
+ <vscale x 1 x i32>* %0,
+ i64 %1)
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i1>,
+ i64,
+ i64)
+define <vscale x 1 x i32> @intrinsic_vle_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* align 4 %1, <vscale x 1 x i1> %2, i64 %3) sanitize_address {
+; CHECK-LABEL: @intrinsic_vle_mask_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP13:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> [[TMP2:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr <vscale x 1 x i32>, ptr [[TMP1:%.*]], i64 0, i64 [[IV]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP11]])
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i1> [[TMP2]], i64 [[TMP3]], i64 1)
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i1> %2,
+ i64 %3, i64 1)
+ ret <vscale x 1 x i32> %a
+}
+
+declare void @llvm.riscv.vse.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ i64)
+define void @intrinsic_vse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* align 4 %1, i64 %2) sanitize_address {
+; CHECK-LABEL: @intrinsic_vse_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[TMP2:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]
+; CHECK: 4:
+; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP5]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr <vscale x 1 x i32>, ptr [[TMP1:%.*]], i64 0, i64 [[IV]]
+; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP10]])
+; CHECK-NEXT: br label [[TMP11]]
+; CHECK: 11:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: call void @llvm.riscv.vse.nxv1i32.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vse.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ i64 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vse.mask.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i1>,
+ i64)
+define void @intrinsic_vse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* align 4 %1, <vscale x 1 x i1> %2, i64 %3) sanitize_address {
+; CHECK-LABEL: @intrinsic_vse_mask_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP13:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> [[TMP2:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr <vscale x 1 x i32>, ptr [[TMP1:%.*]], i64 0, i64 [[IV]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP11]])
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i1> [[TMP2]], i64 [[TMP3]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vse.mask.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i1> %2,
+ i64 %3)
+ ret void
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg2_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg2_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg2_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg2_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg3_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg3_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg3_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg3_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg4_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg4_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg4_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg4_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg5_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg5_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg5_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg5_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg6_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg6_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg6_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg6_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg7_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg7_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg7_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg7_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlseg8_nxv1i32(ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlseg8_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlseg8_mask_nxv1i32(ptr align 4 %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlseg8_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.mask.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ ret <vscale x 1 x i32> %1
+}
+
+declare void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg2_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg2_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg2.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg2_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg2.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg3_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg3_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg3.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg3_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg3.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg4_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg4_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg4.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg4_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg4.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg5_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg5_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg5.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg5_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg5.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg6_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg6_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg6.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg6_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg6.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg7_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg7_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg7.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg7_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg7.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg8_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg8_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg8.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %base, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsseg8_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsseg8.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+; Test stride load
+declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ i64,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* align 4 %0, i64 %1, i64 %2) sanitize_address {
+; CHECK-LABEL: @intrinsic_vlse_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[TMP2:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]]
+; CHECK: 4:
+; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP5]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP12]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[IV]], [[TMP1:%.*]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], i64 [[TMP9]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP11]], i64 4)
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> undef, ptr [[TMP0]], i64 [[TMP1]], i64 [[TMP2]])
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(
+ <vscale x 1 x i32> undef,
+ <vscale x 1 x i32>* %0,
+ i64 %1,
+ i64 %2)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ i64,
+ <vscale x 1 x i1>,
+ i64,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vlse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {
+; CHECK-LABEL: @intrinsic_vlse_mask_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP15:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP7]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP14]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[IV]], [[TMP2:%.*]]
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], i64 [[TMP11]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]], i64 1)
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ i64 %2,
+ <vscale x 1 x i1> %3,
+ i64 %4, i64 1)
+
+ ret <vscale x 1 x i32> %a
+}
+
+; Test stride store
+declare void @llvm.riscv.vsse.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ i64,
+ i64);
+
+define void @intrinsic_vsse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i64 %2, i64 %3) sanitize_address {
+; CHECK-LABEL: @intrinsic_vsse_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP14:%.*]]
+; CHECK: 5:
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP6]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP13]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[IV]], [[TMP2:%.*]]
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], i64 [[TMP10]]
+; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP12]], i64 4)
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: call void @llvm.riscv.vsse.nxv1i32.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]], i64 [[TMP3]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vsse.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ i64 %2,
+ i64 %3)
+
+ ret void
+}
+
+declare void @llvm.riscv.vsse.mask.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ i64,
+ <vscale x 1 x i1>,
+ i64);
+
+define void @intrinsic_vsse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {
+; CHECK-LABEL: @intrinsic_vsse_mask_v_nxv1i32_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP15:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP7]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP14]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[IV]], [[TMP2:%.*]]
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], i64 [[TMP11]]
+; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP13]], i64 4)
+; CHECK-NEXT: br label [[TMP14]]
+; CHECK: 14:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP15]]
+; CHECK: 15:
+; CHECK-NEXT: call void @llvm.riscv.vsse.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vsse.mask.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ i64 %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret void
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg2_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg2_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg2.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg2_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg2_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg2.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg2.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP2]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP3]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg3_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg3_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg3.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg3_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg3_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg3.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg3.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP2]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP3]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg4_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg4_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg4.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg4_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg4_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg4.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg4.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP2]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP3]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg5_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg5_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg5.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg5_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg5_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg5.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg5.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP2]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP3]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg6_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg6_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg6.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg6_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg6_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg6.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg6.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP2]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP3]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg7_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg7_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg7.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg7_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg7_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg7.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg7.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP2]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP3]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vlsseg8_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vlsseg8_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg8.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlsseg8_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vlsseg8_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg8.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlsseg8.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], <vscale x 1 x i32> [[TMP1]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL]], i64 1)
+; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP2]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP3]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %offset, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+ %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+ ret <vscale x 1 x i32> %3
+}
+
+declare void @llvm.riscv.vssseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg2_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg2_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg2.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg2_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg2_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg2.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vssseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg3_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg3_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg3.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg3_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg3_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg3.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vssseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg4_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg4_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg4.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg4_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg4_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg4.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vssseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg5_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg5_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg5.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg5_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg5_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg5.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vssseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg6_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg6_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg6.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg6_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg6_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg6.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vssseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg7_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg7_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg7.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg7_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg7_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg7.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vssseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, i64)
+declare void @llvm.riscv.vssseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, i64, <vscale x 1 x i1>, i64)
+
+define void @test_vssseg8_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg8_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg8.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, i64 %vl)
+ ret void
+}
+
+define void @test_vssseg8_mask_nxv1i32(<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vssseg8_mask_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vssseg8.mask.nxv1i32.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vssseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+; Test stride value is a multiple of pointer alignment.
+define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32_align(<vscale x 1 x i32>* align 4 %0, i64 %1, i64 %2) sanitize_address {
+; CHECK-LABEL: @intrinsic_vlse_v_nxv1i32_nxv1i32_align(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[TMP2:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]]
+; CHECK: 4:
+; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP5]])
+; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
+; CHECK: .split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer), i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP12]]
+; CHECK: 8:
+; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[IV]], 4
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], i64 [[TMP9]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP11]])
+; CHECK-NEXT: br label [[TMP12]]
+; CHECK: 12:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
+; CHECK: .split.split:
+; CHECK-NEXT: br label [[TMP13]]
+; CHECK: 13:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> undef, ptr [[TMP0]], i64 4, i64 [[TMP2]])
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(
+ <vscale x 1 x i32> undef,
+ <vscale x 1 x i32>* %0,
+ i64 4,
+ i64 %2)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i64 %2) sanitize_address {
+; CHECK-LABEL: @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, ptr [[TMP0:%.*]], <vscale x 1 x i16> [[TMP1:%.*]], i64 [[TMP2:%.*]])
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> undef,
+ <vscale x 1 x i32>* %0,
+ <vscale x 1 x i16> %1,
+ i64 %2)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i1>,
+ i64,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {
+; CHECK-LABEL: @intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1:%.*]], <vscale x 1 x i16> [[TMP2:%.*]], <vscale x 1 x i1> [[TMP3:%.*]], i64 [[TMP4:%.*]], i64 1)
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i16> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4, i64 1)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
+ <vscale x 1 x float>,
+ <vscale x 1 x float>*,
+ <vscale x 1 x i16>,
+ i64);
+
+define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i64 %2) sanitize_address {
+; CHECK-LABEL: @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16.i64(<vscale x 1 x float> undef, ptr [[TMP0:%.*]], <vscale x 1 x i16> [[TMP1:%.*]], i64 [[TMP2:%.*]])
+; CHECK-NEXT: ret <vscale x 1 x float> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
+ <vscale x 1 x float> undef,
+ <vscale x 1 x float>* %0,
+ <vscale x 1 x i16> %1,
+ i64 %2)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i64 %2) sanitize_address {
+; CHECK-LABEL: @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, ptr [[TMP0:%.*]], <vscale x 1 x i16> [[TMP1:%.*]], i64 [[TMP2:%.*]])
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> undef,
+ <vscale x 1 x i32>* %0,
+ <vscale x 1 x i16> %1,
+ i64 %2)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i1>,
+ i64,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {
+; CHECK-LABEL: @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1:%.*]], <vscale x 1 x i16> [[TMP2:%.*]], <vscale x 1 x i1> [[TMP3:%.*]], i64 [[TMP4:%.*]], i64 1)
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i16> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4, i64 1)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare void @llvm.riscv.vsoxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ i64);
+
+define void @intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, i64 %3) sanitize_address {
+; CHECK-LABEL: @intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: call void @llvm.riscv.vsoxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1:%.*]], <vscale x 1 x i16> [[TMP2:%.*]], i64 [[TMP3:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vsoxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i16> %2,
+ i64 %3)
+
+ ret void
+}
+
+declare void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i1>,
+ i64);
+
+define void @intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {
+; CHECK-LABEL: @intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1:%.*]], <vscale x 1 x i16> [[TMP2:%.*]], <vscale x 1 x i1> [[TMP3:%.*]], i64 [[TMP4:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i16> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret void
+}
+
+declare void @llvm.riscv.vsuxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ i64);
+
+define void @intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, i64 %3) sanitize_address {
+; CHECK-LABEL: @intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: call void @llvm.riscv.vsuxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1:%.*]], <vscale x 1 x i16> [[TMP2:%.*]], i64 [[TMP3:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vsuxei.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i16> %2,
+ i64 %3)
+
+ ret void
+}
+
+declare void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i1>,
+ i64);
+
+define void @intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {
+; CHECK-LABEL: @intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1:%.*]], <vscale x 1 x i16> [[TMP2:%.*]], <vscale x 1 x i1> [[TMP3:%.*]], i64 [[TMP4:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32>* %1,
+ <vscale x 1 x i16> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret void
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg2_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg2_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg2.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg2_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg2.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg3_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg3_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg3.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg3_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg3.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg4_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg4_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg4.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg4_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg4.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg5_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg5_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg5.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg5_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg5.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg6_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg6_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg6.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg6_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg6.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg7_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg7_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg7.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg7_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg7.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vloxseg8_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vloxseg8_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg8.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vloxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vloxseg8_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vloxseg8.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vloxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg2_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg2_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg2.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg2_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg3_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg3_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg3.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg3_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg3.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg4_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg4_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg4.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg4_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg4.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg5_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg5_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg5.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg5_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg5.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg6_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg6_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg6.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg6_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg6.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg7_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg7_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg7.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg7_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg7.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64)
+
+define <vscale x 1 x i32> @test_vluxseg8_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vluxseg8_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg8.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vluxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @test_vluxseg8_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vluxseg8.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+;
+entry:
+ %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vluxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
+ %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+ ret <vscale x 1 x i32> %1
+}
+
+declare void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg2_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg2_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg3_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg3_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg3_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg4_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg4_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg4_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg5_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg5_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg5_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg6_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg6_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg6_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg7_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg7_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg7_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsoxseg8_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg8_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsoxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsoxseg8_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg2_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg2_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg3_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg3_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg3_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg4_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg4_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg4_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg5_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg5_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg5_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg6_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg6_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg6_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg7_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg7_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg7_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg8_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg8_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
+ ret void
+}
+
+define void @test_vsuxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) sanitize_address {
+; CHECK-LABEL: @test_vsuxseg8_mask_nxv1i32_nxv1i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[VAL:%.*]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], <vscale x 1 x i32> [[VAL]], ptr [[BASE:%.*]], <vscale x 1 x i16> [[INDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+; CHECK-NEXT: ret void
+;
+entry:
+ tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.masked.strided.load.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr, i64,<vscale x 1 x i1>)
+define <vscale x 1 x i32> @intrinsic_masked_strided_load_nxv1i32(ptr align 4 %ptr, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @intrinsic_masked_strided_load_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: br label [[ENTRY_SPLIT:%.*]]
+; CHECK: entry.split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[TMP6:%.*]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP6]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[IV]], 4
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[TMP4]] to i64
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP5]])
+; CHECK-NEXT: br label [[TMP6]]
+; CHECK: 6:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP0]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[ENTRY_SPLIT_SPLIT:%.*]], label [[ENTRY_SPLIT]]
+; CHECK: entry.split.split:
+; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.masked.strided.load.nxv1i32.p0.i64(<vscale x 1 x i32> undef, ptr [[PTR]], i64 4, <vscale x 1 x i1> [[MASK]])
+; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]
+;
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.masked.strided.load.nxv1i32.p0.i64(
+ <vscale x 1 x i32> undef,
+ ptr %ptr,
+ i64 4,
+ <vscale x 1 x i1> %mask)
+ ret <vscale x 1 x i32> %a
+}
+
+declare void @llvm.riscv.masked.strided.store.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr, i64,<vscale x 1 x i1>)
+define void @intrinsic_masked_strided_store_nxv1i32(<vscale x 1 x i32> %val, ptr align 4 %ptr, <vscale x 1 x i1> %mask) sanitize_address {
+; CHECK-LABEL: @intrinsic_masked_strided_store_nxv1i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: br label [[ENTRY_SPLIT:%.*]]
+; CHECK: entry.split:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[TMP6:%.*]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP6]]
+; CHECK: 2:
+; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[IV]], 4
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[TMP4]] to i64
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP5]])
+; CHECK-NEXT: br label [[TMP6]]
+; CHECK: 6:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP0]]
+; CHECK-NEXT: br i1 [[IV_CHECK]], label [[ENTRY_SPLIT_SPLIT:%.*]], label [[ENTRY_SPLIT]]
+; CHECK: entry.split.split:
+; CHECK-NEXT: call void @llvm.riscv.masked.strided.store.nxv1i32.p0.i64(<vscale x 1 x i32> [[VAL:%.*]], ptr [[PTR]], i64 4, <vscale x 1 x i1> [[MASK]])
+; CHECK-NEXT: ret void
+;
+entry:
+ call void @llvm.riscv.masked.strided.store.nxv1i32.p0.i64(
+ <vscale x 1 x i32> %val,
+ ptr %ptr,
+ i64 4,
+ <vscale x 1 x i1> %mask)
+ ret void
+}
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