[llvm] [RegisterCoalescer] Fix SUBREG_TO_REG handling in the RegisterCoalescer. (PR #96839)

[Kai Luo via llvm-commits]

bzEq wrote:

> %2 [32r,112r:0) 0 at 32r  L000000000000000F [16r,112r:0) 0 at 16r  weight:0.000000e+00

Is it typo? The main liverange should not be shorter than subrange. I tried this patch, looks it should be
Before coalescing 
```
%2 [32r,112r:0) 0 at 32r  weight:0.000000e+00
```
After coalescing
```
%2 [16r,112r:0) 0 at 16r  L000000000000000F [16r,112r:0) 0 at 16r  weight:0.000000e+00
```
During coalescing,
```
32B %2:gr64_nosp = SUBREG_TO_REG 0, %0:gr32, %subreg.sub_32bit                                                                                                                               
  Considering merging to GR64_NOSP with %0 in %2:sub_32bit                                                                                                                                   
    RHS = %0 [16r,32r:0) 0 at 16r  weight:0.000000e+00                                                                                                                                          
    LHS = %2 [32r,112r:0) 0 at 32r  weight:0.000000e+00                                                                                                                                         
    merge %2:0 at 32r into %0:0 at 16r --> @16r                                                                                                                                                    
    merge %2:0 at 32r into %0:0 at 16r --> @16r                                                                                                                                                    
    joined lanes: 000000000000000F [16r,112r:0) 0 at 16r                                                                                                                                        
    Expecting instruction removal at 32r                                                                                                                                                     
    erased: 32r %2:gr64_nosp = SUBREG_TO_REG 0, %0:gr32, %subreg.sub_32bit
    updated: 16B  undef %2.sub_32bit:gr64_nosp = MOV32rm undef %1:gr64, 1, $noreg, 0, $noreg :: (volatile load (s32) from `ptr undef`)                                                       
  Success: %0:sub_32bit -> %2                                                                                                                                                                
  Result = %2 [16r,112r:0) 0 at 16r  L000000000000000F [16r,112r:0) 0 at 16r  weight:0.000000e+00
```

https://github.com/llvm/llvm-project/pull/96839