[llvm] [RISCV] Allow non-power-of-2 vectors for VLS code generation (PR #97010)

[Kito Cheng via llvm-commits]

kito-cheng wrote:


> As an alternative to creating new MVTs for odd sizes though, have you considered just letting SelectionDAG widen them to the next legal VL? Asides from reductions and loads/stores, increasing the VL shouldn't impact performance. I also landed a patch a few years ago that should widen loads and stores of illegal fixed-length vector sizes to VP ops: https://reviews.llvm.org/D148713

Yeah, and I didn't go that way in my first intuition since that way may take more work then just adding MVT, however that remind we may have another way to doing that: doing at LLVM IR, which means doing that on CodeGenPrepare, that may prevent us to doing that again on GlobalISel for non-power-of-2 support again :P

> And then to avoid VL toggles from the discrepancy between the widened ops VLs and loads/stores VLs, I think my original plan was to take advantage of https://llvm.org/devmtg/2023-05/slides/Posters/01-Albano-VectorPredictionPoster.pdf somehow to reduce the VL of the widened ops

One possibility is just doing that in backend, RISC-V GCC already do that in RTL/backend, so I guess that should be do-able on MI with SSA, but that would be much complicate way.

https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv-avlprop.cc

https://github.com/llvm/llvm-project/pull/97010