[llvm] [X86][SimplifyCFG] Support hoisting load/store with conditional faulting (PR #96878)

[Shengchen Kan via llvm-commits]

KanRobert wrote:

> How is the performance of the hoisting load/store being benchmarked? I don't know the specific implementation in microarchitecture, but using these conditional instructions to replace a very easy-to-predict branch may negatively contribute to performance. Is there any microarchitecture simulator or real chip implemented so we can benchmark the performance?

I can share code for check predictability

```
  // If the branch is non-unpredictable, and is predicted to *not* branch to
  // the `then` block, then avoid speculating it.
  if (!BI->getMetadata(LLVMContext::MD_unpredictable)) {
    uint64_t TWeight, FWeight;
    if (extractBranchWeights(*BI, TWeight, FWeight) &&
        (TWeight + FWeight) != 0) {
      uint64_t EndWeight = Invert ? TWeight : FWeight;
      BranchProbability BIEndProb =
          BranchProbability::getBranchProbability(EndWeight, TWeight + FWeight);
      BranchProbability Likely = TTI.getPredictableBranchThreshold();
      if (BIEndProb >= Likely)
        return false;
    }
  }
``` 
in `SpeculativelyExecuteBB` with the newly added transform.

We have a internal cycle-accurate performance simulators. The real chip is not public yet. You know, even if I have data, I can't make any comments on the performance of future HW.

https://github.com/llvm/llvm-project/pull/96878