[llvm] [AArch64] Switch to LiveRegUnits (PR #96840)
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Thu Jun 27 17:13:26 PDT 2024
https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/96840
>From 101e8ff8e1b879de749eec81dfc24cde84d89e68 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Wed, 26 Jun 2024 23:07:44 -0400
Subject: [PATCH] Reapply "[AArch64][NFC] Switch to LiveRegUnits (#87313)"
This reverts commit 84314d0ae49628e17667a2d927cb835ecf3d62b8.
---
.../Target/AArch64/AArch64FrameLowering.cpp | 32 +++++++++----------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 8216fa7db822c..22023eb7f9e69 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -197,6 +197,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -1011,7 +1012,7 @@ void AArch64FrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,
}
}
-static void getLiveRegsForEntryMBB(LivePhysRegs &LiveRegs,
+static void getLiveRegsForEntryMBB(LiveRegUnits &LiveRegs,
const MachineBasicBlock &MBB) {
const MachineFunction *MF = MBB.getParent();
LiveRegs.addLiveIns(MBB);
@@ -1044,16 +1045,18 @@ static Register findScratchNonCalleeSaveRegister(MachineBasicBlock *MBB) {
const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>();
const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
- LivePhysRegs LiveRegs(TRI);
+ LiveRegUnits LiveRegs(TRI);
getLiveRegsForEntryMBB(LiveRegs, *MBB);
// Prefer X9 since it was historically used for the prologue scratch reg.
- const MachineRegisterInfo &MRI = MF->getRegInfo();
- if (LiveRegs.available(MRI, AArch64::X9))
+ if (LiveRegs.available(AArch64::X9))
return AArch64::X9;
- for (unsigned Reg : AArch64::GPR64RegClass) {
- if (LiveRegs.available(MRI, Reg))
+ BitVector Allocatable =
+ TRI.getAllocatableSet(*MF, TRI.getRegClass(AArch64::GPR64RegClassID));
+
+ for (unsigned Reg : Allocatable.set_bits()) {
+ if (LiveRegs.available(Reg))
return Reg;
}
return AArch64::NoRegister;
@@ -1069,14 +1072,11 @@ bool AArch64FrameLowering::canUseAsPrologue(
const AArch64FunctionInfo *AFI = MF->getInfo<AArch64FunctionInfo>();
if (AFI->hasSwiftAsyncContext()) {
- const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
- const MachineRegisterInfo &MRI = MF->getRegInfo();
- LivePhysRegs LiveRegs(TRI);
+ LiveRegUnits LiveRegs(*RegInfo);
getLiveRegsForEntryMBB(LiveRegs, MBB);
// The StoreSwiftAsyncContext clobbers X16 and X17. Make sure they are
// available.
- if (!LiveRegs.available(MRI, AArch64::X16) ||
- !LiveRegs.available(MRI, AArch64::X17))
+ if (!LiveRegs.available(AArch64::X16) || !LiveRegs.available(AArch64::X17))
return false;
}
@@ -1668,7 +1668,7 @@ static void emitDefineCFAWithFP(MachineFunction &MF, MachineBasicBlock &MBB,
/// Collect live registers from the end of \p MI's parent up to (including) \p
/// MI in \p LiveRegs.
static void getLivePhysRegsUpTo(MachineInstr &MI, const TargetRegisterInfo &TRI,
- LivePhysRegs &LiveRegs) {
+ LiveRegUnits &LiveRegs) {
MachineBasicBlock &MBB = *MI.getParent();
LiveRegs.addLiveOuts(MBB);
@@ -1706,7 +1706,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
NonFrameStart->getFlag(MachineInstr::FrameSetup))
++NonFrameStart;
- LivePhysRegs LiveRegs(*TRI);
+ LiveRegUnits LiveRegs(*TRI);
if (NonFrameStart != MBB.end()) {
getLivePhysRegsUpTo(*NonFrameStart, *TRI, LiveRegs);
// Ignore registers used for stack management for now.
@@ -1730,7 +1730,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
make_range(MBB.instr_begin(), NonFrameStart->getIterator())) {
for (auto &Op : MI.operands())
if (Op.isReg() && Op.isDef())
- assert(!LiveRegs.contains(Op.getReg()) &&
+ assert(LiveRegs.available(Op.getReg()) &&
"live register clobbered by inserted prologue instructions");
}
});
@@ -4324,7 +4324,7 @@ MachineBasicBlock::iterator tryMergeAdjacentSTG(MachineBasicBlock::iterator II,
// FIXME : This approach of bailing out from merge is conservative in
// some ways like even if stg loops are not present after merge the
// insert list, this liveness check is done (which is not needed).
- LivePhysRegs LiveRegs(*(MBB->getParent()->getSubtarget().getRegisterInfo()));
+ LiveRegUnits LiveRegs(*(MBB->getParent()->getSubtarget().getRegisterInfo()));
LiveRegs.addLiveOuts(*MBB);
for (auto I = MBB->rbegin();; ++I) {
MachineInstr &MI = *I;
@@ -4333,7 +4333,7 @@ MachineBasicBlock::iterator tryMergeAdjacentSTG(MachineBasicBlock::iterator II,
LiveRegs.stepBackward(*I);
}
InsertI++;
- if (LiveRegs.contains(AArch64::NZCV))
+ if (!LiveRegs.available(AArch64::NZCV))
return InsertI;
llvm::stable_sort(Instrs,
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