[llvm] [AArch64] Add flag setting instructions to scheduling model. (PR #96880)

Ricardo Jesus via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 27 08:32:36 PDT 2024


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@@ -1108,12 +1108,18 @@ def : InstRW<[V2Write_1cyc_1B_1R], (instrs BL, BLR)>;
 // ALU, basic
 // ALU, basic, flagset
 def : SchedAlias<WriteI, V2Write_1cyc_1I>;
-def : InstRW<[V2Write_1cyc_1F], (instregex "^(ADC|SBC)S[WX]r$")>;
+def : InstRW<[V2Write_1cyc_1F], (instregex "^(ADD|SUB)S[WX]r[ir]$",
+                        "^(ADC|SBC)S[WX]r$",
+                        "^ANDS[WX]ri$")>;
 def : InstRW<[V2Write_0or1cyc_1I], (instregex "^MOVZ[WX]i$")>;
 
 // ALU, extend and shift
 def : SchedAlias<WriteIEReg, V2Write_2cyc_1M>;
 
+// Conditional compare
+def : InstRW<[V2Write_1cyc_1F],
+            (instregex "^CCMP(W|X)(i|r)", "^CCMN(W|X)(i|r)")>;
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rj-jesus wrote:

Thanks

https://github.com/llvm/llvm-project/pull/96880


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