[llvm] [AArch64] Add flag setting instructions to scheduling model. (PR #96880)

[Ricardo Jesus via llvm-commits]

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@@ -1108,12 +1108,18 @@ def : InstRW<[V2Write_1cyc_1B_1R], (instrs BL, BLR)>;
 // ALU, basic
 // ALU, basic, flagset
 def : SchedAlias<WriteI, V2Write_1cyc_1I>;
-def : InstRW<[V2Write_1cyc_1F], (instregex "^(ADC|SBC)S[WX]r$")>;
+def : InstRW<[V2Write_1cyc_1F], (instregex "^(ADD|SUB)S[WX]r[ir]$",
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rj-jesus wrote:

I believe `r` is wrong in the last group, should be `s`, but that's already captured a few lines down.
```suggestion
def : InstRW<[V2Write_1cyc_1F], (instregex "^(ADD|SUB)S[WX]ri$",
```
Also, it is not clear to me if for ADD{S}/SUB{S} (immediate), this should only apply for "LSL shift, shift <= 4". Have you tested with `LSL #12`?

https://github.com/llvm/llvm-project/pull/96880