[llvm] 4e70720 - [AMDGPU] Add some gfx1200 test coverage
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 27 06:56:21 PDT 2024
Author: Jay Foad
Date: 2024-06-27T14:53:59+01:00
New Revision: 4e70720139ff8b03ab02087df249ce4fd4bbfd59
URL: https://github.com/llvm/llvm-project/commit/4e70720139ff8b03ab02087df249ce4fd4bbfd59
DIFF: https://github.com/llvm/llvm-project/commit/4e70720139ff8b03ab02087df249ce4fd4bbfd59.diff
LOG: [AMDGPU] Add some gfx1200 test coverage
Added:
Modified:
llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll b/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
index 74b9d98257fb3..ac03d2dae8fa8 100644
--- a/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
+++ b/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
@@ -1,7 +1,8 @@
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -show-mc-encoding < %s | FileCheck -check-prefixes=CHECK,GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -show-mc-encoding < %s | FileCheck -check-prefixes=CHECK,GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -show-mc-encoding < %s | FileCheck -check-prefixes=CHECK,GFX11,GFX1100 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -show-mc-encoding < %s | FileCheck -check-prefixes=CHECK,GFX11,GFX1150 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX9,NOT-GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX10,NOT-GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11,GFX1100,NOT-GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11,GFX1150,NOT-GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX1200 %s
declare float @llvm.fabs.f32(float)
declare float @llvm.fma.f32(float, float, float)
@@ -24,10 +25,21 @@ define float @v_mul_f32_vop2(float %x, float %y) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf]
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 ; encoding: [0x00,0x03,0x00,0x10]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
+;
+; GFX1200-LABEL: v_mul_f32_vop2:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+; GFX1200-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+; GFX1200-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+; GFX1200-NEXT: v_mul_f32_e32 v0, v0, v1 ; encoding: [0x00,0x03,0x00,0x10]
+; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
%mul = fmul float %x, %y
ret float %mul
}
-; CHECK: codeLenInByte = 12
+; NOT-GFX12: codeLenInByte = 12
+; GFX1200: codeLenInByte = 28
define float @v_mul_f32_vop2_inline_imm(float %x) {
; GFX9-LABEL: v_mul_f32_vop2_inline_imm:
@@ -47,10 +59,21 @@ define float @v_mul_f32_vop2_inline_imm(float %x) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf]
; GFX11-NEXT: v_mul_f32_e32 v0, 4.0, v0 ; encoding: [0xf6,0x00,0x00,0x10]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
+;
+; GFX1200-LABEL: v_mul_f32_vop2_inline_imm:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+; GFX1200-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+; GFX1200-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+; GFX1200-NEXT: v_mul_f32_e32 v0, 4.0, v0 ; encoding: [0xf6,0x00,0x00,0x10]
+; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
%mul = fmul float %x, 4.0
ret float %mul
}
-; CHECK: codeLenInByte = 12
+; NOT-GFX12: codeLenInByte = 12
+; GFX1200: codeLenInByte = 28
define float @v_mul_f32_vop2_literal(float %x) {
; GFX9-LABEL: v_mul_f32_vop2_literal:
@@ -70,10 +93,21 @@ define float @v_mul_f32_vop2_literal(float %x) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf]
; GFX11-NEXT: v_mul_f32_e32 v0, 0x42f60000, v0 ; encoding: [0xff,0x00,0x00,0x10,0x00,0x00,0xf6,0x42]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
+;
+; GFX1200-LABEL: v_mul_f32_vop2_literal:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+; GFX1200-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+; GFX1200-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+; GFX1200-NEXT: v_mul_f32_e32 v0, 0x42f60000, v0 ; encoding: [0xff,0x00,0x00,0x10,0x00,0x00,0xf6,0x42]
+; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
%mul = fmul float %x, 123.0
ret float %mul
}
-; CHECK: codeLenInByte = 16
+; NOT-GFX12: codeLenInByte = 16
+; GFX1200: codeLenInByte = 32
define float @v_mul_f32_vop3_src_mods(float %x, float %y) {
; GFX9-LABEL: v_mul_f32_vop3_src_mods:
@@ -93,11 +127,22 @@ define float @v_mul_f32_vop3_src_mods(float %x, float %y) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf]
; GFX11-NEXT: v_mul_f32_e64 v0, |v0|, v1 ; encoding: [0x00,0x01,0x08,0xd5,0x00,0x03,0x02,0x00]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
+;
+; GFX1200-LABEL: v_mul_f32_vop3_src_mods:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+; GFX1200-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+; GFX1200-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+; GFX1200-NEXT: v_mul_f32_e64 v0, |v0|, v1 ; encoding: [0x00,0x01,0x08,0xd5,0x00,0x03,0x02,0x00]
+; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
%fabs.x = call float @llvm.fabs.f32(float %x)
%mul = fmul float %fabs.x, %y
ret float %mul
}
-; CHECK: codeLenInByte = 16
+; NOT-GFX12: codeLenInByte = 16
+; GFX1200: codeLenInByte = 32
define float @v_mul_f32_vop3_src_mods_inline_imm(float %x, float %y) {
; GFX9-LABEL: v_mul_f32_vop3_src_mods_inline_imm:
@@ -117,12 +162,23 @@ define float @v_mul_f32_vop3_src_mods_inline_imm(float %x, float %y) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf]
; GFX11-NEXT: v_mul_f32_e64 v0, |v0|, 4.0 ; encoding: [0x00,0x01,0x08,0xd5,0x00,0xed,0x01,0x00]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
+;
+; GFX1200-LABEL: v_mul_f32_vop3_src_mods_inline_imm:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+; GFX1200-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+; GFX1200-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+; GFX1200-NEXT: v_mul_f32_e64 v0, |v0|, 4.0 ; encoding: [0x00,0x01,0x08,0xd5,0x00,0xed,0x01,0x00]
+; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
%fabs.x = call float @llvm.fabs.f32(float %x)
%mul = fmul float %fabs.x, 4.0
ret float %mul
}
-; CHECK: codeLenInByte = 16
+; NOT-GFX12: codeLenInByte = 16
+; GFX1200: codeLenInByte = 32
define float @v_mul_f32_vop3_src_mods_literal(float %x, float %y) {
; GFX9-LABEL: v_mul_f32_vop3_src_mods_literal:
@@ -143,6 +199,16 @@ define float @v_mul_f32_vop3_src_mods_literal(float %x, float %y) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf]
; GFX11-NEXT: v_mul_f32_e64 v0, 0x42f60000, |v0| ; encoding: [0x00,0x02,0x08,0xd5,0xff,0x00,0x02,0x00,0x00,0x00,0xf6,0x42]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
+;
+; GFX1200-LABEL: v_mul_f32_vop3_src_mods_literal:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+; GFX1200-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+; GFX1200-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+; GFX1200-NEXT: v_mul_f32_e64 v0, 0x42f60000, |v0| ; encoding: [0x00,0x02,0x08,0xd5,0xff,0x00,0x02,0x00,0x00,0x00,0xf6,0x42]
+; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
%fabs.x = call float @llvm.fabs.f32(float %x)
%mul = fmul float %fabs.x, 123.0
ret float %mul
@@ -151,6 +217,7 @@ define float @v_mul_f32_vop3_src_mods_literal(float %x, float %y) {
; GFX9: codeLenInByte = 24
; GFX10: codeLenInByte = 20
; GFX11: codeLenInByte = 20
+; GFX1200: codeLenInByte = 36
define float @v_mul_f32_vop2_frame_index(float %x) {
; GFX9-LABEL: v_mul_f32_vop2_frame_index:
@@ -172,6 +239,16 @@ define float @v_mul_f32_vop2_frame_index(float %x) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf]
; GFX11-NEXT: v_mul_f32_e32 v0, s32, v0 ; encoding: [0x20,0x00,0x00,0x10]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
+;
+; GFX1200-LABEL: v_mul_f32_vop2_frame_index:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+; GFX1200-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+; GFX1200-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+; GFX1200-NEXT: v_mul_f32_e32 v0, s32, v0 ; encoding: [0x20,0x00,0x00,0x10]
+; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
%alloca = alloca i32, addrspace(5)
%ptrtoint = ptrtoint ptr addrspace(5) %alloca to i32
%cast = bitcast i32 %ptrtoint to float
@@ -182,6 +259,7 @@ define float @v_mul_f32_vop2_frame_index(float %x) {
; GFX9: codeLenInByte = 20
; GFX10: codeLenInByte = 20
; GFX11: codeLenInByte = 12
+; GFX1200: codeLenInByte = 28
define float @v_fma_f32(float %x, float %y, float %z) {
; GFX9-LABEL: v_fma_f32:
@@ -201,11 +279,22 @@ define float @v_fma_f32(float %x, float %y, float %z) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf]
; GFX11-NEXT: v_fma_f32 v0, v0, v1, v2 ; encoding: [0x00,0x00,0x13,0xd6,0x00,0x03,0x0a,0x04]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
+;
+; GFX1200-LABEL: v_fma_f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+; GFX1200-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+; GFX1200-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+; GFX1200-NEXT: v_fma_f32 v0, v0, v1, v2 ; encoding: [0x00,0x00,0x13,0xd6,0x00,0x03,0x0a,0x04]
+; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
%fma = call float @llvm.fma.f32(float %x, float %y, float %z)
ret float %fma
}
-; CHECK: codeLenInByte = 16
+; NOT-GFX12: codeLenInByte = 16
+; GFX1200: codeLenInByte = 32
define float @v_fma_f32_src_mods(float %x, float %y, float %z) {
; GFX9-LABEL: v_fma_f32_src_mods:
@@ -225,12 +314,23 @@ define float @v_fma_f32_src_mods(float %x, float %y, float %z) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf]
; GFX11-NEXT: v_fma_f32 v0, |v0|, v1, v2 ; encoding: [0x00,0x01,0x13,0xd6,0x00,0x03,0x0a,0x04]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
+;
+; GFX1200-LABEL: v_fma_f32_src_mods:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+; GFX1200-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+; GFX1200-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+; GFX1200-NEXT: v_fma_f32 v0, |v0|, v1, v2 ; encoding: [0x00,0x01,0x13,0xd6,0x00,0x03,0x0a,0x04]
+; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
%fabs.x = call float @llvm.fabs.f32(float %x)
%fma = call float @llvm.fma.f32(float %fabs.x, float %y, float %z)
ret float %fma
}
-; CHECK: codeLenInByte = 16
+; NOT-GFX12: codeLenInByte = 16
+; GFX1200: codeLenInByte = 32
define float @v_fmac_f32(float %x, float %y) {
; GFX9-LABEL: v_fmac_f32:
@@ -250,6 +350,16 @@ define float @v_fmac_f32(float %x, float %y) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf]
; GFX11-NEXT: v_fmac_f32_e32 v0, v0, v1 ; encoding: [0x00,0x03,0x00,0x56]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
+;
+; GFX1200-LABEL: v_fmac_f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+; GFX1200-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+; GFX1200-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+; GFX1200-NEXT: v_fmac_f32_e32 v0, v0, v1 ; encoding: [0x00,0x03,0x00,0x56]
+; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
%fma = call float @llvm.fma.f32(float %x, float %y, float %x)
ret float %fma
}
@@ -257,6 +367,7 @@ define float @v_fmac_f32(float %x, float %y) {
; GFX9: codeLenInByte = 16
; GFX10: codeLenInByte = 12
; GFX11: codeLenInByte = 12
+; GFX1200: codeLenInByte = 28
define float @v_fmaak_f32(float %x, float %y) {
; GFX9-LABEL: v_fmaak_f32:
@@ -277,6 +388,16 @@ define float @v_fmaak_f32(float %x, float %y) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf]
; GFX11-NEXT: v_fmaak_f32 v0, v0, v1, 0x43800000 ; encoding: [0x00,0x03,0x00,0x5a,0x00,0x00,0x80,0x43]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
+;
+; GFX1200-LABEL: v_fmaak_f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+; GFX1200-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+; GFX1200-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+; GFX1200-NEXT: v_fmaak_f32 v0, v0, v1, 0x43800000 ; encoding: [0x00,0x03,0x00,0x5a,0x00,0x00,0x80,0x43]
+; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
%fma = call float @llvm.fma.f32(float %x, float %y, float 256.0)
ret float %fma
}
@@ -284,6 +405,7 @@ define float @v_fmaak_f32(float %x, float %y) {
; GFX9: codeLenInByte = 24
; GFX10: codeLenInByte = 16
; GFX11: codeLenInByte = 16
+; GFX1200: codeLenInByte = 32
define float @v_fma_k_f32_src_mods(float %x, float %y) {
; GFX9-LABEL: v_fma_k_f32_src_mods:
@@ -304,6 +426,16 @@ define float @v_fma_k_f32_src_mods(float %x, float %y) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf]
; GFX11-NEXT: v_fma_f32 v0, |v0|, v1, 0x43800000 ; encoding: [0x00,0x01,0x13,0xd6,0x00,0x03,0xfe,0x03,0x00,0x00,0x80,0x43]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
+;
+; GFX1200-LABEL: v_fma_k_f32_src_mods:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+; GFX1200-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+; GFX1200-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+; GFX1200-NEXT: v_fma_f32 v0, |v0|, v1, 0x43800000 ; encoding: [0x00,0x01,0x13,0xd6,0x00,0x03,0xfe,0x03,0x00,0x00,0x80,0x43]
+; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
%fabs.x = call float @llvm.fabs.f32(float %x)
%fma = call float @llvm.fma.f32(float %fabs.x, float %y, float 256.0)
ret float %fma
@@ -312,6 +444,7 @@ define float @v_fma_k_f32_src_mods(float %x, float %y) {
; GFX9: codeLenInByte = 24
; GFX10: codeLenInByte = 20
; GFX11: codeLenInByte = 20
+; GFX1200: codeLenInByte = 36
define amdgpu_ps float @s_fmaak_f32(float inreg %x, float inreg %y) {
; GFX9-LABEL: s_fmaak_f32:
@@ -340,6 +473,13 @@ define amdgpu_ps float @s_fmaak_f32(float inreg %x, float inreg %y) {
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_3) ; encoding: [0x0b,0x00,0x87,0xbf]
; GFX1150-NEXT: v_mov_b32_e32 v0, s0 ; encoding: [0x00,0x02,0x00,0x7e]
; GFX1150-NEXT: ; return to shader part epilog
+;
+; GFX1200-LABEL: s_fmaak_f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_fmaak_f32 s0, s0, s1, 0x43800000 ; encoding: [0x00,0x01,0x80,0xa2,0x00,0x00,0x80,0x43]
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_3) ; encoding: [0x0b,0x00,0x87,0xbf]
+; GFX1200-NEXT: v_mov_b32_e32 v0, s0 ; encoding: [0x00,0x02,0x00,0x7e]
+; GFX1200-NEXT: ; return to shader part epilog
%fma = call float @llvm.fma.f32(float %x, float %y, float 256.0)
ret float %fma
}
@@ -348,3 +488,4 @@ define amdgpu_ps float @s_fmaak_f32(float inreg %x, float inreg %y) {
; GFX10: codeLenInByte = 12
; GFX1100: codeLenInByte = 16
; GFX1150: codeLenInByte = 16
+; GFX1200: codeLenInByte = 16
diff --git a/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll b/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
index 96ec90b1f4d07..13640b74a7937 100644
--- a/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
+++ b/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
@@ -2,6 +2,8 @@
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10-MESA %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-PAL %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-MESA %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX1200-PAL %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX1200-MESA %s
; Check EXTRA_LDS_SIZE in SPI_SHADER_PGM_RSRC2_PS.
@@ -15,6 +17,11 @@
; GFX11-MESA: .long 45100
; GFX11-MESA-NEXT: .long 1024
+; GFX1200-PAL: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x400
+
+; GFX1200-MESA: .long 45100
+; GFX1200-MESA-NEXT: .long 1024
+
@lds = internal addrspace(3) global [4096 x i8] undef
define amdgpu_ps void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
index 3dea5cb5c1423..9f093cc7b5abf 100644
--- a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+++ b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
@@ -20,6 +20,9 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX1200,GFX1200-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX1200,GFX1200-GISEL %s
+
; Test for integer mad formation for patterns used in clpeak
define i32 @clpeak_imad_pat_i32(i32 %x, i32 %y) {
@@ -176,6 +179,44 @@ define i32 @clpeak_imad_pat_i32(i32 %x, i32 %y) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_mul_lo_u32 v0, v1, v0
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_i32:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, v2, v0
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[1:2], null, v0, v2, v[0:1]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v1, v0, v[1:2]
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_i32:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, v2, v0
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%y18 = add i32 %x, 1
%add = mul i32 %y18, %y
@@ -333,6 +374,43 @@ define signext i16 @clpeak_imad_pat_i16(i16 signext %x, i16 signext %y) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_i16:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v1, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_i16:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v2, v1, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v1, v2, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v1, v1, 1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%conv33 = add i16 %x, 1
%add = mul i16 %conv33, %y
@@ -510,6 +588,24 @@ define <2 x i16> @clpeak_imad_pat_v2i16(<2 x i16> %x, <2 x i16> %y) {
; GFX11-NEXT: v_pk_mul_lo_u16 v0, v3, v0
; GFX11-NEXT: v_pk_mul_lo_u16 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: clpeak_imad_pat_v2i16:
+; GFX1200: ; %bb.0: ; %entry
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_pk_mad_u16 v2, v0, v1, v0
+; GFX1200-NEXT: v_pk_mad_u16 v0, v0, v1, 1 op_sel_hi:[1,1,0]
+; GFX1200-NEXT: v_pk_mul_lo_u16 v3, v2, v1
+; GFX1200-NEXT: v_pk_mad_u16 v1, v2, v1, 1 op_sel_hi:[1,1,0]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_pk_mul_lo_u16 v0, v3, v0
+; GFX1200-NEXT: v_pk_mul_lo_u16 v0, v0, v1
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
entry:
%y18 = add <2 x i16> %x, <i16 1, i16 1>
%add = mul <2 x i16> %y18, %y
@@ -805,6 +901,60 @@ define <3 x i16> @clpeak_imad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) {
; GFX11-GISEL-NEXT: v_pk_mul_lo_u16 v0, v0, v2
; GFX11-GISEL-NEXT: v_pk_mul_lo_u16 v1, v1, v3
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_v3i16:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX1200-SDAG-NEXT: v_pk_add_u16 v1, v1, 1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v4, v0, v2, v0
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v5, v1, v3, v1
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v6, v4, v2
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v7, v5, v3
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v1, v7, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v0, v0, v2
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v1, v1, v3
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_v3i16:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX1200-GISEL-NEXT: v_pk_add_u16 v1, v1, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v4, v0, v2, v0
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v5, v1, v3, v1
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v1, v1, v3, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v6, v4, v2
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v7, v5, v3
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v3, v5, v3, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v0, v6, v0
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v1, v7, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v0, v0, v2
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v1, v1, v3
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%y48 = add <3 x i16> %x, <i16 1, i16 1, i16 1>
%add = mul <3 x i16> %y48, %y
@@ -1186,6 +1336,60 @@ define <4 x i16> @clpeak_imad_pat_v4i16(<4 x i16> %x, <4 x i16> %y) {
; GFX11-GISEL-NEXT: v_pk_mul_lo_u16 v0, v0, v2
; GFX11-GISEL-NEXT: v_pk_mul_lo_u16 v1, v1, v3
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_v4i16:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX1200-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v4, v0, v2, v0
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v5, v1, v3, v1
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v6, v4, v2
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v7, v5, v3
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 op_sel_hi:[1,1,0]
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v1, v7, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v0, v0, v2
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v1, v1, v3
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_v4i16:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX1200-GISEL-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v4, v0, v2, v0
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v5, v1, v3, v1
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v6, v4, v2
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v7, v5, v3
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v3, v5, v3, 1 op_sel_hi:[1,1,0]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v0, v6, v0
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v1, v7, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v0, v0, v2
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v1, v1, v3
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%y18 = add <4 x i16> %x, <i16 1, i16 1, i16 1, i16 1>
%add = mul <4 x i16> %y18, %y
@@ -1337,6 +1541,43 @@ define zeroext i16 @clpeak_umad_pat_i16(i16 zeroext %x, i16 zeroext %y) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_umad_pat_i16:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v1, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_umad_pat_i16:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v2, v1, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v1, v2, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v1, v1, 1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%conv33 = add i16 %x, 1
%add = mul i16 %conv33, %y
@@ -1514,6 +1755,24 @@ define <2 x i16> @clpeak_umad_pat_v2i16(<2 x i16> %x, <2 x i16> %y) {
; GFX11-NEXT: v_pk_mul_lo_u16 v0, v3, v0
; GFX11-NEXT: v_pk_mul_lo_u16 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: clpeak_umad_pat_v2i16:
+; GFX1200: ; %bb.0: ; %entry
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_pk_mad_u16 v2, v0, v1, v0
+; GFX1200-NEXT: v_pk_mad_u16 v0, v0, v1, 1 op_sel_hi:[1,1,0]
+; GFX1200-NEXT: v_pk_mul_lo_u16 v3, v2, v1
+; GFX1200-NEXT: v_pk_mad_u16 v1, v2, v1, 1 op_sel_hi:[1,1,0]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_pk_mul_lo_u16 v0, v3, v0
+; GFX1200-NEXT: v_pk_mul_lo_u16 v0, v0, v1
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
entry:
%y18 = add <2 x i16> %x, <i16 1, i16 1>
%add = mul <2 x i16> %y18, %y
@@ -1809,6 +2068,60 @@ define <3 x i16> @clpeak_umad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) {
; GFX11-GISEL-NEXT: v_pk_mul_lo_u16 v0, v0, v2
; GFX11-GISEL-NEXT: v_pk_mul_lo_u16 v1, v1, v3
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_umad_pat_v3i16:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX1200-SDAG-NEXT: v_pk_add_u16 v1, v1, 1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v4, v0, v2, v0
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v5, v1, v3, v1
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v6, v4, v2
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v7, v5, v3
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v1, v7, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v0, v0, v2
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v1, v1, v3
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_umad_pat_v3i16:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX1200-GISEL-NEXT: v_pk_add_u16 v1, v1, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v4, v0, v2, v0
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v5, v1, v3, v1
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v1, v1, v3, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v6, v4, v2
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v7, v5, v3
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v3, v5, v3, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v0, v6, v0
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v1, v7, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v0, v0, v2
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v1, v1, v3
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%y48 = add <3 x i16> %x, <i16 1, i16 1, i16 1>
%add = mul <3 x i16> %y48, %y
@@ -2190,6 +2503,60 @@ define <4 x i16> @clpeak_umad_pat_v4i16(<4 x i16> %x, <4 x i16> %y) {
; GFX11-GISEL-NEXT: v_pk_mul_lo_u16 v0, v0, v2
; GFX11-GISEL-NEXT: v_pk_mul_lo_u16 v1, v1, v3
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_umad_pat_v4i16:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX1200-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v4, v0, v2, v0
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v5, v1, v3, v1
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v6, v4, v2
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v7, v5, v3
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 op_sel_hi:[1,1,0]
+; GFX1200-SDAG-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v1, v7, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v0, v0, v2
+; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v1, v1, v3
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_umad_pat_v4i16:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX1200-GISEL-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v4, v0, v2, v0
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v5, v1, v3, v1
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v6, v4, v2
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v7, v5, v3
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0]
+; GFX1200-GISEL-NEXT: v_pk_mad_u16 v3, v5, v3, 1 op_sel_hi:[1,1,0]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v0, v6, v0
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v1, v7, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v0, v0, v2
+; GFX1200-GISEL-NEXT: v_pk_mul_lo_u16 v1, v1, v3
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%y18 = add <4 x i16> %x, <i16 1, i16 1, i16 1, i16 1>
%add = mul <4 x i16> %y18, %y
@@ -2449,6 +2816,62 @@ define <2 x i32> @clpeak_imad_pat_v2i32(<2 x i32> %x, <2 x i32> %y) {
; GFX11-GISEL-NEXT: v_mul_lo_u32 v0, v2, v0
; GFX11-GISEL-NEXT: v_mul_lo_u32 v1, v3, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_v2i32:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v4, v0, v2
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v5, v1, v3
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, v4, v0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v1, v5, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v0, v0, v2
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v1, v3
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[3:4], null, v0, v4, v[0:1]
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[4:5], null, v2, v5, v[2:3]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v3, v0, v[3:4]
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[1:2], null, v4, v2, v[4:5]
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_v2i32:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v4, v0, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v5, v1, v3
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, v4, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, v5, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v0, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v1, v3
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v2, 1, v4
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v3, 1, v5
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v0, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v2, v0
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v3, v1
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%y18 = add <2 x i32> %x, <i32 1, i32 1>
%add = mul <2 x i32> %y18, %y
@@ -2802,6 +3225,82 @@ define <3 x i32> @clpeak_imad_pat_v3i32(<3 x i32> %x, <3 x i32> %y) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_mul_lo_u32 v2, v5, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_v3i32:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v2, 1, v2
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v6, v0, v3
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v7, v1, v4
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v8, v2, v5
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, v6, v0
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v1, v7, v1
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v9, v8, v2
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v0, v0, v3
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v1, v4
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v3, v9, v5
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[4:5], null, v0, v6, v[0:1]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[5:6], null, v2, v7, v[2:3]
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[6:7], null, v3, v8, v[3:4]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v4, v0, v[4:5]
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[1:2], null, v5, v2, v[5:6]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[2:3], null, v6, v3, v[6:7]
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_v3i32:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v2, 1, v2
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v6, v0, v3
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v7, v1, v4
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v8, v2, v5
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, v6, v0
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, v7, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v2, v8, v2
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v0, v3
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v1, v4
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v2, v5
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v3, 1, v6
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v4, 1, v7
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v5, 1, v8
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v3, v0, v3
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v4, v1, v4
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v5, v2, v5
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v2, 1, v2
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v3, v0
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v4, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v5, v2
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%y48 = add <3 x i32> %x, <i32 1, i32 1, i32 1>
%add = mul <3 x i32> %y48, %y
@@ -3209,6 +3708,97 @@ define <4 x i32> @clpeak_imad_pat_v4i32(<4 x i32> %x, <4 x i32> %y) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_mul_lo_u32 v3, v6, v3
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_v4i32:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v2, 1, v2
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v3, 1, v3
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v8, v0, v4
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v9, v1, v5
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v10, v2, v6
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v11, v3, v7
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, v8, v0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v1, v9, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v12, v10, v2
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v0, v0, v4
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v4, v11, v3
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v1, v5
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v3, v12, v6
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v4, v4, v7
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[5:6], null, v0, v8, v[0:1]
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[6:7], null, v2, v9, v[2:3]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[7:8], null, v3, v10, v[3:4]
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[8:9], null, v4, v11, v[4:5]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v5, v0, v[5:6]
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[1:2], null, v6, v2, v[6:7]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[2:3], null, v7, v3, v[7:8]
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[3:4], null, v8, v4, v[8:9]
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_v4i32:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v2, 1, v2
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v3, 1, v3
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v8, v0, v4
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v9, v1, v5
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v10, v2, v6
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v11, v3, v7
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, v8, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, v9, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v2, v10, v2
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v3, v11, v3
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v0, v4
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v1, v5
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v2, v6
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v3, v3, v7
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v4, 1, v8
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v5, 1, v9
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v6, 1, v10
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v7, 1, v11
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v8, 1, v0
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v0, v4
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v4, v1, v5
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v5, v2, v6
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v6, v3, v7
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v2, 1, v2
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v3, 1, v3
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v0, v8
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v4, v1
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v5, v2
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v3, v6, v3
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%y18 = add <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
%add = mul <4 x i32> %y18, %y
@@ -3399,6 +3989,48 @@ define i32 @clpeak_imad_pat_i24(i32 %x, i32 %y) {
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
; GFX11-GISEL-NEXT: v_mul_lo_u32 v0, v1, v0
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_i24:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GFX1200-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 24
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v1, v0
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, v2, v0
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[1:2], null, v0, v2, v[0:1]
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v1, v0, v[1:2]
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_i24:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GFX1200-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 24
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v1, v0
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, v2, v0
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v2
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%shl = shl i32 %x, 8
%shr = ashr exact i32 %shl, 8
@@ -3593,6 +4225,48 @@ define i32 @clpeak_imad_pat_u24(i32 %x, i32 %y) {
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
; GFX11-GISEL-NEXT: v_mul_lo_u32 v0, v1, v0
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_u24:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX1200-SDAG-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v1, v0
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, v2, v0
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[1:2], null, v0, v2, v[0:1]
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v1, v0, v[1:2]
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_u24:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX1200-GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v1, v0
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, v2, v0
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v2
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%shl = and i32 %x, 16777215
%shl1 = and i32 %y, 16777215
@@ -3752,6 +4426,43 @@ define signext i8 @clpeak_imad_pat_i8(i8 signext %x, i8 signext %y) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_i8:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v1, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_i8:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v2, v1, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v1, v2, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v1, v1, 1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%conv33 = add i8 %x, 1
%add = mul i8 %conv33, %y
@@ -4013,6 +4724,68 @@ define <2 x i8> @clpeak_imad_pat_v2i8(<2 x i8> %x, <2 x i8> %y) {
; GFX11-GISEL-NEXT: v_mul_lo_u16 v0, v0, v4
; GFX11-GISEL-NEXT: v_mul_lo_u16 v1, v1, v5
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_v2i8:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_add_nc_u16 v1, v1, 1
+; GFX1200-SDAG-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mad_u16 v4, v1, v3, v1
+; GFX1200-SDAG-NEXT: v_mad_u16 v5, v0, v2, v0
+; GFX1200-SDAG-NEXT: v_mul_lo_u16 v1, v1, v3
+; GFX1200-SDAG-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_mul_lo_u16 v3, v4, v3
+; GFX1200-SDAG-NEXT: v_mul_lo_u16 v2, v5, v2
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mad_u16 v1, v3, v1, v3
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v2, v0, v2
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mad_u16 v1, v1, v3, v1
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v0, v2, v0
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_lshlrev_b16 v2, 8, v1
+; GFX1200-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX1200-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_v2i8:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v1, v1, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v4, v0, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v5, v1, v3
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v4, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v1, v5, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v1, v1, v3
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v2, v4, 1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v3, v5, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v4, v0, 1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v5, v1, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v1, v1, v3
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v4
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v1, v1, v5
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%y18 = add <2 x i8> %x, <i8 1, i8 1>
%add = mul <2 x i8> %y18, %y
@@ -4436,6 +5209,86 @@ define i64 @clpeak_imad_pat_i64(i64 %x, i64 %y) {
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[6:7], null, v3, v10, v[1:2]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v5, v9, v[6:7]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_i64:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_add_co_u32 v4, vcc_lo, v0, 1
+; GFX1200-SDAG-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v7, v4, v3
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v4, v2, 0
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v6, v5, v2
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_add_co_u32 v4, vcc_lo, v0, v4
+; GFX1200-SDAG-NEXT: v_add3_u32 v1, v1, v7, v6
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v6, v4, v3
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[3:4], null, v4, v2, 0
+; GFX1200-SDAG-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v5, vcc_lo
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v5, v2
+; GFX1200-SDAG-NEXT: v_add3_u32 v4, v4, v6, v2
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v3, v1
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v5, v4, v0
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v3, v0, v[3:4]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_add3_u32 v1, v5, v1, v2
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v0, v4
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v4, v1, v3
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v0, v3, v[0:1]
+; GFX1200-SDAG-NEXT: v_add3_u32 v1, v4, v1, v2
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_i64:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v0, 1
+; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_hi_u32 v0, v4, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v6, v4, v2
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[0:1], null, v4, v3, v[0:1]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v6, v4
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[0:1], null, v5, v2, v[0:1]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_mov_b32_e32 v7, v0
+; GFX1200-GISEL-NEXT: v_mul_hi_u32 v0, v4, v2
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v7, v5, vcc_lo
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[0:1], null, v4, v3, v[0:1]
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v3, v4, v2
+; GFX1200-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v6, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[0:1], null, v5, v2, v[0:1]
+; GFX1200-GISEL-NEXT: v_mul_hi_u32 v1, v3, v4
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v5, v3, v4
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_mov_b32_e32 v6, v0
+; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v7, vcc_lo
+; GFX1200-GISEL-NEXT: v_add_co_u32 v7, vcc_lo, v3, 1
+; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[1:2], null, v3, v2, v[1:2]
+; GFX1200-GISEL-NEXT: v_mul_hi_u32 v2, v5, v7
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[3:4], null, v0, v4, v[1:2]
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v5, v7
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[1:2], null, v5, v6, v[2:3]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[1:2], null, v3, v7, v[1:2]
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%y18 = add i64 %x, 1
%add = mul i64 %y18, %y
@@ -5202,6 +6055,140 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, v5
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_v2i64:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_add_co_u32 v8, vcc_lo, v0, 1
+; GFX1200-SDAG-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
+; GFX1200-SDAG-NEXT: v_add_co_u32 v10, vcc_lo, v2, 1
+; GFX1200-SDAG-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, 0, v3, vcc_lo
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v12, v9, v4
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v13, v8, v5
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v8, v4, 0
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v14, v11, v6
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v15, v10, v7
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[2:3], null, v10, v6, 0
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_add3_u32 v12, v1, v13, v12
+; GFX1200-SDAG-NEXT: v_add_co_u32 v1, vcc_lo, v0, v8
+; GFX1200-SDAG-NEXT: v_add3_u32 v13, v3, v15, v14
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v12, v9, vcc_lo
+; GFX1200-SDAG-NEXT: v_add_co_u32 v8, vcc_lo, v2, v10
+; GFX1200-SDAG-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v13, v11, vcc_lo
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v10, v3, v4
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v11, v1, v5
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v7, v8, v7
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v9, v9, v6
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[5:6], null, v8, v6, 0
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[3:4], null, v1, v4, 0
+; GFX1200-SDAG-NEXT: v_add3_u32 v6, v6, v7, v9
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_add3_u32 v4, v4, v11, v10
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v11, v3, v12
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v9, v6, v2
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[7:8], null, v5, v2, v[5:6]
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v10, v4, v0
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v3, v0, v[3:4]
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v5, v13
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v6, v7, v6
+; GFX1200-SDAG-NEXT: v_add3_u32 v1, v10, v1, v11
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v4, v0, v4
+; GFX1200-SDAG-NEXT: v_add3_u32 v8, v9, v8, v2
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v9, v1, v3
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v0, v3, v[0:1]
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v10, v8, v5
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[2:3], null, v7, v5, v[7:8]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_add3_u32 v1, v9, v1, v4
+; GFX1200-SDAG-NEXT: v_add3_u32 v3, v10, v3, v6
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_v2i64:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_co_u32 v8, vcc_lo, v0, 1
+; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
+; GFX1200-GISEL-NEXT: v_add_co_u32 v10, vcc_lo, v2, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_mul_hi_u32 v0, v8, v4
+; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, 0, v3, vcc_lo
+; GFX1200-GISEL-NEXT: v_mul_hi_u32 v1, v10, v6
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v12, v8, v4
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v13, v10, v6
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[2:3], null, v8, v5, v[0:1]
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[0:1], null, v10, v7, v[1:2]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[1:2], null, v9, v4, v[2:3]
+; GFX1200-GISEL-NEXT: v_mov_b32_e32 v14, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[2:3], null, v11, v6, v[0:1]
+; GFX1200-GISEL-NEXT: v_add_co_u32 v3, vcc_lo, v12, v8
+; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v14, v9, vcc_lo
+; GFX1200-GISEL-NEXT: v_add_co_u32 v10, vcc_lo, v13, v10
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_mul_hi_u32 v0, v3, v4
+; GFX1200-GISEL-NEXT: v_mov_b32_e32 v8, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v15, v3, v4
+; GFX1200-GISEL-NEXT: v_mul_hi_u32 v1, v10, v6
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v16, v10, v6
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v8, v11, vcc_lo
+; GFX1200-GISEL-NEXT: v_add_co_u32 v12, vcc_lo, v12, 1
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[2:3], null, v3, v5, v[0:1]
+; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v14, vcc_lo
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[0:1], null, v10, v7, v[1:2]
+; GFX1200-GISEL-NEXT: v_mul_hi_u32 v1, v15, v12
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[2:3], null, v9, v4, v[2:3]
+; GFX1200-GISEL-NEXT: v_add_co_u32 v9, vcc_lo, v13, 1
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[3:4], null, v11, v6, v[0:1]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[4:5], null, v15, v5, v[1:2]
+; GFX1200-GISEL-NEXT: v_mov_b32_e32 v1, v2
+; GFX1200-GISEL-NEXT: v_mul_hi_u32 v0, v16, v9
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v14, v16, v9
+; GFX1200-GISEL-NEXT: v_mov_b32_e32 v11, v3
+; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v8, v15, v12
+; GFX1200-GISEL-NEXT: v_add_co_u32 v10, vcc_lo, v15, 1
+; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, 0, v1, vcc_lo
+; GFX1200-GISEL-NEXT: v_add_co_u32 v15, vcc_lo, v16, 1
+; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_hi_u32 v1, v8, v10
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[5:6], null, v16, v7, v[0:1]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_hi_u32 v0, v14, v15
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[6:7], null, v2, v12, v[4:5]
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[1:2], null, v8, v13, v[1:2]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[3:4], null, v3, v9, v[5:6]
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[4:5], null, v14, v11, v[0:1]
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[1:2], null, v6, v10, v[1:2]
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v8, v10
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v14, v15
+; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[3:4], null, v3, v15, v[4:5]
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%y18 = add <2 x i64> %x, <i64 1, i64 1>
%add = mul <2 x i64> %y18, %y
@@ -5434,6 +6421,31 @@ define i32 @v_multi_use_mul_chain_add_other_use_all(i32 %arg, i32 %arg1, i32 %ar
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_add_nc_u32_e32 v0, v5, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: v_multi_use_mul_chain_add_other_use_all:
+; GFX1200: ; %bb.0: ; %bb
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX1200-NEXT: v_add_nc_u32_e32 v0, v2, v0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_mul_lo_u32 v1, v0, v1
+; GFX1200-NEXT: v_add_nc_u32_e32 v0, 1, v2
+; GFX1200-NEXT: v_mul_lo_u32 v5, v1, v0
+; GFX1200-NEXT: s_wait_storecnt 0x0
+; GFX1200-NEXT: global_store_b32 v[3:4], v2, off scope:SCOPE_SYS
+; GFX1200-NEXT: s_wait_storecnt 0x0
+; GFX1200-NEXT: global_store_b32 v[3:4], v1, off scope:SCOPE_SYS
+; GFX1200-NEXT: s_wait_storecnt 0x0
+; GFX1200-NEXT: global_store_b32 v[3:4], v5, off scope:SCOPE_SYS
+; GFX1200-NEXT: s_wait_storecnt 0x0
+; GFX1200-NEXT: v_add_nc_u32_e32 v0, v5, v0
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
bb:
%i = add i32 %arg, 1
%i3 = mul i32 %i, %arg1
@@ -5644,6 +6656,29 @@ define i32 @v_multi_use_mul_chain_add_other_use_some(i32 %arg, i32 %arg1, i32 %a
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_add_nc_u32_e32 v0, v5, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: v_multi_use_mul_chain_add_other_use_some:
+; GFX1200: ; %bb.0: ; %bb
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX1200-NEXT: v_add_nc_u32_e32 v0, v2, v0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX1200-NEXT: v_add_nc_u32_e32 v1, 1, v2
+; GFX1200-NEXT: v_mul_lo_u32 v5, v0, v1
+; GFX1200-NEXT: s_wait_storecnt 0x0
+; GFX1200-NEXT: global_store_b32 v[3:4], v2, off scope:SCOPE_SYS
+; GFX1200-NEXT: s_wait_storecnt 0x0
+; GFX1200-NEXT: global_store_b32 v[3:4], v5, off scope:SCOPE_SYS
+; GFX1200-NEXT: s_wait_storecnt 0x0
+; GFX1200-NEXT: v_add_nc_u32_e32 v0, v5, v1
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
bb:
%i = add i32 %arg, 1
%i3 = mul i32 %i, %arg1
@@ -5913,6 +6948,66 @@ define i32 @clpeak_imad_pat_i32_x2(i32 %x, i32 %y) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_mul_lo_u32 v0, v1, v0
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_i32_x2:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, v2, v0
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v1, 1, v2
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v1, v2, v1
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v1, 1, v2
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v1, v2, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[1:2], null, v0, v2, v[0:1]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v1, v0, v[1:2]
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_i32_x2:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, v2, v0
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, v2, v1
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v2
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, v2, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%y38 = add i32 %x, 1
%add = mul i32 %y38, %y
@@ -6384,6 +7479,106 @@ define <2 x i32> @clpeak_imad_pat_v2i32_x2(<2 x i32> %x, <2 x i32> %y) {
; GFX11-GISEL-NEXT: v_mul_lo_u32 v0, v2, v0
; GFX11-GISEL-NEXT: v_mul_lo_u32 v1, v3, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_v2i32_x2:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v4, v0, v2
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v5, v1, v3
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v0, v4, v0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v1, v5, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v0, v0, v2
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v2, 1, v4
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v1, v1, v3
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v3, 1, v5
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v4, v0, v2
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v5, v1, v3
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v2, v4, v2
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v3, v5, v3
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v0, v2, v0
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v2, 1, v4
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v1, v3, v1
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v3, 1, v5
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v4, v0, v2
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v5, v1, v3
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v2, v4, v2
+; GFX1200-SDAG-NEXT: v_add_nc_u32_e32 v3, v5, v3
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v0, v2, v0
+; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v3, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[3:4], null, v0, v4, v[0:1]
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[4:5], null, v2, v5, v[2:3]
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v3, v0, v[3:4]
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[1:2], null, v4, v2, v[4:5]
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_v2i32_x2:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v4, v0, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v5, v1, v3
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, v4, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, v5, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v0, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v1, v3
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v2, 1, v4
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v3, 1, v5
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v4, v0, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v5, v1, v3
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v2, v4, v2
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v3, v5, v3
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v2, v0
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v3, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v2, 1, v4
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v3, 1, v5
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v4, v0, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v5, v1, v3
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v2, v4, v2
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v3, v5, v3
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v2, v0
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v3, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v2, 1, v4
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v3, 1, v5
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v2, v0, v2
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v0, v2, v0
+; GFX1200-GISEL-NEXT: v_mul_lo_u32 v1, v3, v1
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%y38 = add <2 x i32> %x, <i32 1, i32 1>
%add = mul <2 x i32> %y38, %y
@@ -6633,6 +7828,59 @@ define signext i16 @clpeak_imad_pat_i16_x2(i16 signext %x, i16 signext %y) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_imad_pat_i16_x2:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v1, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v1, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v1, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_imad_pat_i16_x2:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v2, v1, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v1, v2, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v1, v1, 1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v1, v1, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v1, v1, 1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v1, v1, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v1, v1, 1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%conv69 = add i16 %x, 1
%add = mul i16 %conv69, %y
@@ -6876,6 +8124,59 @@ define zeroext i16 @clpeak_umad_pat_i16_x2(i16 zeroext %x, i16 zeroext %y) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: clpeak_umad_pat_i16_x2:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v1, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v1, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v1, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v1, v0, v1
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v0, v1, v0
+; GFX1200-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: clpeak_umad_pat_i16_x2:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v2, v1, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v1, v2, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v1, v1, 1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v1, v1, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v1, v1, 1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v1, v1, v0
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, 1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v1, v1, 1
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%conv69 = add i16 %x, 1
%add = mul i16 %conv69, %y
@@ -7173,6 +8474,32 @@ define <2 x i16> @clpeak_imad_pat_v2i16_x2(<2 x i16> %x, <2 x i16> %y) {
; GFX11-NEXT: v_pk_mul_lo_u16 v0, v3, v0
; GFX11-NEXT: v_pk_mul_lo_u16 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: clpeak_imad_pat_v2i16_x2:
+; GFX1200: ; %bb.0: ; %entry
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_pk_mad_u16 v2, v0, v1, v0
+; GFX1200-NEXT: v_pk_mad_u16 v0, v0, v1, 1 op_sel_hi:[1,1,0]
+; GFX1200-NEXT: v_pk_mul_lo_u16 v1, v2, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_pk_mad_u16 v2, v1, v0, v0
+; GFX1200-NEXT: v_pk_mad_u16 v0, v1, v0, 1 op_sel_hi:[1,1,0]
+; GFX1200-NEXT: v_pk_mul_lo_u16 v1, v2, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_pk_mad_u16 v2, v1, v0, v0
+; GFX1200-NEXT: v_pk_mad_u16 v0, v1, v0, 1 op_sel_hi:[1,1,0]
+; GFX1200-NEXT: v_pk_mul_lo_u16 v3, v2, v1
+; GFX1200-NEXT: v_pk_mad_u16 v1, v2, v1, 1 op_sel_hi:[1,1,0]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_pk_mul_lo_u16 v0, v3, v0
+; GFX1200-NEXT: v_pk_mul_lo_u16 v0, v0, v1
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
entry:
%y38 = add <2 x i16> %x, <i16 1, i16 1>
%add = mul <2 x i16> %y38, %y
@@ -7470,6 +8797,32 @@ define <2 x i16> @clpeak_umad_pat_v2i16_x2(<2 x i16> %x, <2 x i16> %y) {
; GFX11-NEXT: v_pk_mul_lo_u16 v0, v3, v0
; GFX11-NEXT: v_pk_mul_lo_u16 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: clpeak_umad_pat_v2i16_x2:
+; GFX1200: ; %bb.0: ; %entry
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_pk_mad_u16 v2, v0, v1, v0
+; GFX1200-NEXT: v_pk_mad_u16 v0, v0, v1, 1 op_sel_hi:[1,1,0]
+; GFX1200-NEXT: v_pk_mul_lo_u16 v1, v2, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_pk_mad_u16 v2, v1, v0, v0
+; GFX1200-NEXT: v_pk_mad_u16 v0, v1, v0, 1 op_sel_hi:[1,1,0]
+; GFX1200-NEXT: v_pk_mul_lo_u16 v1, v2, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_pk_mad_u16 v2, v1, v0, v0
+; GFX1200-NEXT: v_pk_mad_u16 v0, v1, v0, 1 op_sel_hi:[1,1,0]
+; GFX1200-NEXT: v_pk_mul_lo_u16 v3, v2, v1
+; GFX1200-NEXT: v_pk_mad_u16 v1, v2, v1, 1 op_sel_hi:[1,1,0]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_pk_mul_lo_u16 v0, v3, v0
+; GFX1200-NEXT: v_pk_mul_lo_u16 v0, v0, v1
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
entry:
%y38 = add <2 x i16> %x, <i16 1, i16 1>
%add = mul <2 x i16> %y38, %y
@@ -7532,6 +8885,19 @@ define <2 x i32> @multi_use_mul_mad_i32_var(i32 %x, i32 %y, i32 %z0, i32 %z1) {
; GFX11-NEXT: v_add_nc_u32_e32 v0, v1, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, v1, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: multi_use_mul_mad_i32_var:
+; GFX1200: ; %bb.0: ; %entry
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_mul_lo_u32 v1, v0, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v0, v1, v2
+; GFX1200-NEXT: v_add_nc_u32_e32 v1, v1, v3
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
entry:
%mul = mul i32 %x, %y
%add0 = add i32 %mul, %z0
@@ -7634,6 +9000,35 @@ define <2 x i16> @multi_use_mul_mad_i16_var(i16 %x, i16 %y, i16 %z0, i16 %z1) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: multi_use_mul_mad_i16_var:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_mad_u16 v2, v0, v1, v2
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v0, v1, v3
+; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-SDAG-NEXT: v_perm_b32 v0, v0, v2, 0x5040100
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: multi_use_mul_mad_i16_var:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v1, v0, v2
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v0, v3
+; GFX1200-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%mul = mul i16 %x, %y
%add0 = add i16 %mul, %z0
@@ -7691,6 +9086,20 @@ define i32 @other_use_mul_mad_i32_var(i32 %x, i32 %y, i32 %z, ptr addrspace(3) %
; GFX11-NEXT: ds_store_b32 v3, v1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: other_use_mul_mad_i32_var:
+; GFX1200: ; %bb.0: ; %entry
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_mul_lo_u32 v1, v0, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v0, v1, v2
+; GFX1200-NEXT: ds_store_b32 v3, v1
+; GFX1200-NEXT: s_wait_dscnt 0x0
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
entry:
%mul = mul i32 %x, %y
%add0 = add i32 %mul, %z
@@ -7778,6 +9187,33 @@ define i16 @other_use_mul_mad_i16_var(i16 %x, i16 %y, i16 %z, ptr addrspace(3) %
; GFX11-GISEL-NEXT: ds_store_b16 v3, v1
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: other_use_mul_mad_i16_var:
+; GFX1200-SDAG: ; %bb.0: ; %entry
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_mul_lo_u16 v4, v0, v1
+; GFX1200-SDAG-NEXT: v_mad_u16 v0, v0, v1, v2
+; GFX1200-SDAG-NEXT: ds_store_b16 v3, v4
+; GFX1200-SDAG-NEXT: s_wait_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: other_use_mul_mad_i16_var:
+; GFX1200-GISEL: ; %bb.0: ; %entry
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_mul_lo_u16 v1, v0, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-GISEL-NEXT: v_add_nc_u16 v0, v1, v2
+; GFX1200-GISEL-NEXT: ds_store_b16 v3, v1
+; GFX1200-GISEL-NEXT: s_wait_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%mul = mul i16 %x, %y
%add0 = add i16 %mul, %z
@@ -7882,6 +9318,19 @@ define <4 x i16> @multi_use_mul_mad_v2i16_var(<2 x i16> %x, <2 x i16> %y, <2 x i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_mov_b32_e32 v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: multi_use_mul_mad_v2i16_var:
+; GFX1200: ; %bb.0: ; %entry
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_pk_mad_u16 v2, v0, v1, v2
+; GFX1200-NEXT: v_pk_mad_u16 v1, v0, v1, v3
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_mov_b32_e32 v0, v2
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
entry:
%mul = mul <2 x i16> %x, %y
%add0 = add <2 x i16> %mul, %z0
@@ -7996,6 +9445,19 @@ define <2 x i16> @other_use_mul_mad_v2i16_var(<2 x i16> %x, <2 x i16> %y, <2 x i
; GFX11-NEXT: ds_store_b32 v3, v4
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: other_use_mul_mad_v2i16_var:
+; GFX1200: ; %bb.0: ; %entry
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_pk_mul_lo_u16 v4, v0, v1
+; GFX1200-NEXT: v_pk_mad_u16 v0, v0, v1, v2
+; GFX1200-NEXT: ds_store_b32 v3, v4
+; GFX1200-NEXT: s_wait_dscnt 0x0
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
entry:
%mul = mul <2 x i16> %x, %y
%add0 = add <2 x i16> %mul, %z
@@ -8069,6 +9531,30 @@ define i64 @mul_u24_add64(i32 %x, i32 %y, i64 %z) {
; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v4, v2
; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-SDAG-LABEL: mul_u24_add64:
+; GFX1200-SDAG: ; %bb.0:
+; GFX1200-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[0:1], null, v0, v1, v[2:3]
+; GFX1200-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-GISEL-LABEL: mul_u24_add64:
+; GFX1200-GISEL: ; %bb.0:
+; GFX1200-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1200-GISEL-NEXT: v_mul_u32_u24_e32 v4, v0, v1
+; GFX1200-GISEL-NEXT: v_mul_hi_u32_u24_e32 v1, v0, v1
+; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v4, v2
+; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX1200-GISEL-NEXT: s_setpc_b64 s[30:31]
%mul = call i64 @llvm.amdgcn.mul.u24.i64(i32 %x, i32 %y)
%add = add i64 %mul, %z
ret i64 %add
@@ -8115,6 +9601,19 @@ define i64 @mul_u24_zext_add64(i32 %x, i32 %y, i64 %z) {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: mul_u24_zext_add64:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_mul_u32_u24_e32 v0, v0, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX1200-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
%mul = call i32 @llvm.amdgcn.mul.u24(i32 %x, i32 %y)
%mul.zext = zext i32 %mul to i64
%add = add i64 %mul.zext, %z
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