[llvm] [LSV] Enhance LoadStoreVectorizer to Handle Disjoint Flag in OR Instructions and Restore Vectorization Opportunities (PR #96495)

[Hao Li via llvm-commits]

LiHao217 wrote:

> A new phase-ordering test has been added to demonstrate that without this patch, OR instructions lacking the disjoint flag were not vectorized under -O1, -O2, and -O3 optimization levels. With the patch applied, SCEV successfully flags the OR instructions as disjoint, allowing LSV to vectorize them, as confirmed by the test.

Hi @arsenm @nikic @dtcxzyw ,

Thank your for your review and feedback.  I have updated my patch and added a new test case: llvm/test/Transforms/PhaseOrdering/disjoint_or_vectorizer.ll.  This test case illustrates that prior to applying my patch, OR instructions in the IR were not flagged as disjoint at the -O1, -O2, and -O3 optimization levels.

I have also refined the implementation based on our discussion.  The detection of or disjoint has now been moved from the LoadStoreVectorizer (LSV) to the Scalar Evolution (SCEV) analysis.  This change provides a more appropriate and robust handling of OR instructions with the disjoint flag within the existing LLVM infrastructure.

The new patch ensures that OR instructions marked as disjoint are identified early in the optimization process during SCEV analysis, paving the way for proper vectorization in subsequent stages.

I believe this addresses the previous concerns and should make the vectorization logic more consistent.  Could you please take another look at the updated patch and the added test case?  Your feedback is greatly appreciated.

Best regards,
Hao LI



https://github.com/llvm/llvm-project/pull/96495