[llvm] [RISCV] Add groupid/bitmask for RISC-V extension (PR #94440)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 27 05:49:05 PDT 2024
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/94440
>From 0d4af6e2f351b7e4e94d9fabbcee6ad49d6647a2 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 01/27] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.
This patch defines the groupid/bitmask in RISCVFeatures.td and generates the corresponding table in RISCVTargetParserDef.inc.
The groupid/bitmask of extensions provides an abstraction layer between the compiler and runtime functions.
---
.../llvm/TargetParser/RISCVTargetParser.h | 8 ++
llvm/lib/Target/RISCV/RISCVFeatures.td | 105 ++++++++++++++++++
llvm/lib/TargetParser/RISCVTargetParser.cpp | 32 ++++++
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 39 +++++++
4 files changed, 184 insertions(+)
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 5b1494efe7bdc..24755dcfec52a 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -24,6 +24,14 @@ class Triple;
namespace RISCV {
+namespace RISCVExtensionBitmaskTable {
+struct RISCVExtensionBitmask {
+ const char *Name;
+ unsigned GroupID;
+ unsigned long long Bitmask;
+};
+} // namespace RISCVExtensionBitmaskTable
+
// We use 64 bits as the known part in the scalable vector types.
static constexpr unsigned RVVBitsPerBlock = 64;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 9bf06850483d8..bfaa7b1a1b99b 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -37,6 +37,13 @@ class RISCVExtension<string name, int major, int minor, string desc,
bit Experimental = false;
}
+// TODO: Maybe integrate into RISCVExtension class
+class RISCVExtensionBitmask<string name, bits<3> groupID, int bitmaskShift> {
+ string Name = name;
+ bits<3> GroupID = groupID;
+ bits<64> Bitmask = !shl(1, bitmaskShift);
+}
+
// Version of RISCVExtension to be used for Experimental extensions. This
// sets the Experimental flag and prepends experimental- to the -mattr name.
class RISCVExperimentalExtension<string name, int major, int minor, string desc,
@@ -53,18 +60,22 @@ class RISCVExperimentalExtension<string name, int major, int minor, string desc,
def FeatureStdExtI
: RISCVExtension<"i", 2, 1,
"'I' (Base Integer Instruction Set)">;
+def : RISCVExtensionBitmask<"i", 0, 0>;
def FeatureStdExtE
: RISCVExtension<"e", 2, 0,
"Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
+def : RISCVExtensionBitmask<"e", 0, 1>;
def FeatureStdExtZic64b
: RISCVExtension<"zic64b", 1, 0,
"'Zic64b' (Cache Block Size Is 64 Bytes)">;
+def : RISCVExtensionBitmask<"zic64b", 0, 2>;
def FeatureStdExtZicbom
: RISCVExtension<"zicbom", 1, 0,
"'Zicbom' (Cache-Block Management Instructions)">;
+def : RISCVExtensionBitmask<"zicbom", 0, 3>;
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
AssemblerPredicate<(all_of FeatureStdExtZicbom),
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -72,6 +83,7 @@ def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
def FeatureStdExtZicbop
: RISCVExtension<"zicbop", 1, 0,
"'Zicbop' (Cache-Block Prefetch Instructions)">;
+def : RISCVExtensionBitmask<"zicbop", 0, 4>;
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
@@ -79,6 +91,7 @@ def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
def FeatureStdExtZicboz
: RISCVExtension<"zicboz", 1, 0,
"'Zicboz' (Cache-Block Zero Instructions)">;
+def : RISCVExtensionBitmask<"zicboz", 0, 5>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
@@ -86,22 +99,27 @@ def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
def FeatureStdExtZiccamoa
: RISCVExtension<"ziccamoa", 1, 0,
"'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+def : RISCVExtensionBitmask<"ziccamoa", 0, 6>;
def FeatureStdExtZiccif
: RISCVExtension<"ziccif", 1, 0,
"'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
+def : RISCVExtensionBitmask<"ziccif", 0, 7>;
def FeatureStdExtZicclsm
: RISCVExtension<"zicclsm", 1, 0,
"'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
+def : RISCVExtensionBitmask<"zicclsm", 0, 8>;
def FeatureStdExtZiccrse
: RISCVExtension<"ziccrse", 1, 0,
"'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
+def : RISCVExtensionBitmask<"ziccrse", 0, 9>;
def FeatureStdExtZicsr
: RISCVExtension<"zicsr", 2, 0,
"'zicsr' (CSRs)">;
+def : RISCVExtensionBitmask<"zicsr", 0, 10>;
def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
@@ -110,10 +128,12 @@ def FeatureStdExtZicntr
: RISCVExtension<"zicntr", 2, 0,
"'Zicntr' (Base Counters and Timers)",
[FeatureStdExtZicsr]>;
+def : RISCVExtensionBitmask<"zicntr", 0, 11>;
def FeatureStdExtZicond
: RISCVExtension<"zicond", 1, 0,
"'Zicond' (Integer Conditional Operations)">;
+def : RISCVExtensionBitmask<"zicond", 0, 12>;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
@@ -121,6 +141,7 @@ def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
def FeatureStdExtZifencei
: RISCVExtension<"zifencei", 2, 0,
"'Zifencei' (fence.i)">;
+def : RISCVExtensionBitmask<"zifencei", 0, 13>;
def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
@@ -128,6 +149,7 @@ def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
def FeatureStdExtZihintpause
: RISCVExtension<"zihintpause", 2, 0,
"'Zihintpause' (Pause Hint)">;
+def : RISCVExtensionBitmask<"zihintpause", 0, 14>;
def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
AssemblerPredicate<(all_of FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
@@ -135,6 +157,7 @@ def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
def FeatureStdExtZihintntl
: RISCVExtension<"zihintntl", 1, 0,
"'Zihintntl' (Non-Temporal Locality Hints)">;
+def : RISCVExtensionBitmask<"zihintntl", 0, 15>;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -143,9 +166,11 @@ def FeatureStdExtZihpm
: RISCVExtension<"zihpm", 2, 0,
"'Zihpm' (Hardware Performance Counters)",
[FeatureStdExtZicsr]>;
+def : RISCVExtensionBitmask<"zihpm", 0, 16>;
def FeatureStdExtZimop : RISCVExtension<"zimop", 1, 0,
"'Zimop' (May-Be-Operations)">;
+def : RISCVExtensionBitmask<"zimop", 0, 17>;
def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
@@ -154,6 +179,7 @@ def FeatureStdExtZicfilp
: RISCVExperimentalExtension<"zicfilp", 0, 4,
"'Zicfilp' (Landing pad)",
[FeatureStdExtZicsr]>;
+def : RISCVExtensionBitmask<"zicfilp", 0, 18>;
def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
AssemblerPredicate<(all_of FeatureStdExtZicfilp),
"'Zicfilp' (Landing pad)">;
@@ -164,6 +190,7 @@ def FeatureStdExtZicfiss
: RISCVExperimentalExtension<"zicfiss", 0, 4,
"'Zicfiss' (Shadow stack)",
[FeatureStdExtZicsr, FeatureStdExtZimop]>;
+def : RISCVExtensionBitmask<"zicfiss", 0, 19>;
def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
AssemblerPredicate<(all_of FeatureStdExtZicfiss),
"'Zicfiss' (Shadow stack)">;
@@ -174,6 +201,7 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
def FeatureStdExtM
: RISCVExtension<"m", 2, 0,
"'M' (Integer Multiplication and Division)">;
+def : RISCVExtensionBitmask<"m", 0, 20>;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;
@@ -181,6 +209,7 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
def FeatureStdExtZmmul
: RISCVExtension<"zmmul", 1, 0,
"'Zmmul' (Integer Multiplication)">;
+def : RISCVExtensionBitmask<"zmmul", 0, 21>;
def HasStdExtMOrZmmul
: Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
@@ -193,6 +222,7 @@ def HasStdExtMOrZmmul
def FeatureStdExtA
: RISCVExtension<"a", 2, 1,
"'A' (Atomic Instructions)">;
+def : RISCVExtensionBitmask<"a", 0, 22>;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<(all_of FeatureStdExtA),
"'A' (Atomic Instructions)">;
@@ -200,6 +230,7 @@ def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
def FeatureStdExtZtso
: RISCVExperimentalExtension<"ztso", 0, 1,
"'Ztso' (Memory Model - Total Store Order)">;
+def : RISCVExtensionBitmask<"ztso", 0, 23>;
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
@@ -207,13 +238,16 @@ def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
def FeatureStdExtZa64rs : RISCVExtension<"za64rs", 1, 0,
"'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
+def : RISCVExtensionBitmask<"za64rs", 0, 24>;
def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
"'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
+def : RISCVExtensionBitmask<"za128rs", 0, 25>;
def FeatureStdExtZaamo
: RISCVExtension<"zaamo", 1, 0,
"'Zaamo' (Atomic Memory Operations)">;
+def : RISCVExtensionBitmask<"zaamo", 0, 26>;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -223,6 +257,7 @@ def HasStdExtAOrZaamo
def FeatureStdExtZabha
: RISCVExtension<"zabha", 1, 0,
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
+def : RISCVExtensionBitmask<"zabha", 0, 27>;
def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
AssemblerPredicate<(all_of FeatureStdExtZabha),
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
@@ -230,6 +265,7 @@ def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
def FeatureStdExtZacas
: RISCVExtension<"zacas", 1, 0,
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
+def : RISCVExtensionBitmask<"zacas", 0, 28>;
def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
AssemblerPredicate<(all_of FeatureStdExtZacas),
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
@@ -238,6 +274,7 @@ def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
def FeatureStdExtZalasr
: RISCVExperimentalExtension<"zalasr", 0, 1,
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
+def : RISCVExtensionBitmask<"zalasr", 0, 29>;
def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
AssemblerPredicate<(all_of FeatureStdExtZalasr),
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
@@ -245,6 +282,7 @@ def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
def FeatureStdExtZalrsc
: RISCVExtension<"zalrsc", 1, 0,
"'Zalrsc' (Load-Reserved/Store-Conditional)">;
+def : RISCVExtensionBitmask<"zalrsc", 0, 30>;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
@@ -254,9 +292,11 @@ def HasStdExtAOrZalrsc
def FeatureStdExtZama16b
: RISCVExtension<"zama16b", 1, 0,
"'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">;
+def : RISCVExtensionBitmask<"zama16b", 0, 31>;
def FeatureStdExtZawrs : RISCVExtension<"zawrs", 1, 0,
"'Zawrs' (Wait on Reservation Set)">;
+def : RISCVExtensionBitmask<"zawrs", 0, 32>;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
AssemblerPredicate<(all_of FeatureStdExtZawrs),
"'Zawrs' (Wait on Reservation Set)">;
@@ -267,6 +307,7 @@ def FeatureStdExtF
: RISCVExtension<"f", 2, 2,
"'F' (Single-Precision Floating-Point)",
[FeatureStdExtZicsr]>;
+def : RISCVExtensionBitmask<"f", 0, 33>;
def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
AssemblerPredicate<(all_of FeatureStdExtF),
"'F' (Single-Precision Floating-Point)">;
@@ -275,6 +316,7 @@ def FeatureStdExtD
: RISCVExtension<"d", 2, 2,
"'D' (Double-Precision Floating-Point)",
[FeatureStdExtF]>;
+def : RISCVExtensionBitmask<"d", 0, 34>;
def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
AssemblerPredicate<(all_of FeatureStdExtD),
"'D' (Double-Precision Floating-Point)">;
@@ -283,6 +325,7 @@ def FeatureStdExtZfhmin
: RISCVExtension<"zfhmin", 1, 0,
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
[FeatureStdExtF]>;
+def : RISCVExtensionBitmask<"zfhmin", 0, 35>;
def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfhmin),
"'Zfh' (Half-Precision Floating-Point) or "
@@ -292,6 +335,7 @@ def FeatureStdExtZfh
: RISCVExtension<"zfh", 1, 0,
"'Zfh' (Half-Precision Floating-Point)",
[FeatureStdExtZfhmin]>;
+def : RISCVExtensionBitmask<"zfh", 0, 36>;
def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
AssemblerPredicate<(all_of FeatureStdExtZfh),
"'Zfh' (Half-Precision Floating-Point)">;
@@ -301,6 +345,7 @@ def FeatureStdExtZfbfmin
: RISCVExperimentalExtension<"zfbfmin", 1, 0,
"'Zfbfmin' (Scalar BF16 Converts)",
[FeatureStdExtF]>;
+def : RISCVExtensionBitmask<"zfbfmin", 0, 37>;
def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
"'Zfbfmin' (Scalar BF16 Converts)">;
@@ -317,6 +362,7 @@ def FeatureStdExtZfa
: RISCVExtension<"zfa", 1, 0,
"'Zfa' (Additional Floating-Point)",
[FeatureStdExtF]>;
+def : RISCVExtensionBitmask<"zfa", 0, 38>;
def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
AssemblerPredicate<(all_of FeatureStdExtZfa),
"'Zfa' (Additional Floating-Point)">;
@@ -325,6 +371,7 @@ def FeatureStdExtZfinx
: RISCVExtension<"zfinx", 1, 0,
"'Zfinx' (Float in Integer)",
[FeatureStdExtZicsr]>;
+def : RISCVExtensionBitmask<"zfinx", 0, 39>;
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
AssemblerPredicate<(all_of FeatureStdExtZfinx),
"'Zfinx' (Float in Integer)">;
@@ -333,6 +380,7 @@ def FeatureStdExtZdinx
: RISCVExtension<"zdinx", 1, 0,
"'Zdinx' (Double in Integer)",
[FeatureStdExtZfinx]>;
+def : RISCVExtensionBitmask<"zdinx", 0, 40>;
def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
AssemblerPredicate<(all_of FeatureStdExtZdinx),
"'Zdinx' (Double in Integer)">;
@@ -341,6 +389,7 @@ def FeatureStdExtZhinxmin
: RISCVExtension<"zhinxmin", 1, 0,
"'Zhinxmin' (Half Float in Integer Minimal)",
[FeatureStdExtZfinx]>;
+def : RISCVExtensionBitmask<"zhinxmin", 0, 41>;
def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
"'Zhinx' (Half Float in Integer) or "
@@ -350,6 +399,7 @@ def FeatureStdExtZhinx
: RISCVExtension<"zhinx", 1, 0,
"'Zhinx' (Half Float in Integer)",
[FeatureStdExtZhinxmin]>;
+def : RISCVExtensionBitmask<"zhinx", 0, 42>;
def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
AssemblerPredicate<(all_of FeatureStdExtZhinx),
"'Zhinx' (Half Float in Integer)">;
@@ -360,6 +410,7 @@ def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
def FeatureStdExtC
: RISCVExtension<"c", 2, 0,
"'C' (Compressed Instructions)">;
+def : RISCVExtensionBitmask<"c", 0, 43>;
def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtC),
"'C' (Compressed Instructions)">;
@@ -375,6 +426,7 @@ def FeatureStdExtZca
: RISCVExtension<"zca", 1, 0,
"'Zca' (part of the C extension, excluding compressed "
"floating point loads/stores)">;
+def : RISCVExtensionBitmask<"zca", 0, 44>;
def HasStdExtCOrZca
: Predicate<"Subtarget->hasStdExtCOrZca()">,
@@ -387,6 +439,7 @@ def FeatureStdExtZcb
: RISCVExtension<"zcb", 1, 0,
"'Zcb' (Compressed basic bit manipulation instructions)",
[FeatureStdExtZca]>;
+def : RISCVExtensionBitmask<"zcb", 0, 45>;
def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
AssemblerPredicate<(all_of FeatureStdExtZcb),
"'Zcb' (Compressed basic bit manipulation instructions)">;
@@ -395,6 +448,7 @@ def FeatureStdExtZcd
: RISCVExtension<"zcd", 1, 0,
"'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
[FeatureStdExtD, FeatureStdExtZca]>;
+def : RISCVExtensionBitmask<"zcd", 0, 46>;
def HasStdExtCOrZcd
: Predicate<"Subtarget->hasStdExtCOrZcd()">,
@@ -406,11 +460,13 @@ def FeatureStdExtZcf
: RISCVExtension<"zcf", 1, 0,
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
[FeatureStdExtF, FeatureStdExtZca]>;
+def : RISCVExtensionBitmask<"zcf", 0, 47>;
def FeatureStdExtZcmp
: RISCVExtension<"zcmp", 1, 0,
"'Zcmp' (sequenced instuctions for code-size reduction)",
[FeatureStdExtZca]>;
+def : RISCVExtensionBitmask<"zcmp", 0, 48>;
def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtZcmp),
"'Zcmp' (sequenced instuctions for code-size reduction)">;
@@ -419,6 +475,7 @@ def FeatureStdExtZcmt
: RISCVExtension<"zcmt", 1, 0,
"'Zcmt' (table jump instuctions for code-size reduction)",
[FeatureStdExtZca, FeatureStdExtZicsr]>;
+def : RISCVExtensionBitmask<"zcmt", 0, 49>;
def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
AssemblerPredicate<(all_of FeatureStdExtZcmt),
"'Zcmt' (table jump instuctions for code-size reduction)">;
@@ -427,6 +484,7 @@ def FeatureStdExtZce
: RISCVExtension<"zce", 1, 0,
"'Zce' (Compressed extensions for microcontrollers)",
[FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>;
+def : RISCVExtensionBitmask<"zce", 0, 50>;
def HasStdExtCOrZcfOrZce
: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
@@ -440,6 +498,7 @@ def FeatureStdExtZcmop
: RISCVExtension<"zcmop", 1, 0,
"'Zcmop' (Compressed May-Be-Operations)",
[FeatureStdExtZca]>;
+def : RISCVExtensionBitmask<"zcmop", 0, 51>;
def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
AssemblerPredicate<(all_of FeatureStdExtZcmop),
"'Zcmop' (Compressed May-Be-Operations)">;
@@ -449,6 +508,7 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
def FeatureStdExtZba
: RISCVExtension<"zba", 1, 0,
"'Zba' (Address Generation Instructions)">;
+def : RISCVExtensionBitmask<"zba", 0, 52>;
def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
AssemblerPredicate<(all_of FeatureStdExtZba),
"'Zba' (Address Generation Instructions)">;
@@ -457,6 +517,7 @@ def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
def FeatureStdExtZbb
: RISCVExtension<"zbb", 1, 0,
"'Zbb' (Basic Bit-Manipulation)">;
+def : RISCVExtensionBitmask<"zbb", 0, 53>;
def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
AssemblerPredicate<(all_of FeatureStdExtZbb),
"'Zbb' (Basic Bit-Manipulation)">;
@@ -464,6 +525,7 @@ def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
def FeatureStdExtZbc
: RISCVExtension<"zbc", 1, 0,
"'Zbc' (Carry-Less Multiplication)">;
+def : RISCVExtensionBitmask<"zbc", 0, 54>;
def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
AssemblerPredicate<(all_of FeatureStdExtZbc),
"'Zbc' (Carry-Less Multiplication)">;
@@ -471,6 +533,7 @@ def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
def FeatureStdExtZbs
: RISCVExtension<"zbs", 1, 0,
"'Zbs' (Single-Bit Instructions)">;
+def : RISCVExtensionBitmask<"zbs", 0, 55>;
def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
AssemblerPredicate<(all_of FeatureStdExtZbs),
"'Zbs' (Single-Bit Instructions)">;
@@ -480,6 +543,7 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
def FeatureStdExtZbkb
: RISCVExtension<"zbkb", 1, 0,
"'Zbkb' (Bitmanip instructions for Cryptography)">;
+def : RISCVExtensionBitmask<"zbkb", 0, 56>;
def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
AssemblerPredicate<(all_of FeatureStdExtZbkb),
"'Zbkb' (Bitmanip instructions for Cryptography)">;
@@ -487,6 +551,7 @@ def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
def FeatureStdExtZbkx
: RISCVExtension<"zbkx", 1, 0,
"'Zbkx' (Crossbar permutation instructions)">;
+def : RISCVExtensionBitmask<"zbkx", 0, 57>;
def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
AssemblerPredicate<(all_of FeatureStdExtZbkx),
"'Zbkx' (Crossbar permutation instructions)">;
@@ -504,6 +569,7 @@ def FeatureStdExtZbkc
: RISCVExtension<"zbkc", 1, 0,
"'Zbkc' (Carry-less multiply instructions for "
"Cryptography)">;
+def : RISCVExtensionBitmask<"zbkc", 0, 58>;
def HasStdExtZbkc
: Predicate<"Subtarget->hasStdExtZbkc()">,
AssemblerPredicate<(all_of FeatureStdExtZbkc),
@@ -521,6 +587,7 @@ def HasStdExtZbcOrZbkc
def FeatureStdExtZknd
: RISCVExtension<"zknd", 1, 0,
"'Zknd' (NIST Suite: AES Decryption)">;
+def : RISCVExtensionBitmask<"zknd", 0, 59>;
def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
AssemblerPredicate<(all_of FeatureStdExtZknd),
"'Zknd' (NIST Suite: AES Decryption)">;
@@ -528,6 +595,7 @@ def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
def FeatureStdExtZkne
: RISCVExtension<"zkne", 1, 0,
"'Zkne' (NIST Suite: AES Encryption)">;
+def : RISCVExtensionBitmask<"zkne", 0, 60>;
def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
AssemblerPredicate<(all_of FeatureStdExtZkne),
"'Zkne' (NIST Suite: AES Encryption)">;
@@ -543,6 +611,7 @@ def HasStdExtZkndOrZkne
def FeatureStdExtZknh
: RISCVExtension<"zknh", 1, 0,
"'Zknh' (NIST Suite: Hash Function Instructions)">;
+def : RISCVExtensionBitmask<"zknh", 0, 61>;
def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
AssemblerPredicate<(all_of FeatureStdExtZknh),
"'Zknh' (NIST Suite: Hash Function Instructions)">;
@@ -550,6 +619,7 @@ def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
def FeatureStdExtZksed
: RISCVExtension<"zksed", 1, 0,
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
+def : RISCVExtensionBitmask<"zksed", 0, 62>;
def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
AssemblerPredicate<(all_of FeatureStdExtZksed),
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
@@ -557,6 +627,7 @@ def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
def FeatureStdExtZksh
: RISCVExtension<"zksh", 1, 0,
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
+def : RISCVExtensionBitmask<"zksh", 0, 63>;
def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
AssemblerPredicate<(all_of FeatureStdExtZksh),
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
@@ -564,6 +635,7 @@ def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
def FeatureStdExtZkr
: RISCVExtension<"zkr", 1, 0,
"'Zkr' (Entropy Source Extension)">;
+def : RISCVExtensionBitmask<"zkr", 1, 0>;
def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
AssemblerPredicate<(all_of FeatureStdExtZkr),
"'Zkr' (Entropy Source Extension)">;
@@ -577,6 +649,7 @@ def FeatureStdExtZkn
FeatureStdExtZkne,
FeatureStdExtZknd,
FeatureStdExtZknh]>;
+def : RISCVExtensionBitmask<"zkn", 1, 1>;
def FeatureStdExtZks
: RISCVExtension<"zks", 1, 0,
@@ -586,10 +659,12 @@ def FeatureStdExtZks
FeatureStdExtZbkx,
FeatureStdExtZksed,
FeatureStdExtZksh]>;
+def : RISCVExtensionBitmask<"zks", 1, 2>;
def FeatureStdExtZkt
: RISCVExtension<"zkt", 1, 0,
"'Zkt' (Data Independent Execution Latency)">;
+def : RISCVExtensionBitmask<"zkt", 1, 3>;
def FeatureStdExtZk
: RISCVExtension<"zk", 1, 0,
@@ -597,12 +672,14 @@ def FeatureStdExtZk
[FeatureStdExtZkn,
FeatureStdExtZkr,
FeatureStdExtZkt]>;
+def : RISCVExtensionBitmask<"zk", 1, 4>;
// Vector Extensions
def FeatureStdExtZvl32b : RISCVExtension<"zvl32b", 1, 0,
"'Zvl' (Minimum Vector Length) 32", [],
"ZvlLen", "32">;
+def : RISCVExtensionBitmask<"zvl32b", 1, 5>;
foreach i = { 6-16 } in {
defvar I = !shl(1, i);
@@ -611,6 +688,7 @@ foreach i = { 6-16 } in {
"'Zvl' (Minimum Vector Length) "#I,
[!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")],
"ZvlLen", !cast<string>(I)>;
+ def : RISCVExtensionBitmask<"zvl"#I#"b", 1, !add(6, !sub(i, 6))>;
}
def FeatureStdExtZve32x
@@ -618,40 +696,48 @@ def FeatureStdExtZve32x
"'Zve32x' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW)",
[FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
+def : RISCVExtensionBitmask<"zve32x", 1, 17>;
+
def FeatureStdExtZve32f
: RISCVExtension<"zve32f", 1, 0,
"'Zve32f' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW and F extension)",
[FeatureStdExtZve32x, FeatureStdExtF]>;
+def : RISCVExtensionBitmask<"zve32f", 1, 18>;
def FeatureStdExtZve64x
: RISCVExtension<"zve64x", 1, 0,
"'Zve64x' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW)",
[FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
+def : RISCVExtensionBitmask<"zve64x", 1, 19>;
def FeatureStdExtZve64f
: RISCVExtension<"zve64f", 1, 0,
"'Zve64f' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW and F extension)",
[FeatureStdExtZve32f, FeatureStdExtZve64x]>;
+def : RISCVExtensionBitmask<"zve64f", 1, 20>;
def FeatureStdExtZve64d
: RISCVExtension<"zve64d", 1, 0,
"'Zve64d' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW, F and D extension)",
[FeatureStdExtZve64f, FeatureStdExtD]>;
+def : RISCVExtensionBitmask<"zve64d", 1, 21>;
def FeatureStdExtV
: RISCVExtension<"v", 1, 0,
"'V' (Vector Extension for Application Processors)",
[FeatureStdExtZvl128b, FeatureStdExtZve64d]>;
+def : RISCVExtensionBitmask<"v", 1, 22>;
def FeatureStdExtZvfbfmin
: RISCVExperimentalExtension<"zvfbfmin", 1, 0,
"'Zvbfmin' (Vector BF16 Converts)",
[FeatureStdExtZve32f]>;
+def : RISCVExtensionBitmask<"zvfbfmin", 1, 23>;
def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
"'Zvfbfmin' (Vector BF16 Converts)">;
@@ -660,6 +746,7 @@ def FeatureStdExtZvfbfwma
: RISCVExperimentalExtension<"zvfbfwma", 1, 0,
"'Zvfbfwma' (Vector BF16 widening mul-add)",
[FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>;
+def : RISCVExtensionBitmask<"zvfbfwma", 1, 24>;
def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
"'Zvfbfwma' (Vector BF16 widening mul-add)">;
@@ -668,11 +755,13 @@ def FeatureStdExtZvfhmin
: RISCVExtension<"zvfhmin", 1, 0,
"'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
[FeatureStdExtZve32f]>;
+def : RISCVExtensionBitmask<"zvfhmin", 1, 25>;
def FeatureStdExtZvfh
: RISCVExtension<"zvfh", 1, 0,
"'Zvfh' (Vector Half-Precision Floating-Point)",
[FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>;
+def : RISCVExtensionBitmask<"zvfh", 1, 26>;
def HasStdExtZfhOrZvfh
: Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
@@ -685,6 +774,7 @@ def HasStdExtZfhOrZvfh
def FeatureStdExtZvkb
: RISCVExtension<"zvkb", 1, 0,
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
+def : RISCVExtensionBitmask<"zvkb", 1, 27>;
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
AssemblerPredicate<(all_of FeatureStdExtZvkb),
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
@@ -693,6 +783,7 @@ def FeatureStdExtZvbb
: RISCVExtension<"zvbb", 1, 0,
"'Zvbb' (Vector basic bit-manipulation instructions)",
[FeatureStdExtZvkb]>;
+def : RISCVExtensionBitmask<"zvbb", 1, 28>;
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
AssemblerPredicate<(all_of FeatureStdExtZvbb),
"'Zvbb' (Vector basic bit-manipulation instructions)">;
@@ -700,6 +791,7 @@ def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
def FeatureStdExtZvbc
: RISCVExtension<"zvbc", 1, 0,
"'Zvbc' (Vector Carryless Multiplication)">;
+def : RISCVExtensionBitmask<"zvbc", 1, 29>;
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
AssemblerPredicate<(all_of FeatureStdExtZvbc),
"'Zvbc' (Vector Carryless Multiplication)">;
@@ -707,6 +799,7 @@ def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
def FeatureStdExtZvkg
: RISCVExtension<"zvkg", 1, 0,
"'Zvkg' (Vector GCM instructions for Cryptography)">;
+def : RISCVExtensionBitmask<"zvkg", 1, 30>;
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
AssemblerPredicate<(all_of FeatureStdExtZvkg),
"'Zvkg' (Vector GCM instructions for Cryptography)">;
@@ -714,6 +807,7 @@ def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
def FeatureStdExtZvkned
: RISCVExtension<"zvkned", 1, 0,
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
+def : RISCVExtensionBitmask<"zvkned", 1, 31>;
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
AssemblerPredicate<(all_of FeatureStdExtZvkned),
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
@@ -721,6 +815,7 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
def FeatureStdExtZvknha
: RISCVExtension<"zvknha", 1, 0,
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
+def : RISCVExtensionBitmask<"zvknha", 1, 32>;
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
AssemblerPredicate<(all_of FeatureStdExtZvknha),
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
@@ -729,6 +824,7 @@ def FeatureStdExtZvknhb
: RISCVExtension<"zvknhb", 1, 0,
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
[FeatureStdExtZve64x]>;
+def : RISCVExtensionBitmask<"zvknhb", 1, 33>;
def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
AssemblerPredicate<(all_of FeatureStdExtZvknhb),
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;
@@ -740,6 +836,7 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg
def FeatureStdExtZvksed
: RISCVExtension<"zvksed", 1, 0,
"'Zvksed' (SM4 Block Cipher Instructions)">;
+def : RISCVExtensionBitmask<"zvksed", 1, 34>;
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
AssemblerPredicate<(all_of FeatureStdExtZvksed),
"'Zvksed' (SM4 Block Cipher Instructions)">;
@@ -747,6 +844,7 @@ def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
def FeatureStdExtZvksh
: RISCVExtension<"zvksh", 1, 0,
"'Zvksh' (SM3 Hash Function Instructions)">;
+def : RISCVExtensionBitmask<"zvksh", 1, 35>;
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
AssemblerPredicate<(all_of FeatureStdExtZvksh),
"'Zvksh' (SM3 Hash Function Instructions)">;
@@ -754,6 +852,7 @@ def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
def FeatureStdExtZvkt
: RISCVExtension<"zvkt", 1, 0,
"'Zvkt' (Vector Data-Independent Execution Latency)">;
+def : RISCVExtensionBitmask<"zvkt", 1, 36>;
// Zvk short-hand extensions
@@ -763,16 +862,19 @@ def FeatureStdExtZvkn
"'Zvkt')",
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
+def : RISCVExtensionBitmask<"zvkn", 1, 37>;
def FeatureStdExtZvknc
: RISCVExtension<"zvknc", 1, 0,
"'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')",
[FeatureStdExtZvkn, FeatureStdExtZvbc]>;
+def : RISCVExtensionBitmask<"zvknc", 1, 38>;
def FeatureStdExtZvkng
: RISCVExtension<"zvkng", 1, 0,
"'zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
[FeatureStdExtZvkn, FeatureStdExtZvkg]>;
+def : RISCVExtensionBitmask<"zvkng", 1, 39>;
def FeatureStdExtZvks
: RISCVExtension<"zvks", 1, 0,
@@ -780,16 +882,19 @@ def FeatureStdExtZvks
"'Zvkt')",
[FeatureStdExtZvksed, FeatureStdExtZvksh,
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
+def : RISCVExtensionBitmask<"zvks", 1, 40>;
def FeatureStdExtZvksc
: RISCVExtension<"zvksc", 1, 0,
"'Zvksc' (shorthand for 'Zvks' and 'Zvbc')",
[FeatureStdExtZvks, FeatureStdExtZvbc]>;
+def : RISCVExtensionBitmask<"zvksc", 1, 41>;
def FeatureStdExtZvksg
: RISCVExtension<"zvksg", 1, 0,
"'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
[FeatureStdExtZvks, FeatureStdExtZvkg]>;
+def : RISCVExtensionBitmask<"zvksg", 1, 42>;
// Vector instruction predicates
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 9003f9beffa7e..ec6447a44f90d 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -119,6 +119,38 @@ void getFeaturesForCPU(StringRef CPU,
else
EnabledFeatures.push_back(F.substr(1));
}
+
+namespace RISCVExtensionBitmaskTable {
+#define GET_RISCVExtensionBitmaskTable_IMPL
+#include "llvm/TargetParser/RISCVTargetParserDef.inc"
+
+} // namespace RISCVExtensionBitmaskTable
+
+namespace {
+struct LessExtName {
+ bool operator()(const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &LHS,
+ StringRef RHS) {
+ return StringRef(LHS.Name) < RHS;
+ }
+ bool
+ operator()(StringRef LHS,
+ const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &RHS) {
+ return LHS < StringRef(RHS.Name);
+ }
+};
+} // namespace
+
+static RISCVExtensionBitmaskTable::RISCVExtensionBitmask
+getExtensionBitmask(StringRef ExtName) {
+ ArrayRef<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmasks =
+ ArrayRef(RISCVExtensionBitmaskTable::ExtensionBitmask);
+ auto *I = llvm::lower_bound(ExtBitmasks, ExtName, LessExtName());
+
+ if (I != ExtBitmasks.end())
+ return *I;
+
+ return RISCVExtensionBitmaskTable::RISCVExtensionBitmask();
+}
} // namespace RISCV
namespace RISCVVType {
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index b76ba05954aa5..0c02ca626f91a 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -210,10 +210,49 @@ static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) {
OS << "\n#undef TUNE_PROC\n";
}
+static inline uint64_t getValueFromBitsInit(const BitsInit *B,
+ const Record &R) {
+ assert(B->getNumBits() <= sizeof(uint64_t) * 8 && "BitInits' too long!");
+
+ uint64_t Value = 0;
+ for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
+ const auto *Bit = dyn_cast<BitInit>(B->getBit(i));
+ if (Bit)
+ Value |= uint64_t(Bit->getValue()) << i;
+ }
+ return Value;
+}
+
+static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
+
+ std::vector<Record *> Extensions =
+ RK.getAllDerivedDefinitionsIfDefined("RISCVExtensionBitmask");
+ llvm::sort(Extensions, [](const Record *Rec1, const Record *Rec2) {
+ return getExtensionName(Rec1) < getExtensionName(Rec2);
+ });
+
+ OS << "#ifdef GET_RISCVExtensionBitmaskTable_IMPL\n";
+ OS << "static const RISCVExtensionBitmask ExtensionBitmask[]={\n";
+ for (const Record *Rec : Extensions) {
+ BitsInit *GroupIDBits = Rec->getValueAsBitsInit("GroupID");
+ BitsInit *BitmaskBits = Rec->getValueAsBitsInit("Bitmask");
+
+ assert(GroupIDBits);
+ assert(BitmaskBits);
+
+ OS << " {" << "\"" << Rec->getValueAsString("Name") << "\"" << ", "
+ << getValueFromBitsInit(GroupIDBits, *Rec) << ", "
+ << getValueFromBitsInit(BitmaskBits, *Rec) << "ULL" << "},\n";
+ }
+ OS << "};\n";
+ OS << "#endif\n";
+}
+
static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
emitRISCVExtensions(RK, OS);
emitRISCVProfiles(RK, OS);
emitRISCVProcs(RK, OS);
+ emitRISCVExtensionBitmask(RK, OS);
}
static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef,
>From 08b3e913017853f81763bdac7c13d8dca954aeb8 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 5 Jun 2024 01:42:36 -0700
Subject: [PATCH 02/27] Fixup format issue
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 0c02ca626f91a..4b6677c6b3d63 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -240,9 +240,11 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
assert(GroupIDBits);
assert(BitmaskBits);
- OS << " {" << "\"" << Rec->getValueAsString("Name") << "\"" << ", "
- << getValueFromBitsInit(GroupIDBits, *Rec) << ", "
- << getValueFromBitsInit(BitmaskBits, *Rec) << "ULL" << "},\n";
+ OS << " {"
+ << "\"" << Rec->getValueAsString("Name") << "\""
+ << ", " << getValueFromBitsInit(GroupIDBits, *Rec) << ", "
+ << getValueFromBitsInit(BitmaskBits, *Rec) << "ULL"
+ << "},\n";
}
OS << "};\n";
OS << "#endif\n";
>From 80ff9b64a44db3717b472238d53a9391377f60e6 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 5 Jun 2024 03:14:24 -0700
Subject: [PATCH 03/27] Use RISCVExtension to contain the bitmask info
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 307 ++++++------------
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 6 +-
2 files changed, 109 insertions(+), 204 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index bfaa7b1a1b99b..9b0cd3b6bb200 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -25,7 +25,7 @@
class RISCVExtension<string name, int major, int minor, string desc,
list<SubtargetFeature> implies = [],
string fieldname = !subst("Feature", "Has", NAME),
- string value = "true">
+ string value = "true", bits<3> groupID=0, int bitmaskShift=-1>
: SubtargetFeature<name, fieldname, value, desc, implies> {
// MajorVersion - The major version for this extension.
int MajorVersion = major;
@@ -35,13 +35,11 @@ class RISCVExtension<string name, int major, int minor, string desc,
// Experimental - Does extension require -menable-experimental-extensions.
bit Experimental = false;
-}
-// TODO: Maybe integrate into RISCVExtension class
-class RISCVExtensionBitmask<string name, bits<3> groupID, int bitmaskShift> {
- string Name = name;
- bits<3> GroupID = groupID;
- bits<64> Bitmask = !shl(1, bitmaskShift);
+ // For Bitmask table
+ string Name = !subst("experimental-", "", name);
+ bits<3> GroupID = groupID;
+ bits<64> Bitmask = !if(!eq(bitmaskShift, -1), 0, !shl(1, bitmaskShift));
}
// Version of RISCVExtension to be used for Experimental extensions. This
@@ -49,9 +47,9 @@ class RISCVExtensionBitmask<string name, bits<3> groupID, int bitmaskShift> {
class RISCVExperimentalExtension<string name, int major, int minor, string desc,
list<RISCVExtension> implies = [],
string fieldname = !subst("Feature", "Has", NAME),
- string value = "true">
+ string value = "true", bits<3> groupID=0, int bitmaskShift=-1>
: RISCVExtension<"experimental-"#name, major, minor, desc, implies,
- fieldname, value> {
+ fieldname, value, groupID, bitmaskShift> {
let Experimental = true;
}
@@ -59,67 +57,56 @@ class RISCVExperimentalExtension<string name, int major, int minor, string desc,
def FeatureStdExtI
: RISCVExtension<"i", 2, 1,
- "'I' (Base Integer Instruction Set)">;
-def : RISCVExtensionBitmask<"i", 0, 0>;
+ "'I' (Base Integer Instruction Set)", groupID=0, bitmaskShift=0>;
def FeatureStdExtE
: RISCVExtension<"e", 2, 0,
- "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
-def : RISCVExtensionBitmask<"e", 0, 1>;
+ "Implements RV{32,64}E (provides 16 rather than 32 GPRs)", groupID=0, bitmaskShift=1>;
def FeatureStdExtZic64b
: RISCVExtension<"zic64b", 1, 0,
- "'Zic64b' (Cache Block Size Is 64 Bytes)">;
-def : RISCVExtensionBitmask<"zic64b", 0, 2>;
+ "'Zic64b' (Cache Block Size Is 64 Bytes)", groupID=0, bitmaskShift=2>;
def FeatureStdExtZicbom
: RISCVExtension<"zicbom", 1, 0,
- "'Zicbom' (Cache-Block Management Instructions)">;
-def : RISCVExtensionBitmask<"zicbom", 0, 3>;
+ "'Zicbom' (Cache-Block Management Instructions)", groupID=0, bitmaskShift=3>;
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
AssemblerPredicate<(all_of FeatureStdExtZicbom),
"'Zicbom' (Cache-Block Management Instructions)">;
def FeatureStdExtZicbop
: RISCVExtension<"zicbop", 1, 0,
- "'Zicbop' (Cache-Block Prefetch Instructions)">;
-def : RISCVExtensionBitmask<"zicbop", 0, 4>;
+ "'Zicbop' (Cache-Block Prefetch Instructions)", groupID=0, bitmaskShift=4>;
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
def FeatureStdExtZicboz
: RISCVExtension<"zicboz", 1, 0,
- "'Zicboz' (Cache-Block Zero Instructions)">;
-def : RISCVExtensionBitmask<"zicboz", 0, 5>;
+ "'Zicboz' (Cache-Block Zero Instructions)", groupID=0, bitmaskShift=5>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
def FeatureStdExtZiccamoa
: RISCVExtension<"ziccamoa", 1, 0,
- "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
-def : RISCVExtensionBitmask<"ziccamoa", 0, 6>;
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)", groupID=0, bitmaskShift=6>;
def FeatureStdExtZiccif
: RISCVExtension<"ziccif", 1, 0,
- "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
-def : RISCVExtensionBitmask<"ziccif", 0, 7>;
+ "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)", groupID=0, bitmaskShift=7>;
def FeatureStdExtZicclsm
: RISCVExtension<"zicclsm", 1, 0,
- "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
-def : RISCVExtensionBitmask<"zicclsm", 0, 8>;
+ "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)", groupID=0, bitmaskShift=8>;
def FeatureStdExtZiccrse
: RISCVExtension<"ziccrse", 1, 0,
- "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
-def : RISCVExtensionBitmask<"ziccrse", 0, 9>;
+ "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)", groupID=0, bitmaskShift=9>;
def FeatureStdExtZicsr
: RISCVExtension<"zicsr", 2, 0,
- "'zicsr' (CSRs)">;
-def : RISCVExtensionBitmask<"zicsr", 0, 10>;
+ "'zicsr' (CSRs)", groupID=0, bitmaskShift=10>;
def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
@@ -127,37 +114,32 @@ def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
def FeatureStdExtZicntr
: RISCVExtension<"zicntr", 2, 0,
"'Zicntr' (Base Counters and Timers)",
- [FeatureStdExtZicsr]>;
-def : RISCVExtensionBitmask<"zicntr", 0, 11>;
+ [FeatureStdExtZicsr], groupID=0, bitmaskShift=11>;
def FeatureStdExtZicond
: RISCVExtension<"zicond", 1, 0,
- "'Zicond' (Integer Conditional Operations)">;
-def : RISCVExtensionBitmask<"zicond", 0, 12>;
+ "'Zicond' (Integer Conditional Operations)", groupID=0, bitmaskShift=12>;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
def FeatureStdExtZifencei
: RISCVExtension<"zifencei", 2, 0,
- "'Zifencei' (fence.i)">;
-def : RISCVExtensionBitmask<"zifencei", 0, 13>;
+ "'Zifencei' (fence.i)", groupID=0, bitmaskShift=13>;
def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
def FeatureStdExtZihintpause
: RISCVExtension<"zihintpause", 2, 0,
- "'Zihintpause' (Pause Hint)">;
-def : RISCVExtensionBitmask<"zihintpause", 0, 14>;
+ "'Zihintpause' (Pause Hint)", groupID=0, bitmaskShift=14>;
def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
AssemblerPredicate<(all_of FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
def FeatureStdExtZihintntl
: RISCVExtension<"zihintntl", 1, 0,
- "'Zihintntl' (Non-Temporal Locality Hints)">;
-def : RISCVExtensionBitmask<"zihintntl", 0, 15>;
+ "'Zihintntl' (Non-Temporal Locality Hints)", groupID=0, bitmaskShift=15>;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -165,12 +147,10 @@ def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
def FeatureStdExtZihpm
: RISCVExtension<"zihpm", 2, 0,
"'Zihpm' (Hardware Performance Counters)",
- [FeatureStdExtZicsr]>;
-def : RISCVExtensionBitmask<"zihpm", 0, 16>;
+ [FeatureStdExtZicsr], groupID=0, bitmaskShift=16>;
def FeatureStdExtZimop : RISCVExtension<"zimop", 1, 0,
- "'Zimop' (May-Be-Operations)">;
-def : RISCVExtensionBitmask<"zimop", 0, 17>;
+ "'Zimop' (May-Be-Operations)", groupID=0, bitmaskShift=17>;
def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
@@ -178,8 +158,7 @@ def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
def FeatureStdExtZicfilp
: RISCVExperimentalExtension<"zicfilp", 0, 4,
"'Zicfilp' (Landing pad)",
- [FeatureStdExtZicsr]>;
-def : RISCVExtensionBitmask<"zicfilp", 0, 18>;
+ [FeatureStdExtZicsr], groupID=0, bitmaskShift=18>;
def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
AssemblerPredicate<(all_of FeatureStdExtZicfilp),
"'Zicfilp' (Landing pad)">;
@@ -189,8 +168,7 @@ def NoStdExtZicfilp : Predicate<"!Subtarget->hasStdExtZicfilp()">,
def FeatureStdExtZicfiss
: RISCVExperimentalExtension<"zicfiss", 0, 4,
"'Zicfiss' (Shadow stack)",
- [FeatureStdExtZicsr, FeatureStdExtZimop]>;
-def : RISCVExtensionBitmask<"zicfiss", 0, 19>;
+ [FeatureStdExtZicsr, FeatureStdExtZimop], groupID=0, bitmaskShift=19>;
def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
AssemblerPredicate<(all_of FeatureStdExtZicfiss),
"'Zicfiss' (Shadow stack)">;
@@ -200,16 +178,14 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
def FeatureStdExtM
: RISCVExtension<"m", 2, 0,
- "'M' (Integer Multiplication and Division)">;
-def : RISCVExtensionBitmask<"m", 0, 20>;
+ "'M' (Integer Multiplication and Division)", groupID=0, bitmaskShift=20>;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;
def FeatureStdExtZmmul
: RISCVExtension<"zmmul", 1, 0,
- "'Zmmul' (Integer Multiplication)">;
-def : RISCVExtensionBitmask<"zmmul", 0, 21>;
+ "'Zmmul' (Integer Multiplication)", groupID=0, bitmaskShift=21>;
def HasStdExtMOrZmmul
: Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
@@ -221,33 +197,28 @@ def HasStdExtMOrZmmul
def FeatureStdExtA
: RISCVExtension<"a", 2, 1,
- "'A' (Atomic Instructions)">;
-def : RISCVExtensionBitmask<"a", 0, 22>;
+ "'A' (Atomic Instructions)", groupID=0, bitmaskShift=22>;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<(all_of FeatureStdExtA),
"'A' (Atomic Instructions)">;
def FeatureStdExtZtso
: RISCVExperimentalExtension<"ztso", 0, 1,
- "'Ztso' (Memory Model - Total Store Order)">;
-def : RISCVExtensionBitmask<"ztso", 0, 23>;
+ "'Ztso' (Memory Model - Total Store Order)", groupID=0, bitmaskShift=23>;
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
def FeatureStdExtZa64rs : RISCVExtension<"za64rs", 1, 0,
- "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
-def : RISCVExtensionBitmask<"za64rs", 0, 24>;
+ "'Za64rs' (Reservation Set Size of at Most 64 Bytes)", groupID=0, bitmaskShift=24>;
def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
- "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
-def : RISCVExtensionBitmask<"za128rs", 0, 25>;
+ "'Za128rs' (Reservation Set Size of at Most 128 Bytes)", groupID=0, bitmaskShift=25>;
def FeatureStdExtZaamo
: RISCVExtension<"zaamo", 1, 0,
- "'Zaamo' (Atomic Memory Operations)">;
-def : RISCVExtensionBitmask<"zaamo", 0, 26>;
+ "'Zaamo' (Atomic Memory Operations)", groupID=0, bitmaskShift=26>;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -256,16 +227,14 @@ def HasStdExtAOrZaamo
def FeatureStdExtZabha
: RISCVExtension<"zabha", 1, 0,
- "'Zabha' (Byte and Halfword Atomic Memory Operations)">;
-def : RISCVExtensionBitmask<"zabha", 0, 27>;
+ "'Zabha' (Byte and Halfword Atomic Memory Operations)", groupID=0, bitmaskShift=27>;
def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
AssemblerPredicate<(all_of FeatureStdExtZabha),
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
def FeatureStdExtZacas
: RISCVExtension<"zacas", 1, 0,
- "'Zacas' (Atomic Compare-And-Swap Instructions)">;
-def : RISCVExtensionBitmask<"zacas", 0, 28>;
+ "'Zacas' (Atomic Compare-And-Swap Instructions)", groupID=0, bitmaskShift=28>;
def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
AssemblerPredicate<(all_of FeatureStdExtZacas),
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
@@ -273,16 +242,14 @@ def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
def FeatureStdExtZalasr
: RISCVExperimentalExtension<"zalasr", 0, 1,
- "'Zalasr' (Load-Acquire and Store-Release Instructions)">;
-def : RISCVExtensionBitmask<"zalasr", 0, 29>;
+ "'Zalasr' (Load-Acquire and Store-Release Instructions)", groupID=0, bitmaskShift=29>;
def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
AssemblerPredicate<(all_of FeatureStdExtZalasr),
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
def FeatureStdExtZalrsc
: RISCVExtension<"zalrsc", 1, 0,
- "'Zalrsc' (Load-Reserved/Store-Conditional)">;
-def : RISCVExtensionBitmask<"zalrsc", 0, 30>;
+ "'Zalrsc' (Load-Reserved/Store-Conditional)", groupID=0, bitmaskShift=30>;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
@@ -291,12 +258,10 @@ def HasStdExtAOrZalrsc
def FeatureStdExtZama16b
: RISCVExtension<"zama16b", 1, 0,
- "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">;
-def : RISCVExtensionBitmask<"zama16b", 0, 31>;
+ "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)", groupID=0, bitmaskShift=31>;
def FeatureStdExtZawrs : RISCVExtension<"zawrs", 1, 0,
- "'Zawrs' (Wait on Reservation Set)">;
-def : RISCVExtensionBitmask<"zawrs", 0, 32>;
+ "'Zawrs' (Wait on Reservation Set)", groupID=0, bitmaskShift=32>;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
AssemblerPredicate<(all_of FeatureStdExtZawrs),
"'Zawrs' (Wait on Reservation Set)">;
@@ -306,8 +271,7 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
def FeatureStdExtF
: RISCVExtension<"f", 2, 2,
"'F' (Single-Precision Floating-Point)",
- [FeatureStdExtZicsr]>;
-def : RISCVExtensionBitmask<"f", 0, 33>;
+ [FeatureStdExtZicsr], groupID=0, bitmaskShift=33>;
def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
AssemblerPredicate<(all_of FeatureStdExtF),
"'F' (Single-Precision Floating-Point)">;
@@ -315,8 +279,7 @@ def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
def FeatureStdExtD
: RISCVExtension<"d", 2, 2,
"'D' (Double-Precision Floating-Point)",
- [FeatureStdExtF]>;
-def : RISCVExtensionBitmask<"d", 0, 34>;
+ [FeatureStdExtF], groupID=0, bitmaskShift=34>;
def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
AssemblerPredicate<(all_of FeatureStdExtD),
"'D' (Double-Precision Floating-Point)">;
@@ -324,8 +287,7 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
def FeatureStdExtZfhmin
: RISCVExtension<"zfhmin", 1, 0,
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
- [FeatureStdExtF]>;
-def : RISCVExtensionBitmask<"zfhmin", 0, 35>;
+ [FeatureStdExtF], groupID=0, bitmaskShift=35>;
def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfhmin),
"'Zfh' (Half-Precision Floating-Point) or "
@@ -334,8 +296,7 @@ def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
def FeatureStdExtZfh
: RISCVExtension<"zfh", 1, 0,
"'Zfh' (Half-Precision Floating-Point)",
- [FeatureStdExtZfhmin]>;
-def : RISCVExtensionBitmask<"zfh", 0, 36>;
+ [FeatureStdExtZfhmin], groupID=0, bitmaskShift=36>;
def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
AssemblerPredicate<(all_of FeatureStdExtZfh),
"'Zfh' (Half-Precision Floating-Point)">;
@@ -344,8 +305,7 @@ def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
def FeatureStdExtZfbfmin
: RISCVExperimentalExtension<"zfbfmin", 1, 0,
"'Zfbfmin' (Scalar BF16 Converts)",
- [FeatureStdExtF]>;
-def : RISCVExtensionBitmask<"zfbfmin", 0, 37>;
+ [FeatureStdExtF], groupID=0, bitmaskShift=37>;
def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
"'Zfbfmin' (Scalar BF16 Converts)">;
@@ -361,8 +321,7 @@ def HasHalfFPLoadStoreMove
def FeatureStdExtZfa
: RISCVExtension<"zfa", 1, 0,
"'Zfa' (Additional Floating-Point)",
- [FeatureStdExtF]>;
-def : RISCVExtensionBitmask<"zfa", 0, 38>;
+ [FeatureStdExtF], groupID=0, bitmaskShift=38>;
def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
AssemblerPredicate<(all_of FeatureStdExtZfa),
"'Zfa' (Additional Floating-Point)">;
@@ -370,8 +329,7 @@ def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
def FeatureStdExtZfinx
: RISCVExtension<"zfinx", 1, 0,
"'Zfinx' (Float in Integer)",
- [FeatureStdExtZicsr]>;
-def : RISCVExtensionBitmask<"zfinx", 0, 39>;
+ [FeatureStdExtZicsr], groupID=0, bitmaskShift=39>;
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
AssemblerPredicate<(all_of FeatureStdExtZfinx),
"'Zfinx' (Float in Integer)">;
@@ -379,8 +337,7 @@ def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
def FeatureStdExtZdinx
: RISCVExtension<"zdinx", 1, 0,
"'Zdinx' (Double in Integer)",
- [FeatureStdExtZfinx]>;
-def : RISCVExtensionBitmask<"zdinx", 0, 40>;
+ [FeatureStdExtZfinx], groupID=0, bitmaskShift=40>;
def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
AssemblerPredicate<(all_of FeatureStdExtZdinx),
"'Zdinx' (Double in Integer)">;
@@ -388,8 +345,7 @@ def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
def FeatureStdExtZhinxmin
: RISCVExtension<"zhinxmin", 1, 0,
"'Zhinxmin' (Half Float in Integer Minimal)",
- [FeatureStdExtZfinx]>;
-def : RISCVExtensionBitmask<"zhinxmin", 0, 41>;
+ [FeatureStdExtZfinx], groupID=0, bitmaskShift=41>;
def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
"'Zhinx' (Half Float in Integer) or "
@@ -398,8 +354,7 @@ def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
def FeatureStdExtZhinx
: RISCVExtension<"zhinx", 1, 0,
"'Zhinx' (Half Float in Integer)",
- [FeatureStdExtZhinxmin]>;
-def : RISCVExtensionBitmask<"zhinx", 0, 42>;
+ [FeatureStdExtZhinxmin], groupID=0, bitmaskShift=42>;
def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
AssemblerPredicate<(all_of FeatureStdExtZhinx),
"'Zhinx' (Half Float in Integer)">;
@@ -409,8 +364,7 @@ def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
def FeatureStdExtC
: RISCVExtension<"c", 2, 0,
- "'C' (Compressed Instructions)">;
-def : RISCVExtensionBitmask<"c", 0, 43>;
+ "'C' (Compressed Instructions)", groupID=0, bitmaskShift=43>;
def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtC),
"'C' (Compressed Instructions)">;
@@ -425,8 +379,7 @@ def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
def FeatureStdExtZca
: RISCVExtension<"zca", 1, 0,
"'Zca' (part of the C extension, excluding compressed "
- "floating point loads/stores)">;
-def : RISCVExtensionBitmask<"zca", 0, 44>;
+ "floating point loads/stores)", groupID=0, bitmaskShift=44>;
def HasStdExtCOrZca
: Predicate<"Subtarget->hasStdExtCOrZca()">,
@@ -438,8 +391,7 @@ def HasStdExtCOrZca
def FeatureStdExtZcb
: RISCVExtension<"zcb", 1, 0,
"'Zcb' (Compressed basic bit manipulation instructions)",
- [FeatureStdExtZca]>;
-def : RISCVExtensionBitmask<"zcb", 0, 45>;
+ [FeatureStdExtZca], groupID=0, bitmaskShift=45>;
def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
AssemblerPredicate<(all_of FeatureStdExtZcb),
"'Zcb' (Compressed basic bit manipulation instructions)">;
@@ -447,8 +399,7 @@ def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
def FeatureStdExtZcd
: RISCVExtension<"zcd", 1, 0,
"'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
- [FeatureStdExtD, FeatureStdExtZca]>;
-def : RISCVExtensionBitmask<"zcd", 0, 46>;
+ [FeatureStdExtD, FeatureStdExtZca], groupID=0, bitmaskShift=46>;
def HasStdExtCOrZcd
: Predicate<"Subtarget->hasStdExtCOrZcd()">,
@@ -459,14 +410,12 @@ def HasStdExtCOrZcd
def FeatureStdExtZcf
: RISCVExtension<"zcf", 1, 0,
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
- [FeatureStdExtF, FeatureStdExtZca]>;
-def : RISCVExtensionBitmask<"zcf", 0, 47>;
+ [FeatureStdExtF, FeatureStdExtZca], groupID=0, bitmaskShift=47>;
def FeatureStdExtZcmp
: RISCVExtension<"zcmp", 1, 0,
"'Zcmp' (sequenced instuctions for code-size reduction)",
- [FeatureStdExtZca]>;
-def : RISCVExtensionBitmask<"zcmp", 0, 48>;
+ [FeatureStdExtZca], groupID=0, bitmaskShift=48>;
def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtZcmp),
"'Zcmp' (sequenced instuctions for code-size reduction)">;
@@ -474,8 +423,7 @@ def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdE
def FeatureStdExtZcmt
: RISCVExtension<"zcmt", 1, 0,
"'Zcmt' (table jump instuctions for code-size reduction)",
- [FeatureStdExtZca, FeatureStdExtZicsr]>;
-def : RISCVExtensionBitmask<"zcmt", 0, 49>;
+ [FeatureStdExtZca, FeatureStdExtZicsr], groupID=0, bitmaskShift=49>;
def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
AssemblerPredicate<(all_of FeatureStdExtZcmt),
"'Zcmt' (table jump instuctions for code-size reduction)">;
@@ -483,8 +431,7 @@ def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
def FeatureStdExtZce
: RISCVExtension<"zce", 1, 0,
"'Zce' (Compressed extensions for microcontrollers)",
- [FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>;
-def : RISCVExtensionBitmask<"zce", 0, 50>;
+ [FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt], groupID=0, bitmaskShift=50>;
def HasStdExtCOrZcfOrZce
: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
@@ -497,8 +444,7 @@ def HasStdExtCOrZcfOrZce
def FeatureStdExtZcmop
: RISCVExtension<"zcmop", 1, 0,
"'Zcmop' (Compressed May-Be-Operations)",
- [FeatureStdExtZca]>;
-def : RISCVExtensionBitmask<"zcmop", 0, 51>;
+ [FeatureStdExtZca], groupID=0, bitmaskShift=51>;
def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
AssemblerPredicate<(all_of FeatureStdExtZcmop),
"'Zcmop' (Compressed May-Be-Operations)">;
@@ -507,8 +453,7 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
def FeatureStdExtZba
: RISCVExtension<"zba", 1, 0,
- "'Zba' (Address Generation Instructions)">;
-def : RISCVExtensionBitmask<"zba", 0, 52>;
+ "'Zba' (Address Generation Instructions)", groupID=0, bitmaskShift=52>;
def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
AssemblerPredicate<(all_of FeatureStdExtZba),
"'Zba' (Address Generation Instructions)">;
@@ -516,24 +461,21 @@ def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
def FeatureStdExtZbb
: RISCVExtension<"zbb", 1, 0,
- "'Zbb' (Basic Bit-Manipulation)">;
-def : RISCVExtensionBitmask<"zbb", 0, 53>;
+ "'Zbb' (Basic Bit-Manipulation)", groupID=0, bitmaskShift=53>;
def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
AssemblerPredicate<(all_of FeatureStdExtZbb),
"'Zbb' (Basic Bit-Manipulation)">;
def FeatureStdExtZbc
: RISCVExtension<"zbc", 1, 0,
- "'Zbc' (Carry-Less Multiplication)">;
-def : RISCVExtensionBitmask<"zbc", 0, 54>;
+ "'Zbc' (Carry-Less Multiplication)", groupID=0, bitmaskShift=54>;
def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
AssemblerPredicate<(all_of FeatureStdExtZbc),
"'Zbc' (Carry-Less Multiplication)">;
def FeatureStdExtZbs
: RISCVExtension<"zbs", 1, 0,
- "'Zbs' (Single-Bit Instructions)">;
-def : RISCVExtensionBitmask<"zbs", 0, 55>;
+ "'Zbs' (Single-Bit Instructions)", groupID=0, bitmaskShift=55>;
def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
AssemblerPredicate<(all_of FeatureStdExtZbs),
"'Zbs' (Single-Bit Instructions)">;
@@ -542,16 +484,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
def FeatureStdExtZbkb
: RISCVExtension<"zbkb", 1, 0,
- "'Zbkb' (Bitmanip instructions for Cryptography)">;
-def : RISCVExtensionBitmask<"zbkb", 0, 56>;
+ "'Zbkb' (Bitmanip instructions for Cryptography)", groupID=0, bitmaskShift=56>;
def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
AssemblerPredicate<(all_of FeatureStdExtZbkb),
"'Zbkb' (Bitmanip instructions for Cryptography)">;
def FeatureStdExtZbkx
: RISCVExtension<"zbkx", 1, 0,
- "'Zbkx' (Crossbar permutation instructions)">;
-def : RISCVExtensionBitmask<"zbkx", 0, 57>;
+ "'Zbkx' (Crossbar permutation instructions)", groupID=0, bitmaskShift=57>;
def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
AssemblerPredicate<(all_of FeatureStdExtZbkx),
"'Zbkx' (Crossbar permutation instructions)">;
@@ -568,8 +508,7 @@ def HasStdExtZbbOrZbkb
def FeatureStdExtZbkc
: RISCVExtension<"zbkc", 1, 0,
"'Zbkc' (Carry-less multiply instructions for "
- "Cryptography)">;
-def : RISCVExtensionBitmask<"zbkc", 0, 58>;
+ "Cryptography)", groupID=0, bitmaskShift=58>;
def HasStdExtZbkc
: Predicate<"Subtarget->hasStdExtZbkc()">,
AssemblerPredicate<(all_of FeatureStdExtZbkc),
@@ -586,16 +525,14 @@ def HasStdExtZbcOrZbkc
def FeatureStdExtZknd
: RISCVExtension<"zknd", 1, 0,
- "'Zknd' (NIST Suite: AES Decryption)">;
-def : RISCVExtensionBitmask<"zknd", 0, 59>;
+ "'Zknd' (NIST Suite: AES Decryption)", groupID=0, bitmaskShift=59>;
def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
AssemblerPredicate<(all_of FeatureStdExtZknd),
"'Zknd' (NIST Suite: AES Decryption)">;
def FeatureStdExtZkne
: RISCVExtension<"zkne", 1, 0,
- "'Zkne' (NIST Suite: AES Encryption)">;
-def : RISCVExtensionBitmask<"zkne", 0, 60>;
+ "'Zkne' (NIST Suite: AES Encryption)", groupID=0, bitmaskShift=60>;
def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
AssemblerPredicate<(all_of FeatureStdExtZkne),
"'Zkne' (NIST Suite: AES Encryption)">;
@@ -610,32 +547,28 @@ def HasStdExtZkndOrZkne
def FeatureStdExtZknh
: RISCVExtension<"zknh", 1, 0,
- "'Zknh' (NIST Suite: Hash Function Instructions)">;
-def : RISCVExtensionBitmask<"zknh", 0, 61>;
+ "'Zknh' (NIST Suite: Hash Function Instructions)", groupID=0, bitmaskShift=61>;
def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
AssemblerPredicate<(all_of FeatureStdExtZknh),
"'Zknh' (NIST Suite: Hash Function Instructions)">;
def FeatureStdExtZksed
: RISCVExtension<"zksed", 1, 0,
- "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
-def : RISCVExtensionBitmask<"zksed", 0, 62>;
+ "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)", groupID=0, bitmaskShift=62>;
def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
AssemblerPredicate<(all_of FeatureStdExtZksed),
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
def FeatureStdExtZksh
: RISCVExtension<"zksh", 1, 0,
- "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
-def : RISCVExtensionBitmask<"zksh", 0, 63>;
+ "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)", groupID=0, bitmaskShift=63>;
def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
AssemblerPredicate<(all_of FeatureStdExtZksh),
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
def FeatureStdExtZkr
: RISCVExtension<"zkr", 1, 0,
- "'Zkr' (Entropy Source Extension)">;
-def : RISCVExtensionBitmask<"zkr", 1, 0>;
+ "'Zkr' (Entropy Source Extension)", groupID=1, bitmaskShift=0>;
def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
AssemblerPredicate<(all_of FeatureStdExtZkr),
"'Zkr' (Entropy Source Extension)">;
@@ -648,8 +581,7 @@ def FeatureStdExtZkn
FeatureStdExtZbkx,
FeatureStdExtZkne,
FeatureStdExtZknd,
- FeatureStdExtZknh]>;
-def : RISCVExtensionBitmask<"zkn", 1, 1>;
+ FeatureStdExtZknh], groupID=1, bitmaskShift=1>;
def FeatureStdExtZks
: RISCVExtension<"zks", 1, 0,
@@ -658,28 +590,24 @@ def FeatureStdExtZks
FeatureStdExtZbkc,
FeatureStdExtZbkx,
FeatureStdExtZksed,
- FeatureStdExtZksh]>;
-def : RISCVExtensionBitmask<"zks", 1, 2>;
+ FeatureStdExtZksh], groupID=1, bitmaskShift=2>;
def FeatureStdExtZkt
: RISCVExtension<"zkt", 1, 0,
- "'Zkt' (Data Independent Execution Latency)">;
-def : RISCVExtensionBitmask<"zkt", 1, 3>;
+ "'Zkt' (Data Independent Execution Latency)", groupID=1, bitmaskShift=3>;
def FeatureStdExtZk
: RISCVExtension<"zk", 1, 0,
"'Zk' (Standard scalar cryptography extension)",
[FeatureStdExtZkn,
FeatureStdExtZkr,
- FeatureStdExtZkt]>;
-def : RISCVExtensionBitmask<"zk", 1, 4>;
+ FeatureStdExtZkt], groupID=1, bitmaskShift=4>;
// Vector Extensions
def FeatureStdExtZvl32b : RISCVExtension<"zvl32b", 1, 0,
"'Zvl' (Minimum Vector Length) 32", [],
- "ZvlLen", "32">;
-def : RISCVExtensionBitmask<"zvl32b", 1, 5>;
+ "ZvlLen", "32", groupID=1, bitmaskShift=5>;
foreach i = { 6-16 } in {
defvar I = !shl(1, i);
@@ -687,57 +615,49 @@ foreach i = { 6-16 } in {
RISCVExtension<"zvl"#I#"b", 1, 0,
"'Zvl' (Minimum Vector Length) "#I,
[!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")],
- "ZvlLen", !cast<string>(I)>;
- def : RISCVExtensionBitmask<"zvl"#I#"b", 1, !add(6, !sub(i, 6))>;
+ "ZvlLen", !cast<string>(I), groupID=1, bitmaskShift=!add(6, !sub(i, 6))>;
}
def FeatureStdExtZve32x
: RISCVExtension<"zve32x", 1, 0,
"'Zve32x' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW)",
- [FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
-def : RISCVExtensionBitmask<"zve32x", 1, 17>;
+ [FeatureStdExtZicsr, FeatureStdExtZvl32b], groupID=1, bitmaskShift=17>;
def FeatureStdExtZve32f
: RISCVExtension<"zve32f", 1, 0,
"'Zve32f' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW and F extension)",
- [FeatureStdExtZve32x, FeatureStdExtF]>;
-def : RISCVExtensionBitmask<"zve32f", 1, 18>;
+ [FeatureStdExtZve32x, FeatureStdExtF], groupID=1, bitmaskShift=18>;
def FeatureStdExtZve64x
: RISCVExtension<"zve64x", 1, 0,
"'Zve64x' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW)",
- [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
-def : RISCVExtensionBitmask<"zve64x", 1, 19>;
+ [FeatureStdExtZve32x, FeatureStdExtZvl64b], groupID=1, bitmaskShift=19>;
def FeatureStdExtZve64f
: RISCVExtension<"zve64f", 1, 0,
"'Zve64f' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW and F extension)",
- [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
-def : RISCVExtensionBitmask<"zve64f", 1, 20>;
+ [FeatureStdExtZve32f, FeatureStdExtZve64x], groupID=1, bitmaskShift=20>;
def FeatureStdExtZve64d
: RISCVExtension<"zve64d", 1, 0,
"'Zve64d' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW, F and D extension)",
- [FeatureStdExtZve64f, FeatureStdExtD]>;
-def : RISCVExtensionBitmask<"zve64d", 1, 21>;
+ [FeatureStdExtZve64f, FeatureStdExtD], groupID=1, bitmaskShift=21>;
def FeatureStdExtV
: RISCVExtension<"v", 1, 0,
"'V' (Vector Extension for Application Processors)",
- [FeatureStdExtZvl128b, FeatureStdExtZve64d]>;
-def : RISCVExtensionBitmask<"v", 1, 22>;
+ [FeatureStdExtZvl128b, FeatureStdExtZve64d], groupID=1, bitmaskShift=22>;
def FeatureStdExtZvfbfmin
: RISCVExperimentalExtension<"zvfbfmin", 1, 0,
"'Zvbfmin' (Vector BF16 Converts)",
- [FeatureStdExtZve32f]>;
-def : RISCVExtensionBitmask<"zvfbfmin", 1, 23>;
+ [FeatureStdExtZve32f], groupID=1, bitmaskShift=23>;
def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
"'Zvfbfmin' (Vector BF16 Converts)">;
@@ -745,8 +665,7 @@ def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
def FeatureStdExtZvfbfwma
: RISCVExperimentalExtension<"zvfbfwma", 1, 0,
"'Zvfbfwma' (Vector BF16 widening mul-add)",
- [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>;
-def : RISCVExtensionBitmask<"zvfbfwma", 1, 24>;
+ [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin], groupID=1, bitmaskShift=24>;
def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
"'Zvfbfwma' (Vector BF16 widening mul-add)">;
@@ -754,14 +673,12 @@ def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
def FeatureStdExtZvfhmin
: RISCVExtension<"zvfhmin", 1, 0,
"'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
- [FeatureStdExtZve32f]>;
-def : RISCVExtensionBitmask<"zvfhmin", 1, 25>;
+ [FeatureStdExtZve32f], groupID=1, bitmaskShift=25>;
def FeatureStdExtZvfh
: RISCVExtension<"zvfh", 1, 0,
"'Zvfh' (Vector Half-Precision Floating-Point)",
- [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>;
-def : RISCVExtensionBitmask<"zvfh", 1, 26>;
+ [FeatureStdExtZvfhmin, FeatureStdExtZfhmin], groupID=1, bitmaskShift=26>;
def HasStdExtZfhOrZvfh
: Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
@@ -773,8 +690,7 @@ def HasStdExtZfhOrZvfh
def FeatureStdExtZvkb
: RISCVExtension<"zvkb", 1, 0,
- "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
-def : RISCVExtensionBitmask<"zvkb", 1, 27>;
+ "'Zvkb' (Vector Bit-manipulation used in Cryptography)", groupID=1, bitmaskShift=27>;
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
AssemblerPredicate<(all_of FeatureStdExtZvkb),
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
@@ -782,40 +698,35 @@ def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
def FeatureStdExtZvbb
: RISCVExtension<"zvbb", 1, 0,
"'Zvbb' (Vector basic bit-manipulation instructions)",
- [FeatureStdExtZvkb]>;
-def : RISCVExtensionBitmask<"zvbb", 1, 28>;
+ [FeatureStdExtZvkb], groupID=1, bitmaskShift=28>;
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
AssemblerPredicate<(all_of FeatureStdExtZvbb),
"'Zvbb' (Vector basic bit-manipulation instructions)">;
def FeatureStdExtZvbc
: RISCVExtension<"zvbc", 1, 0,
- "'Zvbc' (Vector Carryless Multiplication)">;
-def : RISCVExtensionBitmask<"zvbc", 1, 29>;
+ "'Zvbc' (Vector Carryless Multiplication)", groupID=1, bitmaskShift=29>;
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
AssemblerPredicate<(all_of FeatureStdExtZvbc),
"'Zvbc' (Vector Carryless Multiplication)">;
def FeatureStdExtZvkg
: RISCVExtension<"zvkg", 1, 0,
- "'Zvkg' (Vector GCM instructions for Cryptography)">;
-def : RISCVExtensionBitmask<"zvkg", 1, 30>;
+ "'Zvkg' (Vector GCM instructions for Cryptography)", groupID=1, bitmaskShift=30>;
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
AssemblerPredicate<(all_of FeatureStdExtZvkg),
"'Zvkg' (Vector GCM instructions for Cryptography)">;
def FeatureStdExtZvkned
: RISCVExtension<"zvkned", 1, 0,
- "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
-def : RISCVExtensionBitmask<"zvkned", 1, 31>;
+ "'Zvkned' (Vector AES Encryption & Decryption (Single Round))", groupID=1, bitmaskShift=31>;
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
AssemblerPredicate<(all_of FeatureStdExtZvkned),
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
def FeatureStdExtZvknha
: RISCVExtension<"zvknha", 1, 0,
- "'Zvknha' (Vector SHA-2 (SHA-256 only))">;
-def : RISCVExtensionBitmask<"zvknha", 1, 32>;
+ "'Zvknha' (Vector SHA-2 (SHA-256 only))", groupID=1, bitmaskShift=32>;
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
AssemblerPredicate<(all_of FeatureStdExtZvknha),
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
@@ -823,8 +734,7 @@ def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
def FeatureStdExtZvknhb
: RISCVExtension<"zvknhb", 1, 0,
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
- [FeatureStdExtZve64x]>;
-def : RISCVExtensionBitmask<"zvknhb", 1, 33>;
+ [FeatureStdExtZve64x], groupID=1, bitmaskShift=33>;
def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
AssemblerPredicate<(all_of FeatureStdExtZvknhb),
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;
@@ -835,24 +745,21 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg
def FeatureStdExtZvksed
: RISCVExtension<"zvksed", 1, 0,
- "'Zvksed' (SM4 Block Cipher Instructions)">;
-def : RISCVExtensionBitmask<"zvksed", 1, 34>;
+ "'Zvksed' (SM4 Block Cipher Instructions)", groupID=1, bitmaskShift=34>;
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
AssemblerPredicate<(all_of FeatureStdExtZvksed),
"'Zvksed' (SM4 Block Cipher Instructions)">;
def FeatureStdExtZvksh
: RISCVExtension<"zvksh", 1, 0,
- "'Zvksh' (SM3 Hash Function Instructions)">;
-def : RISCVExtensionBitmask<"zvksh", 1, 35>;
+ "'Zvksh' (SM3 Hash Function Instructions)", groupID=1, bitmaskShift=35>;
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
AssemblerPredicate<(all_of FeatureStdExtZvksh),
"'Zvksh' (SM3 Hash Function Instructions)">;
def FeatureStdExtZvkt
: RISCVExtension<"zvkt", 1, 0,
- "'Zvkt' (Vector Data-Independent Execution Latency)">;
-def : RISCVExtensionBitmask<"zvkt", 1, 36>;
+ "'Zvkt' (Vector Data-Independent Execution Latency)", groupID=1, bitmaskShift=36>;
// Zvk short-hand extensions
@@ -861,40 +768,34 @@ def FeatureStdExtZvkn
"'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and "
"'Zvkt')",
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
- FeatureStdExtZvkb, FeatureStdExtZvkt]>;
-def : RISCVExtensionBitmask<"zvkn", 1, 37>;
+ FeatureStdExtZvkb, FeatureStdExtZvkt], groupID=1, bitmaskShift=37>;
def FeatureStdExtZvknc
: RISCVExtension<"zvknc", 1, 0,
"'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')",
- [FeatureStdExtZvkn, FeatureStdExtZvbc]>;
-def : RISCVExtensionBitmask<"zvknc", 1, 38>;
+ [FeatureStdExtZvkn, FeatureStdExtZvbc], groupID=1, bitmaskShift=38>;
def FeatureStdExtZvkng
: RISCVExtension<"zvkng", 1, 0,
"'zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
- [FeatureStdExtZvkn, FeatureStdExtZvkg]>;
-def : RISCVExtensionBitmask<"zvkng", 1, 39>;
+ [FeatureStdExtZvkn, FeatureStdExtZvkg], groupID=1, bitmaskShift=39>;
def FeatureStdExtZvks
: RISCVExtension<"zvks", 1, 0,
"'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and "
"'Zvkt')",
[FeatureStdExtZvksed, FeatureStdExtZvksh,
- FeatureStdExtZvkb, FeatureStdExtZvkt]>;
-def : RISCVExtensionBitmask<"zvks", 1, 40>;
+ FeatureStdExtZvkb, FeatureStdExtZvkt], groupID=1, bitmaskShift=40>;
def FeatureStdExtZvksc
: RISCVExtension<"zvksc", 1, 0,
"'Zvksc' (shorthand for 'Zvks' and 'Zvbc')",
- [FeatureStdExtZvks, FeatureStdExtZvbc]>;
-def : RISCVExtensionBitmask<"zvksc", 1, 41>;
+ [FeatureStdExtZvks, FeatureStdExtZvbc], groupID=1, bitmaskShift=41>;
def FeatureStdExtZvksg
: RISCVExtension<"zvksg", 1, 0,
"'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
- [FeatureStdExtZvks, FeatureStdExtZvkg]>;
-def : RISCVExtensionBitmask<"zvksg", 1, 42>;
+ [FeatureStdExtZvks, FeatureStdExtZvkg], groupID=1, bitmaskShift=42>;
// Vector instruction predicates
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 4b6677c6b3d63..342d07685b5ec 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -226,7 +226,7 @@ static inline uint64_t getValueFromBitsInit(const BitsInit *B,
static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
std::vector<Record *> Extensions =
- RK.getAllDerivedDefinitionsIfDefined("RISCVExtensionBitmask");
+ RK.getAllDerivedDefinitionsIfDefined("RISCVExtension");
llvm::sort(Extensions, [](const Record *Rec1, const Record *Rec2) {
return getExtensionName(Rec1) < getExtensionName(Rec2);
});
@@ -240,6 +240,10 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
assert(GroupIDBits);
assert(BitmaskBits);
+ // For the extension without bitmask, skip it.
+ if (!getValueFromBitsInit(BitmaskBits, *Rec))
+ continue;
+
OS << " {"
<< "\"" << Rec->getValueAsString("Name") << "\""
<< ", " << getValueFromBitsInit(GroupIDBits, *Rec) << ", "
>From f78697fc2da66035b982838febf9745b5b16d108 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 5 Jun 2024 03:39:18 -0700
Subject: [PATCH 04/27] Remove Name attr because already exist
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 9b0cd3b6bb200..00af0ae2aab3d 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -37,7 +37,6 @@ class RISCVExtension<string name, int major, int minor, string desc,
bit Experimental = false;
// For Bitmask table
- string Name = !subst("experimental-", "", name);
bits<3> GroupID = groupID;
bits<64> Bitmask = !if(!eq(bitmaskShift, -1), 0, !shl(1, bitmaskShift));
}
>From 65086136c4e26cfc684ae43f2bc89a7ffe200491 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 5 Jun 2024 03:39:45 -0700
Subject: [PATCH 05/27] Add sanity check for duplicated bitmask
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 342d07685b5ec..451760f2ce9c3 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -11,6 +11,7 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/ADT/DenseMap.h"
#include "llvm/Support/RISCVISAUtils.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
@@ -231,6 +232,8 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
return getExtensionName(Rec1) < getExtensionName(Rec2);
});
+ llvm::DenseMap<std::pair<uint64_t, uint64_t>, bool> Seen;
+
OS << "#ifdef GET_RISCVExtensionBitmaskTable_IMPL\n";
OS << "static const RISCVExtensionBitmask ExtensionBitmask[]={\n";
for (const Record *Rec : Extensions) {
@@ -244,10 +247,18 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
if (!getValueFromBitsInit(BitmaskBits, *Rec))
continue;
+ StringRef ExtName = Rec->getValueAsString("Name");
+ ExtName.consume_front("experimental-");
+ uint64_t GroupIDVal = getValueFromBitsInit(GroupIDBits, *Rec);
+ uint64_t BitmaskVal = getValueFromBitsInit(BitmaskBits, *Rec);
+
+ assert(!Seen[std::make_pair(GroupIDVal, BitmaskVal)] &&
+ "duplicated bitmask");
+ Seen[std::make_pair(GroupIDVal, BitmaskVal)] = true;
+
OS << " {"
- << "\"" << Rec->getValueAsString("Name") << "\""
- << ", " << getValueFromBitsInit(GroupIDBits, *Rec) << ", "
- << getValueFromBitsInit(BitmaskBits, *Rec) << "ULL"
+ << "\"" << ExtName << "\""
+ << ", " << GroupIDVal << ", " << BitmaskVal << "ULL"
<< "},\n";
}
OS << "};\n";
>From 43d62797fa1547bf099a6ae090ce482fbf730fac Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 5 Jun 2024 03:58:02 -0700
Subject: [PATCH 06/27] Update testcase
---
llvm/test/TableGen/riscv-target-def.td | 26 +++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
index fb58448d7ce88..58ccf24a37626 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -5,38 +5,41 @@ include "llvm/Target/Target.td"
class RISCVExtension<string name, int major, int minor, string desc,
list<SubtargetFeature> implies = [],
string fieldname = !subst("Feature", "Has", NAME),
- string value = "true">
+ string value = "true", bits<3> groupID=0, int bitmaskShift=-1>
: SubtargetFeature<name, fieldname, value, desc, implies> {
int MajorVersion = major;
int MinorVersion = minor;
bit Experimental = false;
+
+ bits<3> GroupID = groupID;
+ bits<64> Bitmask = !if(!eq(bitmaskShift, -1), 0, !shl(1, bitmaskShift));
}
class RISCVExperimentalExtension<string name, int major, int minor, string desc,
list<RISCVExtension> implies = [],
string fieldname = !subst("Feature", "Has", NAME),
- string value = "true">
+ string value = "true", bits<3> groupID=0, int bitmaskShift=-1>
: RISCVExtension<"experimental-"#name, major, minor, desc, implies,
- fieldname, value> {
+ fieldname, value, groupID, bitmaskShift> {
let Experimental = true;
}
def FeatureStdExtI
: RISCVExtension<"i", 2, 1,
- "'I' (Base Integer Instruction Set)">;
+ "'I' (Base Integer Instruction Set)", groupID=0, bitmaskShift=0>;
def FeatureStdExtZicsr
: RISCVExtension<"zicsr", 2, 0,
- "'zicsr' (CSRs)">;
+ "'zicsr' (CSRs)", groupID=0, bitmaskShift=10>;
def FeatureStdExtZifencei
: RISCVExtension<"zifencei", 2, 0,
- "'Zifencei' (fence.i)">;
+ "'Zifencei' (fence.i)", groupID=0, bitmaskShift=13>;
def FeatureStdExtF
: RISCVExtension<"f", 2, 2,
"'F' (Single-Precision Floating-Point)",
- [FeatureStdExtZicsr]>;
+ [FeatureStdExtZicsr], groupID=0, bitmaskShift=33>;
def FeatureStdExtZidummy
: RISCVExperimentalExtension<"zidummy", 0, 1,
@@ -171,3 +174,12 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
// CHECK-NEXT: TUNE_PROC(ROCKET, "rocket")
// CHECK: #undef TUNE_PROC
+
+// CHECK: #ifdef GET_RISCVExtensionBitmaskTable_IMPL
+// CHECK-NEXT: static const RISCVExtensionBitmask ExtensionBitmask[]={
+// CHECK-NEXT: {"f", 0, 8589934592ULL},
+// CHECK-NEXT: {"i", 0, 1ULL},
+// CHECK-NEXT: {"zicsr", 0, 1024ULL},
+// CHECK-NEXT: {"zifencei", 0, 8192ULL},
+// CHECK-NEXT: };
+// CHECK-NEXT: #endif
>From be86f85467de8cbb3c3e5c43bee5cab190d42667 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 6 Jun 2024 02:56:20 -0700
Subject: [PATCH 07/27] Seqerate bitmask but append with RISCVExtension define
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 225 ++++++++++--------
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 2 +-
2 files changed, 123 insertions(+), 104 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 00af0ae2aab3d..f234a49ebca34 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -25,7 +25,7 @@
class RISCVExtension<string name, int major, int minor, string desc,
list<SubtargetFeature> implies = [],
string fieldname = !subst("Feature", "Has", NAME),
- string value = "true", bits<3> groupID=0, int bitmaskShift=-1>
+ string value = "true">
: SubtargetFeature<name, fieldname, value, desc, implies> {
// MajorVersion - The major version for this extension.
int MajorVersion = major;
@@ -35,10 +35,11 @@ class RISCVExtension<string name, int major, int minor, string desc,
// Experimental - Does extension require -menable-experimental-extensions.
bit Experimental = false;
+}
- // For Bitmask table
- bits<3> GroupID = groupID;
- bits<64> Bitmask = !if(!eq(bitmaskShift, -1), 0, !shl(1, bitmaskShift));
+class RISCVExtensionBitmask<bits<3> groupID, int bitmaskShift> {
+ bits<3> GroupID = groupID;
+ bits<64> Bitmask = !shl(1, bitmaskShift);
}
// Version of RISCVExtension to be used for Experimental extensions. This
@@ -46,9 +47,9 @@ class RISCVExtension<string name, int major, int minor, string desc,
class RISCVExperimentalExtension<string name, int major, int minor, string desc,
list<RISCVExtension> implies = [],
string fieldname = !subst("Feature", "Has", NAME),
- string value = "true", bits<3> groupID=0, int bitmaskShift=-1>
+ string value = "true">
: RISCVExtension<"experimental-"#name, major, minor, desc, implies,
- fieldname, value, groupID, bitmaskShift> {
+ fieldname, value> {
let Experimental = true;
}
@@ -56,56 +57,66 @@ class RISCVExperimentalExtension<string name, int major, int minor, string desc,
def FeatureStdExtI
: RISCVExtension<"i", 2, 1,
- "'I' (Base Integer Instruction Set)", groupID=0, bitmaskShift=0>;
+ "'I' (Base Integer Instruction Set)">,
+ RISCVExtensionBitmask<0, 0>;
def FeatureStdExtE
: RISCVExtension<"e", 2, 0,
- "Implements RV{32,64}E (provides 16 rather than 32 GPRs)", groupID=0, bitmaskShift=1>;
+ "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">,
+ RISCVExtensionBitmask<0, 1>;
def FeatureStdExtZic64b
: RISCVExtension<"zic64b", 1, 0,
- "'Zic64b' (Cache Block Size Is 64 Bytes)", groupID=0, bitmaskShift=2>;
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">,
+ RISCVExtensionBitmask<0, 2>;
def FeatureStdExtZicbom
: RISCVExtension<"zicbom", 1, 0,
- "'Zicbom' (Cache-Block Management Instructions)", groupID=0, bitmaskShift=3>;
+ "'Zicbom' (Cache-Block Management Instructions)">,
+ RISCVExtensionBitmask<0, 3>;
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
AssemblerPredicate<(all_of FeatureStdExtZicbom),
"'Zicbom' (Cache-Block Management Instructions)">;
def FeatureStdExtZicbop
: RISCVExtension<"zicbop", 1, 0,
- "'Zicbop' (Cache-Block Prefetch Instructions)", groupID=0, bitmaskShift=4>;
+ "'Zicbop' (Cache-Block Prefetch Instructions)">,
+ RISCVExtensionBitmask<0, 4>;
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
def FeatureStdExtZicboz
: RISCVExtension<"zicboz", 1, 0,
- "'Zicboz' (Cache-Block Zero Instructions)", groupID=0, bitmaskShift=5>;
+ "'Zicboz' (Cache-Block Zero Instructions)">,
+ RISCVExtensionBitmask<0, 5>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
def FeatureStdExtZiccamoa
: RISCVExtension<"ziccamoa", 1, 0,
- "'Ziccamoa' (Main Memory Supports All Atomics in A)", groupID=0, bitmaskShift=6>;
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">,
+ RISCVExtensionBitmask<0, 6>;
def FeatureStdExtZiccif
: RISCVExtension<"ziccif", 1, 0,
- "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)", groupID=0, bitmaskShift=7>;
+ "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">,
+ RISCVExtensionBitmask<0, 7>;
def FeatureStdExtZicclsm
: RISCVExtension<"zicclsm", 1, 0,
- "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)", groupID=0, bitmaskShift=8>;
+ "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">,
+ RISCVExtensionBitmask<0, 8>;
def FeatureStdExtZiccrse
: RISCVExtension<"ziccrse", 1, 0,
- "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)", groupID=0, bitmaskShift=9>;
+ "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">,
+ RISCVExtensionBitmask<0, 9>;
def FeatureStdExtZicsr
: RISCVExtension<"zicsr", 2, 0,
- "'zicsr' (CSRs)", groupID=0, bitmaskShift=10>;
+ "'zicsr' (CSRs)">, RISCVExtensionBitmask<0, 10>;
def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
@@ -113,32 +124,32 @@ def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
def FeatureStdExtZicntr
: RISCVExtension<"zicntr", 2, 0,
"'Zicntr' (Base Counters and Timers)",
- [FeatureStdExtZicsr], groupID=0, bitmaskShift=11>;
+ [FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 11>;
def FeatureStdExtZicond
: RISCVExtension<"zicond", 1, 0,
- "'Zicond' (Integer Conditional Operations)", groupID=0, bitmaskShift=12>;
+ "'Zicond' (Integer Conditional Operations)">, RISCVExtensionBitmask<0, 12>;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
def FeatureStdExtZifencei
: RISCVExtension<"zifencei", 2, 0,
- "'Zifencei' (fence.i)", groupID=0, bitmaskShift=13>;
+ "'Zifencei' (fence.i)">, RISCVExtensionBitmask<0, 13>;
def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
def FeatureStdExtZihintpause
: RISCVExtension<"zihintpause", 2, 0,
- "'Zihintpause' (Pause Hint)", groupID=0, bitmaskShift=14>;
+ "'Zihintpause' (Pause Hint)">, RISCVExtensionBitmask<0, 14>;
def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
AssemblerPredicate<(all_of FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
def FeatureStdExtZihintntl
: RISCVExtension<"zihintntl", 1, 0,
- "'Zihintntl' (Non-Temporal Locality Hints)", groupID=0, bitmaskShift=15>;
+ "'Zihintntl' (Non-Temporal Locality Hints)">, RISCVExtensionBitmask<0, 15>;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -146,10 +157,10 @@ def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
def FeatureStdExtZihpm
: RISCVExtension<"zihpm", 2, 0,
"'Zihpm' (Hardware Performance Counters)",
- [FeatureStdExtZicsr], groupID=0, bitmaskShift=16>;
+ [FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 16>;
def FeatureStdExtZimop : RISCVExtension<"zimop", 1, 0,
- "'Zimop' (May-Be-Operations)", groupID=0, bitmaskShift=17>;
+ "'Zimop' (May-Be-Operations)">, RISCVExtensionBitmask<0, 17>;
def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
@@ -157,7 +168,7 @@ def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
def FeatureStdExtZicfilp
: RISCVExperimentalExtension<"zicfilp", 0, 4,
"'Zicfilp' (Landing pad)",
- [FeatureStdExtZicsr], groupID=0, bitmaskShift=18>;
+ [FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 18>;
def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
AssemblerPredicate<(all_of FeatureStdExtZicfilp),
"'Zicfilp' (Landing pad)">;
@@ -167,7 +178,8 @@ def NoStdExtZicfilp : Predicate<"!Subtarget->hasStdExtZicfilp()">,
def FeatureStdExtZicfiss
: RISCVExperimentalExtension<"zicfiss", 0, 4,
"'Zicfiss' (Shadow stack)",
- [FeatureStdExtZicsr, FeatureStdExtZimop], groupID=0, bitmaskShift=19>;
+ [FeatureStdExtZicsr, FeatureStdExtZimop]>,
+ RISCVExtensionBitmask<0, 19>;
def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
AssemblerPredicate<(all_of FeatureStdExtZicfiss),
"'Zicfiss' (Shadow stack)">;
@@ -177,14 +189,14 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
def FeatureStdExtM
: RISCVExtension<"m", 2, 0,
- "'M' (Integer Multiplication and Division)", groupID=0, bitmaskShift=20>;
+ "'M' (Integer Multiplication and Division)">, RISCVExtensionBitmask<0, 20>;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;
def FeatureStdExtZmmul
: RISCVExtension<"zmmul", 1, 0,
- "'Zmmul' (Integer Multiplication)", groupID=0, bitmaskShift=21>;
+ "'Zmmul' (Integer Multiplication)">, RISCVExtensionBitmask<0, 21>;
def HasStdExtMOrZmmul
: Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
@@ -196,28 +208,31 @@ def HasStdExtMOrZmmul
def FeatureStdExtA
: RISCVExtension<"a", 2, 1,
- "'A' (Atomic Instructions)", groupID=0, bitmaskShift=22>;
+ "'A' (Atomic Instructions)">, RISCVExtensionBitmask<0, 22>;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<(all_of FeatureStdExtA),
"'A' (Atomic Instructions)">;
def FeatureStdExtZtso
: RISCVExperimentalExtension<"ztso", 0, 1,
- "'Ztso' (Memory Model - Total Store Order)", groupID=0, bitmaskShift=23>;
+ "'Ztso' (Memory Model - Total Store Order)">,
+ RISCVExtensionBitmask<0, 23>;
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
def FeatureStdExtZa64rs : RISCVExtension<"za64rs", 1, 0,
- "'Za64rs' (Reservation Set Size of at Most 64 Bytes)", groupID=0, bitmaskShift=24>;
+ "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">,
+ RISCVExtensionBitmask<0, 24>;
def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
- "'Za128rs' (Reservation Set Size of at Most 128 Bytes)", groupID=0, bitmaskShift=25>;
+ "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">,
+ RISCVExtensionBitmask<0, 25>;
def FeatureStdExtZaamo
: RISCVExtension<"zaamo", 1, 0,
- "'Zaamo' (Atomic Memory Operations)", groupID=0, bitmaskShift=26>;
+ "'Zaamo' (Atomic Memory Operations)">, RISCVExtensionBitmask<0, 26>;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -226,14 +241,14 @@ def HasStdExtAOrZaamo
def FeatureStdExtZabha
: RISCVExtension<"zabha", 1, 0,
- "'Zabha' (Byte and Halfword Atomic Memory Operations)", groupID=0, bitmaskShift=27>;
+ "'Zabha' (Byte and Halfword Atomic Memory Operations)">, RISCVExtensionBitmask<0, 27>;
def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
AssemblerPredicate<(all_of FeatureStdExtZabha),
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
def FeatureStdExtZacas
: RISCVExtension<"zacas", 1, 0,
- "'Zacas' (Atomic Compare-And-Swap Instructions)", groupID=0, bitmaskShift=28>;
+ "'Zacas' (Atomic Compare-And-Swap Instructions)">, RISCVExtensionBitmask<0, 28>;
def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
AssemblerPredicate<(all_of FeatureStdExtZacas),
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
@@ -241,14 +256,15 @@ def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
def FeatureStdExtZalasr
: RISCVExperimentalExtension<"zalasr", 0, 1,
- "'Zalasr' (Load-Acquire and Store-Release Instructions)", groupID=0, bitmaskShift=29>;
+ "'Zalasr' (Load-Acquire and Store-Release Instructions)">,
+ RISCVExtensionBitmask<0, 29>;
def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
AssemblerPredicate<(all_of FeatureStdExtZalasr),
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
def FeatureStdExtZalrsc
: RISCVExtension<"zalrsc", 1, 0,
- "'Zalrsc' (Load-Reserved/Store-Conditional)", groupID=0, bitmaskShift=30>;
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">, RISCVExtensionBitmask<0, 30>;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
@@ -257,10 +273,12 @@ def HasStdExtAOrZalrsc
def FeatureStdExtZama16b
: RISCVExtension<"zama16b", 1, 0,
- "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)", groupID=0, bitmaskShift=31>;
+ "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">,
+ RISCVExtensionBitmask<0, 31>;
def FeatureStdExtZawrs : RISCVExtension<"zawrs", 1, 0,
- "'Zawrs' (Wait on Reservation Set)", groupID=0, bitmaskShift=32>;
+ "'Zawrs' (Wait on Reservation Set)">,
+ RISCVExtensionBitmask<0, 32>;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
AssemblerPredicate<(all_of FeatureStdExtZawrs),
"'Zawrs' (Wait on Reservation Set)">;
@@ -270,7 +288,7 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
def FeatureStdExtF
: RISCVExtension<"f", 2, 2,
"'F' (Single-Precision Floating-Point)",
- [FeatureStdExtZicsr], groupID=0, bitmaskShift=33>;
+ [FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 33>;
def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
AssemblerPredicate<(all_of FeatureStdExtF),
"'F' (Single-Precision Floating-Point)">;
@@ -278,7 +296,7 @@ def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
def FeatureStdExtD
: RISCVExtension<"d", 2, 2,
"'D' (Double-Precision Floating-Point)",
- [FeatureStdExtF], groupID=0, bitmaskShift=34>;
+ [FeatureStdExtF]>, RISCVExtensionBitmask<0, 34>;
def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
AssemblerPredicate<(all_of FeatureStdExtD),
"'D' (Double-Precision Floating-Point)">;
@@ -286,7 +304,7 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
def FeatureStdExtZfhmin
: RISCVExtension<"zfhmin", 1, 0,
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
- [FeatureStdExtF], groupID=0, bitmaskShift=35>;
+ [FeatureStdExtF]>, RISCVExtensionBitmask<0, 35>;
def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfhmin),
"'Zfh' (Half-Precision Floating-Point) or "
@@ -295,7 +313,7 @@ def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
def FeatureStdExtZfh
: RISCVExtension<"zfh", 1, 0,
"'Zfh' (Half-Precision Floating-Point)",
- [FeatureStdExtZfhmin], groupID=0, bitmaskShift=36>;
+ [FeatureStdExtZfhmin]>, RISCVExtensionBitmask<0, 36>;
def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
AssemblerPredicate<(all_of FeatureStdExtZfh),
"'Zfh' (Half-Precision Floating-Point)">;
@@ -304,7 +322,7 @@ def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
def FeatureStdExtZfbfmin
: RISCVExperimentalExtension<"zfbfmin", 1, 0,
"'Zfbfmin' (Scalar BF16 Converts)",
- [FeatureStdExtF], groupID=0, bitmaskShift=37>;
+ [FeatureStdExtF]>, RISCVExtensionBitmask<0, 37>;
def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
"'Zfbfmin' (Scalar BF16 Converts)">;
@@ -320,7 +338,7 @@ def HasHalfFPLoadStoreMove
def FeatureStdExtZfa
: RISCVExtension<"zfa", 1, 0,
"'Zfa' (Additional Floating-Point)",
- [FeatureStdExtF], groupID=0, bitmaskShift=38>;
+ [FeatureStdExtF]>, RISCVExtensionBitmask<0, 38>;
def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
AssemblerPredicate<(all_of FeatureStdExtZfa),
"'Zfa' (Additional Floating-Point)">;
@@ -328,7 +346,7 @@ def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
def FeatureStdExtZfinx
: RISCVExtension<"zfinx", 1, 0,
"'Zfinx' (Float in Integer)",
- [FeatureStdExtZicsr], groupID=0, bitmaskShift=39>;
+ [FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 39>;
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
AssemblerPredicate<(all_of FeatureStdExtZfinx),
"'Zfinx' (Float in Integer)">;
@@ -336,7 +354,7 @@ def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
def FeatureStdExtZdinx
: RISCVExtension<"zdinx", 1, 0,
"'Zdinx' (Double in Integer)",
- [FeatureStdExtZfinx], groupID=0, bitmaskShift=40>;
+ [FeatureStdExtZfinx]>, RISCVExtensionBitmask<0, 40>;
def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
AssemblerPredicate<(all_of FeatureStdExtZdinx),
"'Zdinx' (Double in Integer)">;
@@ -344,7 +362,7 @@ def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
def FeatureStdExtZhinxmin
: RISCVExtension<"zhinxmin", 1, 0,
"'Zhinxmin' (Half Float in Integer Minimal)",
- [FeatureStdExtZfinx], groupID=0, bitmaskShift=41>;
+ [FeatureStdExtZfinx]>, RISCVExtensionBitmask<0, 41>;
def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
"'Zhinx' (Half Float in Integer) or "
@@ -353,7 +371,7 @@ def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
def FeatureStdExtZhinx
: RISCVExtension<"zhinx", 1, 0,
"'Zhinx' (Half Float in Integer)",
- [FeatureStdExtZhinxmin], groupID=0, bitmaskShift=42>;
+ [FeatureStdExtZhinxmin]>, RISCVExtensionBitmask<0, 42>;
def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
AssemblerPredicate<(all_of FeatureStdExtZhinx),
"'Zhinx' (Half Float in Integer)">;
@@ -363,7 +381,7 @@ def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
def FeatureStdExtC
: RISCVExtension<"c", 2, 0,
- "'C' (Compressed Instructions)", groupID=0, bitmaskShift=43>;
+ "'C' (Compressed Instructions)">, RISCVExtensionBitmask<0, 43>;
def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtC),
"'C' (Compressed Instructions)">;
@@ -378,7 +396,7 @@ def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
def FeatureStdExtZca
: RISCVExtension<"zca", 1, 0,
"'Zca' (part of the C extension, excluding compressed "
- "floating point loads/stores)", groupID=0, bitmaskShift=44>;
+ "floating point loads/stores)">, RISCVExtensionBitmask<0, 44>;
def HasStdExtCOrZca
: Predicate<"Subtarget->hasStdExtCOrZca()">,
@@ -390,7 +408,7 @@ def HasStdExtCOrZca
def FeatureStdExtZcb
: RISCVExtension<"zcb", 1, 0,
"'Zcb' (Compressed basic bit manipulation instructions)",
- [FeatureStdExtZca], groupID=0, bitmaskShift=45>;
+ [FeatureStdExtZca]>, RISCVExtensionBitmask<0, 45>;
def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
AssemblerPredicate<(all_of FeatureStdExtZcb),
"'Zcb' (Compressed basic bit manipulation instructions)">;
@@ -398,7 +416,7 @@ def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
def FeatureStdExtZcd
: RISCVExtension<"zcd", 1, 0,
"'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
- [FeatureStdExtD, FeatureStdExtZca], groupID=0, bitmaskShift=46>;
+ [FeatureStdExtD, FeatureStdExtZca]>, RISCVExtensionBitmask<0, 46>;
def HasStdExtCOrZcd
: Predicate<"Subtarget->hasStdExtCOrZcd()">,
@@ -409,12 +427,12 @@ def HasStdExtCOrZcd
def FeatureStdExtZcf
: RISCVExtension<"zcf", 1, 0,
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
- [FeatureStdExtF, FeatureStdExtZca], groupID=0, bitmaskShift=47>;
+ [FeatureStdExtF, FeatureStdExtZca]>, RISCVExtensionBitmask<0, 47>;
def FeatureStdExtZcmp
: RISCVExtension<"zcmp", 1, 0,
"'Zcmp' (sequenced instuctions for code-size reduction)",
- [FeatureStdExtZca], groupID=0, bitmaskShift=48>;
+ [FeatureStdExtZca]>, RISCVExtensionBitmask<0, 48>;
def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtZcmp),
"'Zcmp' (sequenced instuctions for code-size reduction)">;
@@ -422,7 +440,7 @@ def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdE
def FeatureStdExtZcmt
: RISCVExtension<"zcmt", 1, 0,
"'Zcmt' (table jump instuctions for code-size reduction)",
- [FeatureStdExtZca, FeatureStdExtZicsr], groupID=0, bitmaskShift=49>;
+ [FeatureStdExtZca, FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 49>;
def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
AssemblerPredicate<(all_of FeatureStdExtZcmt),
"'Zcmt' (table jump instuctions for code-size reduction)">;
@@ -430,7 +448,8 @@ def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
def FeatureStdExtZce
: RISCVExtension<"zce", 1, 0,
"'Zce' (Compressed extensions for microcontrollers)",
- [FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt], groupID=0, bitmaskShift=50>;
+ [FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>,
+ RISCVExtensionBitmask<0, 50>;
def HasStdExtCOrZcfOrZce
: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
@@ -443,7 +462,7 @@ def HasStdExtCOrZcfOrZce
def FeatureStdExtZcmop
: RISCVExtension<"zcmop", 1, 0,
"'Zcmop' (Compressed May-Be-Operations)",
- [FeatureStdExtZca], groupID=0, bitmaskShift=51>;
+ [FeatureStdExtZca]>, RISCVExtensionBitmask<0, 51>;
def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
AssemblerPredicate<(all_of FeatureStdExtZcmop),
"'Zcmop' (Compressed May-Be-Operations)">;
@@ -452,7 +471,7 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
def FeatureStdExtZba
: RISCVExtension<"zba", 1, 0,
- "'Zba' (Address Generation Instructions)", groupID=0, bitmaskShift=52>;
+ "'Zba' (Address Generation Instructions)">, RISCVExtensionBitmask<0, 52>;
def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
AssemblerPredicate<(all_of FeatureStdExtZba),
"'Zba' (Address Generation Instructions)">;
@@ -460,21 +479,21 @@ def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
def FeatureStdExtZbb
: RISCVExtension<"zbb", 1, 0,
- "'Zbb' (Basic Bit-Manipulation)", groupID=0, bitmaskShift=53>;
+ "'Zbb' (Basic Bit-Manipulation)">, RISCVExtensionBitmask<0, 53>;
def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
AssemblerPredicate<(all_of FeatureStdExtZbb),
"'Zbb' (Basic Bit-Manipulation)">;
def FeatureStdExtZbc
: RISCVExtension<"zbc", 1, 0,
- "'Zbc' (Carry-Less Multiplication)", groupID=0, bitmaskShift=54>;
+ "'Zbc' (Carry-Less Multiplication)">, RISCVExtensionBitmask<0, 54>;
def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
AssemblerPredicate<(all_of FeatureStdExtZbc),
"'Zbc' (Carry-Less Multiplication)">;
def FeatureStdExtZbs
: RISCVExtension<"zbs", 1, 0,
- "'Zbs' (Single-Bit Instructions)", groupID=0, bitmaskShift=55>;
+ "'Zbs' (Single-Bit Instructions)">, RISCVExtensionBitmask<0, 55>;
def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
AssemblerPredicate<(all_of FeatureStdExtZbs),
"'Zbs' (Single-Bit Instructions)">;
@@ -483,14 +502,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
def FeatureStdExtZbkb
: RISCVExtension<"zbkb", 1, 0,
- "'Zbkb' (Bitmanip instructions for Cryptography)", groupID=0, bitmaskShift=56>;
+ "'Zbkb' (Bitmanip instructions for Cryptography)">, RISCVExtensionBitmask<0, 56>;
def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
AssemblerPredicate<(all_of FeatureStdExtZbkb),
"'Zbkb' (Bitmanip instructions for Cryptography)">;
def FeatureStdExtZbkx
: RISCVExtension<"zbkx", 1, 0,
- "'Zbkx' (Crossbar permutation instructions)", groupID=0, bitmaskShift=57>;
+ "'Zbkx' (Crossbar permutation instructions)">, RISCVExtensionBitmask<0, 57>;
def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
AssemblerPredicate<(all_of FeatureStdExtZbkx),
"'Zbkx' (Crossbar permutation instructions)">;
@@ -507,7 +526,7 @@ def HasStdExtZbbOrZbkb
def FeatureStdExtZbkc
: RISCVExtension<"zbkc", 1, 0,
"'Zbkc' (Carry-less multiply instructions for "
- "Cryptography)", groupID=0, bitmaskShift=58>;
+ "Cryptography)">, RISCVExtensionBitmask<0, 58>;
def HasStdExtZbkc
: Predicate<"Subtarget->hasStdExtZbkc()">,
AssemblerPredicate<(all_of FeatureStdExtZbkc),
@@ -524,14 +543,14 @@ def HasStdExtZbcOrZbkc
def FeatureStdExtZknd
: RISCVExtension<"zknd", 1, 0,
- "'Zknd' (NIST Suite: AES Decryption)", groupID=0, bitmaskShift=59>;
+ "'Zknd' (NIST Suite: AES Decryption)">, RISCVExtensionBitmask<0, 59>;
def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
AssemblerPredicate<(all_of FeatureStdExtZknd),
"'Zknd' (NIST Suite: AES Decryption)">;
def FeatureStdExtZkne
: RISCVExtension<"zkne", 1, 0,
- "'Zkne' (NIST Suite: AES Encryption)", groupID=0, bitmaskShift=60>;
+ "'Zkne' (NIST Suite: AES Encryption)">, RISCVExtensionBitmask<0, 60>;
def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
AssemblerPredicate<(all_of FeatureStdExtZkne),
"'Zkne' (NIST Suite: AES Encryption)">;
@@ -546,28 +565,28 @@ def HasStdExtZkndOrZkne
def FeatureStdExtZknh
: RISCVExtension<"zknh", 1, 0,
- "'Zknh' (NIST Suite: Hash Function Instructions)", groupID=0, bitmaskShift=61>;
+ "'Zknh' (NIST Suite: Hash Function Instructions)">, RISCVExtensionBitmask<0, 61>;
def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
AssemblerPredicate<(all_of FeatureStdExtZknh),
"'Zknh' (NIST Suite: Hash Function Instructions)">;
def FeatureStdExtZksed
: RISCVExtension<"zksed", 1, 0,
- "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)", groupID=0, bitmaskShift=62>;
+ "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">, RISCVExtensionBitmask<0, 62>;
def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
AssemblerPredicate<(all_of FeatureStdExtZksed),
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
def FeatureStdExtZksh
: RISCVExtension<"zksh", 1, 0,
- "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)", groupID=0, bitmaskShift=63>;
+ "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">, RISCVExtensionBitmask<0, 63>;
def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
AssemblerPredicate<(all_of FeatureStdExtZksh),
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
def FeatureStdExtZkr
: RISCVExtension<"zkr", 1, 0,
- "'Zkr' (Entropy Source Extension)", groupID=1, bitmaskShift=0>;
+ "'Zkr' (Entropy Source Extension)">, RISCVExtensionBitmask<1, 0>;
def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
AssemblerPredicate<(all_of FeatureStdExtZkr),
"'Zkr' (Entropy Source Extension)">;
@@ -580,7 +599,7 @@ def FeatureStdExtZkn
FeatureStdExtZbkx,
FeatureStdExtZkne,
FeatureStdExtZknd,
- FeatureStdExtZknh], groupID=1, bitmaskShift=1>;
+ FeatureStdExtZknh]>, RISCVExtensionBitmask<1, 1>;
def FeatureStdExtZks
: RISCVExtension<"zks", 1, 0,
@@ -589,24 +608,24 @@ def FeatureStdExtZks
FeatureStdExtZbkc,
FeatureStdExtZbkx,
FeatureStdExtZksed,
- FeatureStdExtZksh], groupID=1, bitmaskShift=2>;
+ FeatureStdExtZksh]>, RISCVExtensionBitmask<1, 2>;
def FeatureStdExtZkt
: RISCVExtension<"zkt", 1, 0,
- "'Zkt' (Data Independent Execution Latency)", groupID=1, bitmaskShift=3>;
+ "'Zkt' (Data Independent Execution Latency)">, RISCVExtensionBitmask<1, 3>;
def FeatureStdExtZk
: RISCVExtension<"zk", 1, 0,
"'Zk' (Standard scalar cryptography extension)",
[FeatureStdExtZkn,
FeatureStdExtZkr,
- FeatureStdExtZkt], groupID=1, bitmaskShift=4>;
+ FeatureStdExtZkt]>, RISCVExtensionBitmask<1, 4>;
// Vector Extensions
def FeatureStdExtZvl32b : RISCVExtension<"zvl32b", 1, 0,
"'Zvl' (Minimum Vector Length) 32", [],
- "ZvlLen", "32", groupID=1, bitmaskShift=5>;
+ "ZvlLen", "32">, RISCVExtensionBitmask<1, 5>;
foreach i = { 6-16 } in {
defvar I = !shl(1, i);
@@ -614,49 +633,49 @@ foreach i = { 6-16 } in {
RISCVExtension<"zvl"#I#"b", 1, 0,
"'Zvl' (Minimum Vector Length) "#I,
[!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")],
- "ZvlLen", !cast<string>(I), groupID=1, bitmaskShift=!add(6, !sub(i, 6))>;
+ "ZvlLen", !cast<string>(I)>, RISCVExtensionBitmask<1, !add(6, !sub(i, 6))>;
}
def FeatureStdExtZve32x
: RISCVExtension<"zve32x", 1, 0,
"'Zve32x' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW)",
- [FeatureStdExtZicsr, FeatureStdExtZvl32b], groupID=1, bitmaskShift=17>;
+ [FeatureStdExtZicsr, FeatureStdExtZvl32b]>, RISCVExtensionBitmask<1, 17>;
def FeatureStdExtZve32f
: RISCVExtension<"zve32f", 1, 0,
"'Zve32f' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW and F extension)",
- [FeatureStdExtZve32x, FeatureStdExtF], groupID=1, bitmaskShift=18>;
+ [FeatureStdExtZve32x, FeatureStdExtF]>, RISCVExtensionBitmask<1, 18>;
def FeatureStdExtZve64x
: RISCVExtension<"zve64x", 1, 0,
"'Zve64x' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW)",
- [FeatureStdExtZve32x, FeatureStdExtZvl64b], groupID=1, bitmaskShift=19>;
+ [FeatureStdExtZve32x, FeatureStdExtZvl64b]>, RISCVExtensionBitmask<1, 19>;
def FeatureStdExtZve64f
: RISCVExtension<"zve64f", 1, 0,
"'Zve64f' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW and F extension)",
- [FeatureStdExtZve32f, FeatureStdExtZve64x], groupID=1, bitmaskShift=20>;
+ [FeatureStdExtZve32f, FeatureStdExtZve64x]>, RISCVExtensionBitmask<1, 20>;
def FeatureStdExtZve64d
: RISCVExtension<"zve64d", 1, 0,
"'Zve64d' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW, F and D extension)",
- [FeatureStdExtZve64f, FeatureStdExtD], groupID=1, bitmaskShift=21>;
+ [FeatureStdExtZve64f, FeatureStdExtD]>, RISCVExtensionBitmask<1, 21>;
def FeatureStdExtV
: RISCVExtension<"v", 1, 0,
"'V' (Vector Extension for Application Processors)",
- [FeatureStdExtZvl128b, FeatureStdExtZve64d], groupID=1, bitmaskShift=22>;
+ [FeatureStdExtZvl128b, FeatureStdExtZve64d]>, RISCVExtensionBitmask<1, 22>;
def FeatureStdExtZvfbfmin
: RISCVExperimentalExtension<"zvfbfmin", 1, 0,
"'Zvbfmin' (Vector BF16 Converts)",
- [FeatureStdExtZve32f], groupID=1, bitmaskShift=23>;
+ [FeatureStdExtZve32f]>, RISCVExtensionBitmask<1, 23>;
def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
"'Zvfbfmin' (Vector BF16 Converts)">;
@@ -664,7 +683,7 @@ def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
def FeatureStdExtZvfbfwma
: RISCVExperimentalExtension<"zvfbfwma", 1, 0,
"'Zvfbfwma' (Vector BF16 widening mul-add)",
- [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin], groupID=1, bitmaskShift=24>;
+ [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>, RISCVExtensionBitmask<1, 24>;
def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
"'Zvfbfwma' (Vector BF16 widening mul-add)">;
@@ -672,12 +691,12 @@ def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
def FeatureStdExtZvfhmin
: RISCVExtension<"zvfhmin", 1, 0,
"'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
- [FeatureStdExtZve32f], groupID=1, bitmaskShift=25>;
+ [FeatureStdExtZve32f]>, RISCVExtensionBitmask<1, 25>;
def FeatureStdExtZvfh
: RISCVExtension<"zvfh", 1, 0,
"'Zvfh' (Vector Half-Precision Floating-Point)",
- [FeatureStdExtZvfhmin, FeatureStdExtZfhmin], groupID=1, bitmaskShift=26>;
+ [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>, RISCVExtensionBitmask<1, 26>;
def HasStdExtZfhOrZvfh
: Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
@@ -689,7 +708,7 @@ def HasStdExtZfhOrZvfh
def FeatureStdExtZvkb
: RISCVExtension<"zvkb", 1, 0,
- "'Zvkb' (Vector Bit-manipulation used in Cryptography)", groupID=1, bitmaskShift=27>;
+ "'Zvkb' (Vector Bit-manipulation used in Cryptography)">, RISCVExtensionBitmask<1, 27>;
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
AssemblerPredicate<(all_of FeatureStdExtZvkb),
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
@@ -697,35 +716,35 @@ def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
def FeatureStdExtZvbb
: RISCVExtension<"zvbb", 1, 0,
"'Zvbb' (Vector basic bit-manipulation instructions)",
- [FeatureStdExtZvkb], groupID=1, bitmaskShift=28>;
+ [FeatureStdExtZvkb]>, RISCVExtensionBitmask<1, 28>;
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
AssemblerPredicate<(all_of FeatureStdExtZvbb),
"'Zvbb' (Vector basic bit-manipulation instructions)">;
def FeatureStdExtZvbc
: RISCVExtension<"zvbc", 1, 0,
- "'Zvbc' (Vector Carryless Multiplication)", groupID=1, bitmaskShift=29>;
+ "'Zvbc' (Vector Carryless Multiplication)">, RISCVExtensionBitmask<1, 29>;
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
AssemblerPredicate<(all_of FeatureStdExtZvbc),
"'Zvbc' (Vector Carryless Multiplication)">;
def FeatureStdExtZvkg
: RISCVExtension<"zvkg", 1, 0,
- "'Zvkg' (Vector GCM instructions for Cryptography)", groupID=1, bitmaskShift=30>;
+ "'Zvkg' (Vector GCM instructions for Cryptography)">, RISCVExtensionBitmask<1, 30>;
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
AssemblerPredicate<(all_of FeatureStdExtZvkg),
"'Zvkg' (Vector GCM instructions for Cryptography)">;
def FeatureStdExtZvkned
: RISCVExtension<"zvkned", 1, 0,
- "'Zvkned' (Vector AES Encryption & Decryption (Single Round))", groupID=1, bitmaskShift=31>;
+ "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">, RISCVExtensionBitmask<1, 31>;
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
AssemblerPredicate<(all_of FeatureStdExtZvkned),
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
def FeatureStdExtZvknha
: RISCVExtension<"zvknha", 1, 0,
- "'Zvknha' (Vector SHA-2 (SHA-256 only))", groupID=1, bitmaskShift=32>;
+ "'Zvknha' (Vector SHA-2 (SHA-256 only))">, RISCVExtensionBitmask<1, 32>;
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
AssemblerPredicate<(all_of FeatureStdExtZvknha),
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
@@ -733,7 +752,7 @@ def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
def FeatureStdExtZvknhb
: RISCVExtension<"zvknhb", 1, 0,
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
- [FeatureStdExtZve64x], groupID=1, bitmaskShift=33>;
+ [FeatureStdExtZve64x]>, RISCVExtensionBitmask<1, 33>;
def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
AssemblerPredicate<(all_of FeatureStdExtZvknhb),
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;
@@ -744,21 +763,21 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg
def FeatureStdExtZvksed
: RISCVExtension<"zvksed", 1, 0,
- "'Zvksed' (SM4 Block Cipher Instructions)", groupID=1, bitmaskShift=34>;
+ "'Zvksed' (SM4 Block Cipher Instructions)">, RISCVExtensionBitmask<1, 34>;
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
AssemblerPredicate<(all_of FeatureStdExtZvksed),
"'Zvksed' (SM4 Block Cipher Instructions)">;
def FeatureStdExtZvksh
: RISCVExtension<"zvksh", 1, 0,
- "'Zvksh' (SM3 Hash Function Instructions)", groupID=1, bitmaskShift=35>;
+ "'Zvksh' (SM3 Hash Function Instructions)">, RISCVExtensionBitmask<1, 35>;
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
AssemblerPredicate<(all_of FeatureStdExtZvksh),
"'Zvksh' (SM3 Hash Function Instructions)">;
def FeatureStdExtZvkt
: RISCVExtension<"zvkt", 1, 0,
- "'Zvkt' (Vector Data-Independent Execution Latency)", groupID=1, bitmaskShift=36>;
+ "'Zvkt' (Vector Data-Independent Execution Latency)">, RISCVExtensionBitmask<1, 36>;
// Zvk short-hand extensions
@@ -767,34 +786,34 @@ def FeatureStdExtZvkn
"'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and "
"'Zvkt')",
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
- FeatureStdExtZvkb, FeatureStdExtZvkt], groupID=1, bitmaskShift=37>;
+ FeatureStdExtZvkb, FeatureStdExtZvkt]>, RISCVExtensionBitmask<1, 37>;
def FeatureStdExtZvknc
: RISCVExtension<"zvknc", 1, 0,
"'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')",
- [FeatureStdExtZvkn, FeatureStdExtZvbc], groupID=1, bitmaskShift=38>;
+ [FeatureStdExtZvkn, FeatureStdExtZvbc]>, RISCVExtensionBitmask<1, 38>;
def FeatureStdExtZvkng
: RISCVExtension<"zvkng", 1, 0,
"'zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
- [FeatureStdExtZvkn, FeatureStdExtZvkg], groupID=1, bitmaskShift=39>;
+ [FeatureStdExtZvkn, FeatureStdExtZvkg]>, RISCVExtensionBitmask<1, 39>;
def FeatureStdExtZvks
: RISCVExtension<"zvks", 1, 0,
"'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and "
"'Zvkt')",
[FeatureStdExtZvksed, FeatureStdExtZvksh,
- FeatureStdExtZvkb, FeatureStdExtZvkt], groupID=1, bitmaskShift=40>;
+ FeatureStdExtZvkb, FeatureStdExtZvkt]>, RISCVExtensionBitmask<1, 40>;
def FeatureStdExtZvksc
: RISCVExtension<"zvksc", 1, 0,
"'Zvksc' (shorthand for 'Zvks' and 'Zvbc')",
- [FeatureStdExtZvks, FeatureStdExtZvbc], groupID=1, bitmaskShift=41>;
+ [FeatureStdExtZvks, FeatureStdExtZvbc]>, RISCVExtensionBitmask<1, 41>;
def FeatureStdExtZvksg
: RISCVExtension<"zvksg", 1, 0,
"'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
- [FeatureStdExtZvks, FeatureStdExtZvkg], groupID=1, bitmaskShift=42>;
+ [FeatureStdExtZvks, FeatureStdExtZvkg]>, RISCVExtensionBitmask<1, 42>;
// Vector instruction predicates
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 451760f2ce9c3..73b259ed242ba 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -227,7 +227,7 @@ static inline uint64_t getValueFromBitsInit(const BitsInit *B,
static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
std::vector<Record *> Extensions =
- RK.getAllDerivedDefinitionsIfDefined("RISCVExtension");
+ RK.getAllDerivedDefinitionsIfDefined("RISCVExtensionBitmask");
llvm::sort(Extensions, [](const Record *Rec1, const Record *Rec2) {
return getExtensionName(Rec1) < getExtensionName(Rec2);
});
>From 1e4bf21d15648735a1053faff25f5f00fcfcd6ec Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 6 Jun 2024 03:04:08 -0700
Subject: [PATCH 08/27] Add comment
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index f234a49ebca34..b81f981e41707 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -37,6 +37,10 @@ class RISCVExtension<string name, int major, int minor, string desc,
bit Experimental = false;
}
+// The groupID/bitmask of RISCVExtension is used to retrieve a specific bit value
+// from __riscv_feature_bit based on the groupID and bitmask.
+// gourpID - groupid of extension
+// bitmaskShift - bitmask shift of extension
class RISCVExtensionBitmask<bits<3> groupID, int bitmaskShift> {
bits<3> GroupID = groupID;
bits<64> Bitmask = !shl(1, bitmaskShift);
>From 8e0e7f73b66d3e6e700635b3d1f4c80c7b79cd57 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 6 Jun 2024 03:11:30 -0700
Subject: [PATCH 09/27] Drop skip Record without bitmask
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 4 ----
1 file changed, 4 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 73b259ed242ba..ad485ab33cebe 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -243,10 +243,6 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
assert(GroupIDBits);
assert(BitmaskBits);
- // For the extension without bitmask, skip it.
- if (!getValueFromBitsInit(BitmaskBits, *Rec))
- continue;
-
StringRef ExtName = Rec->getValueAsString("Name");
ExtName.consume_front("experimental-");
uint64_t GroupIDVal = getValueFromBitsInit(GroupIDBits, *Rec);
>From 12f52d67571f8f46b83374aca23a08bca17c0a77 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 6 Jun 2024 03:11:35 -0700
Subject: [PATCH 10/27] Update testcase
---
llvm/test/TableGen/riscv-target-def.td | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
index 58ccf24a37626..674775413c3bd 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -5,41 +5,43 @@ include "llvm/Target/Target.td"
class RISCVExtension<string name, int major, int minor, string desc,
list<SubtargetFeature> implies = [],
string fieldname = !subst("Feature", "Has", NAME),
- string value = "true", bits<3> groupID=0, int bitmaskShift=-1>
+ string value = "true">
: SubtargetFeature<name, fieldname, value, desc, implies> {
int MajorVersion = major;
int MinorVersion = minor;
bit Experimental = false;
+}
- bits<3> GroupID = groupID;
- bits<64> Bitmask = !if(!eq(bitmaskShift, -1), 0, !shl(1, bitmaskShift));
+class RISCVExtensionBitmask<bits<3> groupID, int bitmaskShift> {
+ bits<3> GroupID = groupID;
+ bits<64> Bitmask = !shl(1, bitmaskShift);
}
class RISCVExperimentalExtension<string name, int major, int minor, string desc,
list<RISCVExtension> implies = [],
string fieldname = !subst("Feature", "Has", NAME),
- string value = "true", bits<3> groupID=0, int bitmaskShift=-1>
+ string value = "true">
: RISCVExtension<"experimental-"#name, major, minor, desc, implies,
- fieldname, value, groupID, bitmaskShift> {
+ fieldname, value> {
let Experimental = true;
}
def FeatureStdExtI
: RISCVExtension<"i", 2, 1,
- "'I' (Base Integer Instruction Set)", groupID=0, bitmaskShift=0>;
+ "'I' (Base Integer Instruction Set)">, RISCVExtensionBitmask<0, 0>;
def FeatureStdExtZicsr
: RISCVExtension<"zicsr", 2, 0,
- "'zicsr' (CSRs)", groupID=0, bitmaskShift=10>;
+ "'zicsr' (CSRs)">, RISCVExtensionBitmask<0, 10>;
def FeatureStdExtZifencei
: RISCVExtension<"zifencei", 2, 0,
- "'Zifencei' (fence.i)", groupID=0, bitmaskShift=13>;
+ "'Zifencei' (fence.i)">, RISCVExtensionBitmask<0, 13>;
def FeatureStdExtF
: RISCVExtension<"f", 2, 2,
"'F' (Single-Precision Floating-Point)",
- [FeatureStdExtZicsr], groupID=0, bitmaskShift=33>;
+ [FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 33>;
def FeatureStdExtZidummy
: RISCVExperimentalExtension<"zidummy", 0, 1,
>From c5fb577b32c869ebd072d3cf17e7cfaaf31937c6 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 6 Jun 2024 18:23:40 -0700
Subject: [PATCH 11/27] drop assert for BitsInit
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 3 ---
1 file changed, 3 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index ad485ab33cebe..0d19713565bac 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -240,9 +240,6 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
BitsInit *GroupIDBits = Rec->getValueAsBitsInit("GroupID");
BitsInit *BitmaskBits = Rec->getValueAsBitsInit("Bitmask");
- assert(GroupIDBits);
- assert(BitmaskBits);
-
StringRef ExtName = Rec->getValueAsString("Name");
ExtName.consume_front("experimental-");
uint64_t GroupIDVal = getValueFromBitsInit(GroupIDBits, *Rec);
>From 0f9b5795bb143e9ede7de6f46729250f2b4b2785 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 6 Jun 2024 18:28:19 -0700
Subject: [PATCH 12/27] Use DenseSet instead DenseMap
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 0d19713565bac..e9ddca5a89020 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -232,7 +232,7 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
return getExtensionName(Rec1) < getExtensionName(Rec2);
});
- llvm::DenseMap<std::pair<uint64_t, uint64_t>, bool> Seen;
+ llvm::DenseSet<std::pair<uint64_t, uint64_t>> Seen;
OS << "#ifdef GET_RISCVExtensionBitmaskTable_IMPL\n";
OS << "static const RISCVExtensionBitmask ExtensionBitmask[]={\n";
@@ -245,9 +245,9 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
uint64_t GroupIDVal = getValueFromBitsInit(GroupIDBits, *Rec);
uint64_t BitmaskVal = getValueFromBitsInit(BitmaskBits, *Rec);
- assert(!Seen[std::make_pair(GroupIDVal, BitmaskVal)] &&
+ assert(!Seen.contains(std::make_pair(GroupIDVal, BitmaskVal)) &&
"duplicated bitmask");
- Seen[std::make_pair(GroupIDVal, BitmaskVal)] = true;
+ Seen.insert(std::make_pair(GroupIDVal, BitmaskVal));
OS << " {"
<< "\"" << ExtName << "\""
>From c23a4d368992b082f0a65365b1ed2a7ea0529223 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 6 Jun 2024 18:32:48 -0700
Subject: [PATCH 13/27] Use uint64_t instead unsigned long long
---
llvm/include/llvm/TargetParser/RISCVTargetParser.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 24755dcfec52a..8444935bd666d 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -28,7 +28,7 @@ namespace RISCVExtensionBitmaskTable {
struct RISCVExtensionBitmask {
const char *Name;
unsigned GroupID;
- unsigned long long Bitmask;
+ uint64_t Bitmask;
};
} // namespace RISCVExtensionBitmaskTable
>From 69d2196facec1a49eaf479e3f37ae99125d3729e Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 6 Jun 2024 18:33:21 -0700
Subject: [PATCH 14/27] Use groupID instead groupid
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index b81f981e41707..7f3deb3b2afd1 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -39,7 +39,7 @@ class RISCVExtension<string name, int major, int minor, string desc,
// The groupID/bitmask of RISCVExtension is used to retrieve a specific bit value
// from __riscv_feature_bit based on the groupID and bitmask.
-// gourpID - groupid of extension
+// gourpID - groupID of extension
// bitmaskShift - bitmask shift of extension
class RISCVExtensionBitmask<bits<3> groupID, int bitmaskShift> {
bits<3> GroupID = groupID;
>From b028368ef8bf2f976ef03e2b4f9263eeebf84019 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Fri, 7 Jun 2024 06:34:25 -0700
Subject: [PATCH 15/27] Add macro for sanity check
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index e9ddca5a89020..cb3e6dff510ea 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -232,7 +232,9 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
return getExtensionName(Rec1) < getExtensionName(Rec2);
});
+#ifndef NDEBUG
llvm::DenseSet<std::pair<uint64_t, uint64_t>> Seen;
+#endif
OS << "#ifdef GET_RISCVExtensionBitmaskTable_IMPL\n";
OS << "static const RISCVExtensionBitmask ExtensionBitmask[]={\n";
@@ -245,8 +247,10 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
uint64_t GroupIDVal = getValueFromBitsInit(GroupIDBits, *Rec);
uint64_t BitmaskVal = getValueFromBitsInit(BitmaskBits, *Rec);
+#ifndef NDEBUG
assert(!Seen.contains(std::make_pair(GroupIDVal, BitmaskVal)) &&
"duplicated bitmask");
+#endif
Seen.insert(std::make_pair(GroupIDVal, BitmaskVal));
OS << " {"
>From 2b6b1f4c7f37ef5bc13a869b739a65e7afe873ba Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Fri, 7 Jun 2024 06:41:21 -0700
Subject: [PATCH 16/27] Use insert return value instead contain
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index cb3e6dff510ea..737d0759f8924 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -248,10 +248,9 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
uint64_t BitmaskVal = getValueFromBitsInit(BitmaskBits, *Rec);
#ifndef NDEBUG
- assert(!Seen.contains(std::make_pair(GroupIDVal, BitmaskVal)) &&
+ assert(Seen.insert(std::make_pair(GroupIDVal, BitmaskVal)).second &&
"duplicated bitmask");
#endif
- Seen.insert(std::make_pair(GroupIDVal, BitmaskVal));
OS << " {"
<< "\"" << ExtName << "\""
>From 38971438c98fe5232aef850d03af8857babf8c44 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Fri, 7 Jun 2024 06:49:53 -0700
Subject: [PATCH 17/27] Update getValueFromBitsInit
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 737d0759f8924..fa1540d7db7a3 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -213,11 +213,11 @@ static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) {
static inline uint64_t getValueFromBitsInit(const BitsInit *B,
const Record &R) {
- assert(B->getNumBits() <= sizeof(uint64_t) * 8 && "BitInits' too long!");
+ assert(B->getNumBits() <= 64 && "BitInits' too long!");
uint64_t Value = 0;
for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
- const auto *Bit = dyn_cast<BitInit>(B->getBit(i));
+ const auto *Bit = cast<BitInit>(B->getBit(i));
if (Bit)
Value |= uint64_t(Bit->getValue()) << i;
}
>From 2122c77286ddf98299002205281cc3373d48ba1d Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Fri, 7 Jun 2024 07:27:45 -0700
Subject: [PATCH 18/27] align RISCVExtensionBitmask with RISCVExtension
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 273 ++++++++++++++++---------
llvm/test/TableGen/riscv-target-def.td | 12 +-
2 files changed, 184 insertions(+), 101 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 7f3deb3b2afd1..4587bf7d2bf4c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -62,22 +62,22 @@ class RISCVExperimentalExtension<string name, int major, int minor, string desc,
def FeatureStdExtI
: RISCVExtension<"i", 2, 1,
"'I' (Base Integer Instruction Set)">,
- RISCVExtensionBitmask<0, 0>;
+ RISCVExtensionBitmask<0, 0>;
def FeatureStdExtE
: RISCVExtension<"e", 2, 0,
"Implements RV{32,64}E (provides 16 rather than 32 GPRs)">,
- RISCVExtensionBitmask<0, 1>;
+ RISCVExtensionBitmask<0, 1>;
def FeatureStdExtZic64b
: RISCVExtension<"zic64b", 1, 0,
"'Zic64b' (Cache Block Size Is 64 Bytes)">,
- RISCVExtensionBitmask<0, 2>;
+ RISCVExtensionBitmask<0, 2>;
def FeatureStdExtZicbom
: RISCVExtension<"zicbom", 1, 0,
"'Zicbom' (Cache-Block Management Instructions)">,
- RISCVExtensionBitmask<0, 3>;
+ RISCVExtensionBitmask<0, 3>;
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
AssemblerPredicate<(all_of FeatureStdExtZicbom),
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -85,7 +85,7 @@ def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
def FeatureStdExtZicbop
: RISCVExtension<"zicbop", 1, 0,
"'Zicbop' (Cache-Block Prefetch Instructions)">,
- RISCVExtensionBitmask<0, 4>;
+ RISCVExtensionBitmask<0, 4>;
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
@@ -93,7 +93,7 @@ def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
def FeatureStdExtZicboz
: RISCVExtension<"zicboz", 1, 0,
"'Zicboz' (Cache-Block Zero Instructions)">,
- RISCVExtensionBitmask<0, 5>;
+ RISCVExtensionBitmask<0, 5>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
@@ -101,26 +101,27 @@ def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
def FeatureStdExtZiccamoa
: RISCVExtension<"ziccamoa", 1, 0,
"'Ziccamoa' (Main Memory Supports All Atomics in A)">,
- RISCVExtensionBitmask<0, 6>;
+ RISCVExtensionBitmask<0, 6>;
def FeatureStdExtZiccif
: RISCVExtension<"ziccif", 1, 0,
"'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">,
- RISCVExtensionBitmask<0, 7>;
+ RISCVExtensionBitmask<0, 7>;
def FeatureStdExtZicclsm
: RISCVExtension<"zicclsm", 1, 0,
"'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">,
- RISCVExtensionBitmask<0, 8>;
+ RISCVExtensionBitmask<0, 8>;
def FeatureStdExtZiccrse
: RISCVExtension<"ziccrse", 1, 0,
"'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">,
- RISCVExtensionBitmask<0, 9>;
+ RISCVExtensionBitmask<0, 9>;
def FeatureStdExtZicsr
: RISCVExtension<"zicsr", 2, 0,
- "'zicsr' (CSRs)">, RISCVExtensionBitmask<0, 10>;
+ "'zicsr' (CSRs)">,
+ RISCVExtensionBitmask<0, 10>;
def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
@@ -128,32 +129,37 @@ def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
def FeatureStdExtZicntr
: RISCVExtension<"zicntr", 2, 0,
"'Zicntr' (Base Counters and Timers)",
- [FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 11>;
+ [FeatureStdExtZicsr]>,
+ RISCVExtensionBitmask<0, 11>;
def FeatureStdExtZicond
: RISCVExtension<"zicond", 1, 0,
- "'Zicond' (Integer Conditional Operations)">, RISCVExtensionBitmask<0, 12>;
+ "'Zicond' (Integer Conditional Operations)">,
+ RISCVExtensionBitmask<0, 12>;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
def FeatureStdExtZifencei
: RISCVExtension<"zifencei", 2, 0,
- "'Zifencei' (fence.i)">, RISCVExtensionBitmask<0, 13>;
+ "'Zifencei' (fence.i)">,
+ RISCVExtensionBitmask<0, 13>;
def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
def FeatureStdExtZihintpause
: RISCVExtension<"zihintpause", 2, 0,
- "'Zihintpause' (Pause Hint)">, RISCVExtensionBitmask<0, 14>;
+ "'Zihintpause' (Pause Hint)">,
+ RISCVExtensionBitmask<0, 14>;
def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
AssemblerPredicate<(all_of FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
def FeatureStdExtZihintntl
: RISCVExtension<"zihintntl", 1, 0,
- "'Zihintntl' (Non-Temporal Locality Hints)">, RISCVExtensionBitmask<0, 15>;
+ "'Zihintntl' (Non-Temporal Locality Hints)">,
+ RISCVExtensionBitmask<0, 15>;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -161,10 +167,12 @@ def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
def FeatureStdExtZihpm
: RISCVExtension<"zihpm", 2, 0,
"'Zihpm' (Hardware Performance Counters)",
- [FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 16>;
+ [FeatureStdExtZicsr]>,
+ RISCVExtensionBitmask<0, 16>;
def FeatureStdExtZimop : RISCVExtension<"zimop", 1, 0,
- "'Zimop' (May-Be-Operations)">, RISCVExtensionBitmask<0, 17>;
+ "'Zimop' (May-Be-Operations)">,
+ RISCVExtensionBitmask<0, 17>;
def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
@@ -172,7 +180,8 @@ def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
def FeatureStdExtZicfilp
: RISCVExperimentalExtension<"zicfilp", 0, 4,
"'Zicfilp' (Landing pad)",
- [FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 18>;
+ [FeatureStdExtZicsr]>,
+ RISCVExtensionBitmask<0, 18>;
def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
AssemblerPredicate<(all_of FeatureStdExtZicfilp),
"'Zicfilp' (Landing pad)">;
@@ -183,7 +192,7 @@ def FeatureStdExtZicfiss
: RISCVExperimentalExtension<"zicfiss", 0, 4,
"'Zicfiss' (Shadow stack)",
[FeatureStdExtZicsr, FeatureStdExtZimop]>,
- RISCVExtensionBitmask<0, 19>;
+ RISCVExtensionBitmask<0, 19>;
def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
AssemblerPredicate<(all_of FeatureStdExtZicfiss),
"'Zicfiss' (Shadow stack)">;
@@ -193,14 +202,16 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
def FeatureStdExtM
: RISCVExtension<"m", 2, 0,
- "'M' (Integer Multiplication and Division)">, RISCVExtensionBitmask<0, 20>;
+ "'M' (Integer Multiplication and Division)">,
+ RISCVExtensionBitmask<0, 20>;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;
def FeatureStdExtZmmul
: RISCVExtension<"zmmul", 1, 0,
- "'Zmmul' (Integer Multiplication)">, RISCVExtensionBitmask<0, 21>;
+ "'Zmmul' (Integer Multiplication)">,
+ RISCVExtensionBitmask<0, 21>;
def HasStdExtMOrZmmul
: Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
@@ -212,7 +223,8 @@ def HasStdExtMOrZmmul
def FeatureStdExtA
: RISCVExtension<"a", 2, 1,
- "'A' (Atomic Instructions)">, RISCVExtensionBitmask<0, 22>;
+ "'A' (Atomic Instructions)">,
+ RISCVExtensionBitmask<0, 22>;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<(all_of FeatureStdExtA),
"'A' (Atomic Instructions)">;
@@ -220,7 +232,7 @@ def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
def FeatureStdExtZtso
: RISCVExperimentalExtension<"ztso", 0, 1,
"'Ztso' (Memory Model - Total Store Order)">,
- RISCVExtensionBitmask<0, 23>;
+ RISCVExtensionBitmask<0, 23>;
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
@@ -228,15 +240,16 @@ def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
def FeatureStdExtZa64rs : RISCVExtension<"za64rs", 1, 0,
"'Za64rs' (Reservation Set Size of at Most 64 Bytes)">,
- RISCVExtensionBitmask<0, 24>;
+ RISCVExtensionBitmask<0, 24>;
def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
"'Za128rs' (Reservation Set Size of at Most 128 Bytes)">,
- RISCVExtensionBitmask<0, 25>;
+ RISCVExtensionBitmask<0, 25>;
def FeatureStdExtZaamo
: RISCVExtension<"zaamo", 1, 0,
- "'Zaamo' (Atomic Memory Operations)">, RISCVExtensionBitmask<0, 26>;
+ "'Zaamo' (Atomic Memory Operations)">,
+ RISCVExtensionBitmask<0, 26>;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -245,14 +258,16 @@ def HasStdExtAOrZaamo
def FeatureStdExtZabha
: RISCVExtension<"zabha", 1, 0,
- "'Zabha' (Byte and Halfword Atomic Memory Operations)">, RISCVExtensionBitmask<0, 27>;
+ "'Zabha' (Byte and Halfword Atomic Memory Operations)">,
+ RISCVExtensionBitmask<0, 27>;
def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
AssemblerPredicate<(all_of FeatureStdExtZabha),
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
def FeatureStdExtZacas
: RISCVExtension<"zacas", 1, 0,
- "'Zacas' (Atomic Compare-And-Swap Instructions)">, RISCVExtensionBitmask<0, 28>;
+ "'Zacas' (Atomic Compare-And-Swap Instructions)">,
+ RISCVExtensionBitmask<0, 28>;
def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
AssemblerPredicate<(all_of FeatureStdExtZacas),
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
@@ -261,14 +276,15 @@ def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
def FeatureStdExtZalasr
: RISCVExperimentalExtension<"zalasr", 0, 1,
"'Zalasr' (Load-Acquire and Store-Release Instructions)">,
- RISCVExtensionBitmask<0, 29>;
+ RISCVExtensionBitmask<0, 29>;
def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
AssemblerPredicate<(all_of FeatureStdExtZalasr),
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
def FeatureStdExtZalrsc
: RISCVExtension<"zalrsc", 1, 0,
- "'Zalrsc' (Load-Reserved/Store-Conditional)">, RISCVExtensionBitmask<0, 30>;
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">,
+ RISCVExtensionBitmask<0, 30>;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
@@ -278,11 +294,11 @@ def HasStdExtAOrZalrsc
def FeatureStdExtZama16b
: RISCVExtension<"zama16b", 1, 0,
"'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">,
- RISCVExtensionBitmask<0, 31>;
+ RISCVExtensionBitmask<0, 31>;
def FeatureStdExtZawrs : RISCVExtension<"zawrs", 1, 0,
"'Zawrs' (Wait on Reservation Set)">,
- RISCVExtensionBitmask<0, 32>;
+ RISCVExtensionBitmask<0, 32>;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
AssemblerPredicate<(all_of FeatureStdExtZawrs),
"'Zawrs' (Wait on Reservation Set)">;
@@ -292,7 +308,8 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
def FeatureStdExtF
: RISCVExtension<"f", 2, 2,
"'F' (Single-Precision Floating-Point)",
- [FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 33>;
+ [FeatureStdExtZicsr]>,
+ RISCVExtensionBitmask<0, 33>;
def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
AssemblerPredicate<(all_of FeatureStdExtF),
"'F' (Single-Precision Floating-Point)">;
@@ -300,7 +317,8 @@ def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
def FeatureStdExtD
: RISCVExtension<"d", 2, 2,
"'D' (Double-Precision Floating-Point)",
- [FeatureStdExtF]>, RISCVExtensionBitmask<0, 34>;
+ [FeatureStdExtF]>,
+ RISCVExtensionBitmask<0, 34>;
def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
AssemblerPredicate<(all_of FeatureStdExtD),
"'D' (Double-Precision Floating-Point)">;
@@ -308,7 +326,8 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
def FeatureStdExtZfhmin
: RISCVExtension<"zfhmin", 1, 0,
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
- [FeatureStdExtF]>, RISCVExtensionBitmask<0, 35>;
+ [FeatureStdExtF]>,
+ RISCVExtensionBitmask<0, 35>;
def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfhmin),
"'Zfh' (Half-Precision Floating-Point) or "
@@ -317,7 +336,8 @@ def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
def FeatureStdExtZfh
: RISCVExtension<"zfh", 1, 0,
"'Zfh' (Half-Precision Floating-Point)",
- [FeatureStdExtZfhmin]>, RISCVExtensionBitmask<0, 36>;
+ [FeatureStdExtZfhmin]>,
+ RISCVExtensionBitmask<0, 36>;
def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
AssemblerPredicate<(all_of FeatureStdExtZfh),
"'Zfh' (Half-Precision Floating-Point)">;
@@ -326,7 +346,8 @@ def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
def FeatureStdExtZfbfmin
: RISCVExperimentalExtension<"zfbfmin", 1, 0,
"'Zfbfmin' (Scalar BF16 Converts)",
- [FeatureStdExtF]>, RISCVExtensionBitmask<0, 37>;
+ [FeatureStdExtF]>,
+ RISCVExtensionBitmask<0, 37>;
def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
"'Zfbfmin' (Scalar BF16 Converts)">;
@@ -342,7 +363,8 @@ def HasHalfFPLoadStoreMove
def FeatureStdExtZfa
: RISCVExtension<"zfa", 1, 0,
"'Zfa' (Additional Floating-Point)",
- [FeatureStdExtF]>, RISCVExtensionBitmask<0, 38>;
+ [FeatureStdExtF]>,
+ RISCVExtensionBitmask<0, 38>;
def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
AssemblerPredicate<(all_of FeatureStdExtZfa),
"'Zfa' (Additional Floating-Point)">;
@@ -350,7 +372,8 @@ def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
def FeatureStdExtZfinx
: RISCVExtension<"zfinx", 1, 0,
"'Zfinx' (Float in Integer)",
- [FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 39>;
+ [FeatureStdExtZicsr]>,
+ RISCVExtensionBitmask<0, 39>;
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
AssemblerPredicate<(all_of FeatureStdExtZfinx),
"'Zfinx' (Float in Integer)">;
@@ -358,7 +381,8 @@ def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
def FeatureStdExtZdinx
: RISCVExtension<"zdinx", 1, 0,
"'Zdinx' (Double in Integer)",
- [FeatureStdExtZfinx]>, RISCVExtensionBitmask<0, 40>;
+ [FeatureStdExtZfinx]>,
+ RISCVExtensionBitmask<0, 40>;
def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
AssemblerPredicate<(all_of FeatureStdExtZdinx),
"'Zdinx' (Double in Integer)">;
@@ -366,7 +390,8 @@ def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
def FeatureStdExtZhinxmin
: RISCVExtension<"zhinxmin", 1, 0,
"'Zhinxmin' (Half Float in Integer Minimal)",
- [FeatureStdExtZfinx]>, RISCVExtensionBitmask<0, 41>;
+ [FeatureStdExtZfinx]>,
+ RISCVExtensionBitmask<0, 41>;
def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
"'Zhinx' (Half Float in Integer) or "
@@ -375,7 +400,8 @@ def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
def FeatureStdExtZhinx
: RISCVExtension<"zhinx", 1, 0,
"'Zhinx' (Half Float in Integer)",
- [FeatureStdExtZhinxmin]>, RISCVExtensionBitmask<0, 42>;
+ [FeatureStdExtZhinxmin]>,
+ RISCVExtensionBitmask<0, 42>;
def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
AssemblerPredicate<(all_of FeatureStdExtZhinx),
"'Zhinx' (Half Float in Integer)">;
@@ -385,7 +411,8 @@ def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
def FeatureStdExtC
: RISCVExtension<"c", 2, 0,
- "'C' (Compressed Instructions)">, RISCVExtensionBitmask<0, 43>;
+ "'C' (Compressed Instructions)">,
+ RISCVExtensionBitmask<0, 43>;
def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtC),
"'C' (Compressed Instructions)">;
@@ -400,7 +427,8 @@ def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
def FeatureStdExtZca
: RISCVExtension<"zca", 1, 0,
"'Zca' (part of the C extension, excluding compressed "
- "floating point loads/stores)">, RISCVExtensionBitmask<0, 44>;
+ "floating point loads/stores)">,
+ RISCVExtensionBitmask<0, 44>;
def HasStdExtCOrZca
: Predicate<"Subtarget->hasStdExtCOrZca()">,
@@ -412,7 +440,8 @@ def HasStdExtCOrZca
def FeatureStdExtZcb
: RISCVExtension<"zcb", 1, 0,
"'Zcb' (Compressed basic bit manipulation instructions)",
- [FeatureStdExtZca]>, RISCVExtensionBitmask<0, 45>;
+ [FeatureStdExtZca]>,
+ RISCVExtensionBitmask<0, 45>;
def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
AssemblerPredicate<(all_of FeatureStdExtZcb),
"'Zcb' (Compressed basic bit manipulation instructions)">;
@@ -420,7 +449,8 @@ def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
def FeatureStdExtZcd
: RISCVExtension<"zcd", 1, 0,
"'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
- [FeatureStdExtD, FeatureStdExtZca]>, RISCVExtensionBitmask<0, 46>;
+ [FeatureStdExtD, FeatureStdExtZca]>,
+ RISCVExtensionBitmask<0, 46>;
def HasStdExtCOrZcd
: Predicate<"Subtarget->hasStdExtCOrZcd()">,
@@ -431,12 +461,14 @@ def HasStdExtCOrZcd
def FeatureStdExtZcf
: RISCVExtension<"zcf", 1, 0,
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
- [FeatureStdExtF, FeatureStdExtZca]>, RISCVExtensionBitmask<0, 47>;
+ [FeatureStdExtF, FeatureStdExtZca]>,
+ RISCVExtensionBitmask<0, 47>;
def FeatureStdExtZcmp
: RISCVExtension<"zcmp", 1, 0,
"'Zcmp' (sequenced instuctions for code-size reduction)",
- [FeatureStdExtZca]>, RISCVExtensionBitmask<0, 48>;
+ [FeatureStdExtZca]>,
+ RISCVExtensionBitmask<0, 48>;
def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtZcmp),
"'Zcmp' (sequenced instuctions for code-size reduction)">;
@@ -444,7 +476,8 @@ def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdE
def FeatureStdExtZcmt
: RISCVExtension<"zcmt", 1, 0,
"'Zcmt' (table jump instuctions for code-size reduction)",
- [FeatureStdExtZca, FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 49>;
+ [FeatureStdExtZca, FeatureStdExtZicsr]>,
+ RISCVExtensionBitmask<0, 49>;
def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
AssemblerPredicate<(all_of FeatureStdExtZcmt),
"'Zcmt' (table jump instuctions for code-size reduction)">;
@@ -453,7 +486,7 @@ def FeatureStdExtZce
: RISCVExtension<"zce", 1, 0,
"'Zce' (Compressed extensions for microcontrollers)",
[FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>,
- RISCVExtensionBitmask<0, 50>;
+ RISCVExtensionBitmask<0, 50>;
def HasStdExtCOrZcfOrZce
: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
@@ -466,7 +499,8 @@ def HasStdExtCOrZcfOrZce
def FeatureStdExtZcmop
: RISCVExtension<"zcmop", 1, 0,
"'Zcmop' (Compressed May-Be-Operations)",
- [FeatureStdExtZca]>, RISCVExtensionBitmask<0, 51>;
+ [FeatureStdExtZca]>,
+ RISCVExtensionBitmask<0, 51>;
def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
AssemblerPredicate<(all_of FeatureStdExtZcmop),
"'Zcmop' (Compressed May-Be-Operations)">;
@@ -475,7 +509,8 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
def FeatureStdExtZba
: RISCVExtension<"zba", 1, 0,
- "'Zba' (Address Generation Instructions)">, RISCVExtensionBitmask<0, 52>;
+ "'Zba' (Address Generation Instructions)">,
+ RISCVExtensionBitmask<0, 52>;
def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
AssemblerPredicate<(all_of FeatureStdExtZba),
"'Zba' (Address Generation Instructions)">;
@@ -483,21 +518,24 @@ def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
def FeatureStdExtZbb
: RISCVExtension<"zbb", 1, 0,
- "'Zbb' (Basic Bit-Manipulation)">, RISCVExtensionBitmask<0, 53>;
+ "'Zbb' (Basic Bit-Manipulation)">,
+ RISCVExtensionBitmask<0, 53>;
def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
AssemblerPredicate<(all_of FeatureStdExtZbb),
"'Zbb' (Basic Bit-Manipulation)">;
def FeatureStdExtZbc
: RISCVExtension<"zbc", 1, 0,
- "'Zbc' (Carry-Less Multiplication)">, RISCVExtensionBitmask<0, 54>;
+ "'Zbc' (Carry-Less Multiplication)">,
+ RISCVExtensionBitmask<0, 54>;
def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
AssemblerPredicate<(all_of FeatureStdExtZbc),
"'Zbc' (Carry-Less Multiplication)">;
def FeatureStdExtZbs
: RISCVExtension<"zbs", 1, 0,
- "'Zbs' (Single-Bit Instructions)">, RISCVExtensionBitmask<0, 55>;
+ "'Zbs' (Single-Bit Instructions)">,
+ RISCVExtensionBitmask<0, 55>;
def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
AssemblerPredicate<(all_of FeatureStdExtZbs),
"'Zbs' (Single-Bit Instructions)">;
@@ -506,14 +544,16 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
def FeatureStdExtZbkb
: RISCVExtension<"zbkb", 1, 0,
- "'Zbkb' (Bitmanip instructions for Cryptography)">, RISCVExtensionBitmask<0, 56>;
+ "'Zbkb' (Bitmanip instructions for Cryptography)">,
+ RISCVExtensionBitmask<0, 56>;
def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
AssemblerPredicate<(all_of FeatureStdExtZbkb),
"'Zbkb' (Bitmanip instructions for Cryptography)">;
def FeatureStdExtZbkx
: RISCVExtension<"zbkx", 1, 0,
- "'Zbkx' (Crossbar permutation instructions)">, RISCVExtensionBitmask<0, 57>;
+ "'Zbkx' (Crossbar permutation instructions)">,
+ RISCVExtensionBitmask<0, 57>;
def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
AssemblerPredicate<(all_of FeatureStdExtZbkx),
"'Zbkx' (Crossbar permutation instructions)">;
@@ -530,7 +570,8 @@ def HasStdExtZbbOrZbkb
def FeatureStdExtZbkc
: RISCVExtension<"zbkc", 1, 0,
"'Zbkc' (Carry-less multiply instructions for "
- "Cryptography)">, RISCVExtensionBitmask<0, 58>;
+ "Cryptography)">,
+ RISCVExtensionBitmask<0, 58>;
def HasStdExtZbkc
: Predicate<"Subtarget->hasStdExtZbkc()">,
AssemblerPredicate<(all_of FeatureStdExtZbkc),
@@ -547,14 +588,16 @@ def HasStdExtZbcOrZbkc
def FeatureStdExtZknd
: RISCVExtension<"zknd", 1, 0,
- "'Zknd' (NIST Suite: AES Decryption)">, RISCVExtensionBitmask<0, 59>;
+ "'Zknd' (NIST Suite: AES Decryption)">,
+ RISCVExtensionBitmask<0, 59>;
def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
AssemblerPredicate<(all_of FeatureStdExtZknd),
"'Zknd' (NIST Suite: AES Decryption)">;
def FeatureStdExtZkne
: RISCVExtension<"zkne", 1, 0,
- "'Zkne' (NIST Suite: AES Encryption)">, RISCVExtensionBitmask<0, 60>;
+ "'Zkne' (NIST Suite: AES Encryption)">,
+ RISCVExtensionBitmask<0, 60>;
def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
AssemblerPredicate<(all_of FeatureStdExtZkne),
"'Zkne' (NIST Suite: AES Encryption)">;
@@ -569,28 +612,32 @@ def HasStdExtZkndOrZkne
def FeatureStdExtZknh
: RISCVExtension<"zknh", 1, 0,
- "'Zknh' (NIST Suite: Hash Function Instructions)">, RISCVExtensionBitmask<0, 61>;
+ "'Zknh' (NIST Suite: Hash Function Instructions)">,
+ RISCVExtensionBitmask<0, 61>;
def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
AssemblerPredicate<(all_of FeatureStdExtZknh),
"'Zknh' (NIST Suite: Hash Function Instructions)">;
def FeatureStdExtZksed
: RISCVExtension<"zksed", 1, 0,
- "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">, RISCVExtensionBitmask<0, 62>;
+ "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">,
+ RISCVExtensionBitmask<0, 62>;
def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
AssemblerPredicate<(all_of FeatureStdExtZksed),
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
def FeatureStdExtZksh
: RISCVExtension<"zksh", 1, 0,
- "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">, RISCVExtensionBitmask<0, 63>;
+ "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">,
+ RISCVExtensionBitmask<0, 63>;
def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
AssemblerPredicate<(all_of FeatureStdExtZksh),
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
def FeatureStdExtZkr
: RISCVExtension<"zkr", 1, 0,
- "'Zkr' (Entropy Source Extension)">, RISCVExtensionBitmask<1, 0>;
+ "'Zkr' (Entropy Source Extension)">,
+ RISCVExtensionBitmask<1, 0>;
def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
AssemblerPredicate<(all_of FeatureStdExtZkr),
"'Zkr' (Entropy Source Extension)">;
@@ -603,7 +650,8 @@ def FeatureStdExtZkn
FeatureStdExtZbkx,
FeatureStdExtZkne,
FeatureStdExtZknd,
- FeatureStdExtZknh]>, RISCVExtensionBitmask<1, 1>;
+ FeatureStdExtZknh]>,
+ RISCVExtensionBitmask<1, 1>;
def FeatureStdExtZks
: RISCVExtension<"zks", 1, 0,
@@ -612,24 +660,28 @@ def FeatureStdExtZks
FeatureStdExtZbkc,
FeatureStdExtZbkx,
FeatureStdExtZksed,
- FeatureStdExtZksh]>, RISCVExtensionBitmask<1, 2>;
+ FeatureStdExtZksh]>,
+ RISCVExtensionBitmask<1, 2>;
def FeatureStdExtZkt
: RISCVExtension<"zkt", 1, 0,
- "'Zkt' (Data Independent Execution Latency)">, RISCVExtensionBitmask<1, 3>;
+ "'Zkt' (Data Independent Execution Latency)">,
+ RISCVExtensionBitmask<1, 3>;
def FeatureStdExtZk
: RISCVExtension<"zk", 1, 0,
"'Zk' (Standard scalar cryptography extension)",
[FeatureStdExtZkn,
FeatureStdExtZkr,
- FeatureStdExtZkt]>, RISCVExtensionBitmask<1, 4>;
+ FeatureStdExtZkt]>,
+ RISCVExtensionBitmask<1, 4>;
// Vector Extensions
def FeatureStdExtZvl32b : RISCVExtension<"zvl32b", 1, 0,
"'Zvl' (Minimum Vector Length) 32", [],
- "ZvlLen", "32">, RISCVExtensionBitmask<1, 5>;
+ "ZvlLen", "32">,
+ RISCVExtensionBitmask<1, 5>;
foreach i = { 6-16 } in {
defvar I = !shl(1, i);
@@ -637,49 +689,57 @@ foreach i = { 6-16 } in {
RISCVExtension<"zvl"#I#"b", 1, 0,
"'Zvl' (Minimum Vector Length) "#I,
[!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")],
- "ZvlLen", !cast<string>(I)>, RISCVExtensionBitmask<1, !add(6, !sub(i, 6))>;
+ "ZvlLen", !cast<string>(I)>,
+ RISCVExtensionBitmask<1, !add(6, !sub(i, 6))>;
}
def FeatureStdExtZve32x
: RISCVExtension<"zve32x", 1, 0,
"'Zve32x' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW)",
- [FeatureStdExtZicsr, FeatureStdExtZvl32b]>, RISCVExtensionBitmask<1, 17>;
+ [FeatureStdExtZicsr, FeatureStdExtZvl32b]>,
+ RISCVExtensionBitmask<1, 17>;
def FeatureStdExtZve32f
: RISCVExtension<"zve32f", 1, 0,
"'Zve32f' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW and F extension)",
- [FeatureStdExtZve32x, FeatureStdExtF]>, RISCVExtensionBitmask<1, 18>;
+ [FeatureStdExtZve32x, FeatureStdExtF]>,
+ RISCVExtensionBitmask<1, 18>;
def FeatureStdExtZve64x
: RISCVExtension<"zve64x", 1, 0,
"'Zve64x' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW)",
- [FeatureStdExtZve32x, FeatureStdExtZvl64b]>, RISCVExtensionBitmask<1, 19>;
+ [FeatureStdExtZve32x, FeatureStdExtZvl64b]>,
+ RISCVExtensionBitmask<1, 19>;
def FeatureStdExtZve64f
: RISCVExtension<"zve64f", 1, 0,
"'Zve64f' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW and F extension)",
- [FeatureStdExtZve32f, FeatureStdExtZve64x]>, RISCVExtensionBitmask<1, 20>;
+ [FeatureStdExtZve32f, FeatureStdExtZve64x]>,
+ RISCVExtensionBitmask<1, 20>;
def FeatureStdExtZve64d
: RISCVExtension<"zve64d", 1, 0,
"'Zve64d' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW, F and D extension)",
- [FeatureStdExtZve64f, FeatureStdExtD]>, RISCVExtensionBitmask<1, 21>;
+ [FeatureStdExtZve64f, FeatureStdExtD]>,
+ RISCVExtensionBitmask<1, 21>;
def FeatureStdExtV
: RISCVExtension<"v", 1, 0,
"'V' (Vector Extension for Application Processors)",
- [FeatureStdExtZvl128b, FeatureStdExtZve64d]>, RISCVExtensionBitmask<1, 22>;
+ [FeatureStdExtZvl128b, FeatureStdExtZve64d]>,
+ RISCVExtensionBitmask<1, 22>;
def FeatureStdExtZvfbfmin
: RISCVExperimentalExtension<"zvfbfmin", 1, 0,
"'Zvbfmin' (Vector BF16 Converts)",
- [FeatureStdExtZve32f]>, RISCVExtensionBitmask<1, 23>;
+ [FeatureStdExtZve32f]>,
+ RISCVExtensionBitmask<1, 23>;
def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
"'Zvfbfmin' (Vector BF16 Converts)">;
@@ -687,7 +747,8 @@ def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
def FeatureStdExtZvfbfwma
: RISCVExperimentalExtension<"zvfbfwma", 1, 0,
"'Zvfbfwma' (Vector BF16 widening mul-add)",
- [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>, RISCVExtensionBitmask<1, 24>;
+ [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>,
+ RISCVExtensionBitmask<1, 24>;
def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
"'Zvfbfwma' (Vector BF16 widening mul-add)">;
@@ -695,12 +756,14 @@ def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
def FeatureStdExtZvfhmin
: RISCVExtension<"zvfhmin", 1, 0,
"'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
- [FeatureStdExtZve32f]>, RISCVExtensionBitmask<1, 25>;
+ [FeatureStdExtZve32f]>,
+ RISCVExtensionBitmask<1, 25>;
def FeatureStdExtZvfh
: RISCVExtension<"zvfh", 1, 0,
"'Zvfh' (Vector Half-Precision Floating-Point)",
- [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>, RISCVExtensionBitmask<1, 26>;
+ [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>,
+ RISCVExtensionBitmask<1, 26>;
def HasStdExtZfhOrZvfh
: Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
@@ -712,7 +775,8 @@ def HasStdExtZfhOrZvfh
def FeatureStdExtZvkb
: RISCVExtension<"zvkb", 1, 0,
- "'Zvkb' (Vector Bit-manipulation used in Cryptography)">, RISCVExtensionBitmask<1, 27>;
+ "'Zvkb' (Vector Bit-manipulation used in Cryptography)">,
+ RISCVExtensionBitmask<1, 27>;
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
AssemblerPredicate<(all_of FeatureStdExtZvkb),
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
@@ -720,35 +784,40 @@ def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
def FeatureStdExtZvbb
: RISCVExtension<"zvbb", 1, 0,
"'Zvbb' (Vector basic bit-manipulation instructions)",
- [FeatureStdExtZvkb]>, RISCVExtensionBitmask<1, 28>;
+ [FeatureStdExtZvkb]>,
+ RISCVExtensionBitmask<1, 28>;
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
AssemblerPredicate<(all_of FeatureStdExtZvbb),
"'Zvbb' (Vector basic bit-manipulation instructions)">;
def FeatureStdExtZvbc
: RISCVExtension<"zvbc", 1, 0,
- "'Zvbc' (Vector Carryless Multiplication)">, RISCVExtensionBitmask<1, 29>;
+ "'Zvbc' (Vector Carryless Multiplication)">,
+ RISCVExtensionBitmask<1, 29>;
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
AssemblerPredicate<(all_of FeatureStdExtZvbc),
"'Zvbc' (Vector Carryless Multiplication)">;
def FeatureStdExtZvkg
: RISCVExtension<"zvkg", 1, 0,
- "'Zvkg' (Vector GCM instructions for Cryptography)">, RISCVExtensionBitmask<1, 30>;
+ "'Zvkg' (Vector GCM instructions for Cryptography)">,
+ RISCVExtensionBitmask<1, 30>;
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
AssemblerPredicate<(all_of FeatureStdExtZvkg),
"'Zvkg' (Vector GCM instructions for Cryptography)">;
def FeatureStdExtZvkned
: RISCVExtension<"zvkned", 1, 0,
- "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">, RISCVExtensionBitmask<1, 31>;
+ "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">,
+ RISCVExtensionBitmask<1, 31>;
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
AssemblerPredicate<(all_of FeatureStdExtZvkned),
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
def FeatureStdExtZvknha
: RISCVExtension<"zvknha", 1, 0,
- "'Zvknha' (Vector SHA-2 (SHA-256 only))">, RISCVExtensionBitmask<1, 32>;
+ "'Zvknha' (Vector SHA-2 (SHA-256 only))">,
+ RISCVExtensionBitmask<1, 32>;
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
AssemblerPredicate<(all_of FeatureStdExtZvknha),
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
@@ -756,7 +825,8 @@ def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
def FeatureStdExtZvknhb
: RISCVExtension<"zvknhb", 1, 0,
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
- [FeatureStdExtZve64x]>, RISCVExtensionBitmask<1, 33>;
+ [FeatureStdExtZve64x]>,
+ RISCVExtensionBitmask<1, 33>;
def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
AssemblerPredicate<(all_of FeatureStdExtZvknhb),
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;
@@ -767,21 +837,24 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg
def FeatureStdExtZvksed
: RISCVExtension<"zvksed", 1, 0,
- "'Zvksed' (SM4 Block Cipher Instructions)">, RISCVExtensionBitmask<1, 34>;
+ "'Zvksed' (SM4 Block Cipher Instructions)">,
+ RISCVExtensionBitmask<1, 34>;
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
AssemblerPredicate<(all_of FeatureStdExtZvksed),
"'Zvksed' (SM4 Block Cipher Instructions)">;
def FeatureStdExtZvksh
: RISCVExtension<"zvksh", 1, 0,
- "'Zvksh' (SM3 Hash Function Instructions)">, RISCVExtensionBitmask<1, 35>;
+ "'Zvksh' (SM3 Hash Function Instructions)">,
+ RISCVExtensionBitmask<1, 35>;
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
AssemblerPredicate<(all_of FeatureStdExtZvksh),
"'Zvksh' (SM3 Hash Function Instructions)">;
def FeatureStdExtZvkt
: RISCVExtension<"zvkt", 1, 0,
- "'Zvkt' (Vector Data-Independent Execution Latency)">, RISCVExtensionBitmask<1, 36>;
+ "'Zvkt' (Vector Data-Independent Execution Latency)">,
+ RISCVExtensionBitmask<1, 36>;
// Zvk short-hand extensions
@@ -790,34 +863,40 @@ def FeatureStdExtZvkn
"'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and "
"'Zvkt')",
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
- FeatureStdExtZvkb, FeatureStdExtZvkt]>, RISCVExtensionBitmask<1, 37>;
+ FeatureStdExtZvkb, FeatureStdExtZvkt]>,
+ RISCVExtensionBitmask<1, 37>;
def FeatureStdExtZvknc
: RISCVExtension<"zvknc", 1, 0,
"'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')",
- [FeatureStdExtZvkn, FeatureStdExtZvbc]>, RISCVExtensionBitmask<1, 38>;
+ [FeatureStdExtZvkn, FeatureStdExtZvbc]>,
+ RISCVExtensionBitmask<1, 38>;
def FeatureStdExtZvkng
: RISCVExtension<"zvkng", 1, 0,
"'zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
- [FeatureStdExtZvkn, FeatureStdExtZvkg]>, RISCVExtensionBitmask<1, 39>;
+ [FeatureStdExtZvkn, FeatureStdExtZvkg]>,
+ RISCVExtensionBitmask<1, 39>;
def FeatureStdExtZvks
: RISCVExtension<"zvks", 1, 0,
"'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and "
"'Zvkt')",
[FeatureStdExtZvksed, FeatureStdExtZvksh,
- FeatureStdExtZvkb, FeatureStdExtZvkt]>, RISCVExtensionBitmask<1, 40>;
+ FeatureStdExtZvkb, FeatureStdExtZvkt]>,
+ RISCVExtensionBitmask<1, 40>;
def FeatureStdExtZvksc
: RISCVExtension<"zvksc", 1, 0,
"'Zvksc' (shorthand for 'Zvks' and 'Zvbc')",
- [FeatureStdExtZvks, FeatureStdExtZvbc]>, RISCVExtensionBitmask<1, 41>;
+ [FeatureStdExtZvks, FeatureStdExtZvbc]>,
+ RISCVExtensionBitmask<1, 41>;
def FeatureStdExtZvksg
: RISCVExtension<"zvksg", 1, 0,
"'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
- [FeatureStdExtZvks, FeatureStdExtZvkg]>, RISCVExtensionBitmask<1, 42>;
+ [FeatureStdExtZvks, FeatureStdExtZvkg]>,
+ RISCVExtensionBitmask<1, 42>;
// Vector instruction predicates
diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
index 674775413c3bd..2303c1f4bf37f 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -28,20 +28,24 @@ class RISCVExperimentalExtension<string name, int major, int minor, string desc,
def FeatureStdExtI
: RISCVExtension<"i", 2, 1,
- "'I' (Base Integer Instruction Set)">, RISCVExtensionBitmask<0, 0>;
+ "'I' (Base Integer Instruction Set)">,
+ RISCVExtensionBitmask<0, 0>;
def FeatureStdExtZicsr
: RISCVExtension<"zicsr", 2, 0,
- "'zicsr' (CSRs)">, RISCVExtensionBitmask<0, 10>;
+ "'zicsr' (CSRs)">,
+ RISCVExtensionBitmask<0, 10>;
def FeatureStdExtZifencei
: RISCVExtension<"zifencei", 2, 0,
- "'Zifencei' (fence.i)">, RISCVExtensionBitmask<0, 13>;
+ "'Zifencei' (fence.i)">,
+ RISCVExtensionBitmask<0, 13>;
def FeatureStdExtF
: RISCVExtension<"f", 2, 2,
"'F' (Single-Precision Floating-Point)",
- [FeatureStdExtZicsr]>, RISCVExtensionBitmask<0, 33>;
+ [FeatureStdExtZicsr]>,
+ RISCVExtensionBitmask<0, 33>;
def FeatureStdExtZidummy
: RISCVExperimentalExtension<"zidummy", 0, 1,
>From 286b06b07357fde2b33da4a4ebfbd7dd33db2996 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 12 Jun 2024 22:43:17 -0700
Subject: [PATCH 19/27] Remove some bitmask due to no way to check it from
platform
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 235 ++++++++++---------------
1 file changed, 97 insertions(+), 138 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 4587bf7d2bf4c..4072f1aff9746 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -62,30 +62,27 @@ class RISCVExperimentalExtension<string name, int major, int minor, string desc,
def FeatureStdExtI
: RISCVExtension<"i", 2, 1,
"'I' (Base Integer Instruction Set)">,
- RISCVExtensionBitmask<0, 0>;
+ RISCVExtensionBitmask<0, 8>;
def FeatureStdExtE
: RISCVExtension<"e", 2, 0,
"Implements RV{32,64}E (provides 16 rather than 32 GPRs)">,
- RISCVExtensionBitmask<0, 1>;
+ RISCVExtensionBitmask<0, 4>;
def FeatureStdExtZic64b
: RISCVExtension<"zic64b", 1, 0,
- "'Zic64b' (Cache Block Size Is 64 Bytes)">,
- RISCVExtensionBitmask<0, 2>;
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">;
def FeatureStdExtZicbom
: RISCVExtension<"zicbom", 1, 0,
- "'Zicbom' (Cache-Block Management Instructions)">,
- RISCVExtensionBitmask<0, 3>;
+ "'Zicbom' (Cache-Block Management Instructions)">;
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
AssemblerPredicate<(all_of FeatureStdExtZicbom),
"'Zicbom' (Cache-Block Management Instructions)">;
def FeatureStdExtZicbop
: RISCVExtension<"zicbop", 1, 0,
- "'Zicbop' (Cache-Block Prefetch Instructions)">,
- RISCVExtensionBitmask<0, 4>;
+ "'Zicbop' (Cache-Block Prefetch Instructions)">;
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
@@ -93,35 +90,31 @@ def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
def FeatureStdExtZicboz
: RISCVExtension<"zicboz", 1, 0,
"'Zicboz' (Cache-Block Zero Instructions)">,
- RISCVExtensionBitmask<0, 5>;
+ RISCVExtensionBitmask<1, 0>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
def FeatureStdExtZiccamoa
: RISCVExtension<"ziccamoa", 1, 0,
- "'Ziccamoa' (Main Memory Supports All Atomics in A)">,
- RISCVExtensionBitmask<0, 6>;
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
def FeatureStdExtZiccif
: RISCVExtension<"ziccif", 1, 0,
- "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">,
- RISCVExtensionBitmask<0, 7>;
+ "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
def FeatureStdExtZicclsm
: RISCVExtension<"zicclsm", 1, 0,
- "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">,
- RISCVExtensionBitmask<0, 8>;
+ "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
def FeatureStdExtZiccrse
: RISCVExtension<"ziccrse", 1, 0,
- "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">,
- RISCVExtensionBitmask<0, 9>;
+ "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
def FeatureStdExtZicsr
: RISCVExtension<"zicsr", 2, 0,
"'zicsr' (CSRs)">,
- RISCVExtensionBitmask<0, 10>;
+ RISCVExtensionBitmask<1, 1>;
def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
@@ -129,29 +122,26 @@ def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
def FeatureStdExtZicntr
: RISCVExtension<"zicntr", 2, 0,
"'Zicntr' (Base Counters and Timers)",
- [FeatureStdExtZicsr]>,
- RISCVExtensionBitmask<0, 11>;
+ [FeatureStdExtZicsr]>;
def FeatureStdExtZicond
: RISCVExtension<"zicond", 1, 0,
"'Zicond' (Integer Conditional Operations)">,
- RISCVExtensionBitmask<0, 12>;
+ RISCVExtensionBitmask<1, 2>;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
def FeatureStdExtZifencei
: RISCVExtension<"zifencei", 2, 0,
- "'Zifencei' (fence.i)">,
- RISCVExtensionBitmask<0, 13>;
+ "'Zifencei' (fence.i)">;
def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
def FeatureStdExtZihintpause
: RISCVExtension<"zihintpause", 2, 0,
- "'Zihintpause' (Pause Hint)">,
- RISCVExtensionBitmask<0, 14>;
+ "'Zihintpause' (Pause Hint)">;
def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
AssemblerPredicate<(all_of FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
@@ -159,7 +149,7 @@ def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
def FeatureStdExtZihintntl
: RISCVExtension<"zihintntl", 1, 0,
"'Zihintntl' (Non-Temporal Locality Hints)">,
- RISCVExtensionBitmask<0, 15>;
+ RISCVExtensionBitmask<1, 3>;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -167,12 +157,10 @@ def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
def FeatureStdExtZihpm
: RISCVExtension<"zihpm", 2, 0,
"'Zihpm' (Hardware Performance Counters)",
- [FeatureStdExtZicsr]>,
- RISCVExtensionBitmask<0, 16>;
+ [FeatureStdExtZicsr]>;
def FeatureStdExtZimop : RISCVExtension<"zimop", 1, 0,
- "'Zimop' (May-Be-Operations)">,
- RISCVExtensionBitmask<0, 17>;
+ "'Zimop' (May-Be-Operations)">;
def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
@@ -180,8 +168,7 @@ def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
def FeatureStdExtZicfilp
: RISCVExperimentalExtension<"zicfilp", 0, 4,
"'Zicfilp' (Landing pad)",
- [FeatureStdExtZicsr]>,
- RISCVExtensionBitmask<0, 18>;
+ [FeatureStdExtZicsr]>;
def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
AssemblerPredicate<(all_of FeatureStdExtZicfilp),
"'Zicfilp' (Landing pad)">;
@@ -191,8 +178,7 @@ def NoStdExtZicfilp : Predicate<"!Subtarget->hasStdExtZicfilp()">,
def FeatureStdExtZicfiss
: RISCVExperimentalExtension<"zicfiss", 0, 4,
"'Zicfiss' (Shadow stack)",
- [FeatureStdExtZicsr, FeatureStdExtZimop]>,
- RISCVExtensionBitmask<0, 19>;
+ [FeatureStdExtZicsr, FeatureStdExtZimop]>;
def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
AssemblerPredicate<(all_of FeatureStdExtZicfiss),
"'Zicfiss' (Shadow stack)">;
@@ -203,15 +189,14 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
def FeatureStdExtM
: RISCVExtension<"m", 2, 0,
"'M' (Integer Multiplication and Division)">,
- RISCVExtensionBitmask<0, 20>;
+ RISCVExtensionBitmask<0, 12>;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;
def FeatureStdExtZmmul
: RISCVExtension<"zmmul", 1, 0,
- "'Zmmul' (Integer Multiplication)">,
- RISCVExtensionBitmask<0, 21>;
+ "'Zmmul' (Integer Multiplication)">;
def HasStdExtMOrZmmul
: Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
@@ -224,7 +209,7 @@ def HasStdExtMOrZmmul
def FeatureStdExtA
: RISCVExtension<"a", 2, 1,
"'A' (Atomic Instructions)">,
- RISCVExtensionBitmask<0, 22>;
+ RISCVExtensionBitmask<0, 0>;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<(all_of FeatureStdExtA),
"'A' (Atomic Instructions)">;
@@ -232,24 +217,21 @@ def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
def FeatureStdExtZtso
: RISCVExperimentalExtension<"ztso", 0, 1,
"'Ztso' (Memory Model - Total Store Order)">,
- RISCVExtensionBitmask<0, 23>;
+ RISCVExtensionBitmask<1, 5>;
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
def FeatureStdExtZa64rs : RISCVExtension<"za64rs", 1, 0,
- "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">,
- RISCVExtensionBitmask<0, 24>;
+ "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
- "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">,
- RISCVExtensionBitmask<0, 25>;
+ "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
def FeatureStdExtZaamo
: RISCVExtension<"zaamo", 1, 0,
- "'Zaamo' (Atomic Memory Operations)">,
- RISCVExtensionBitmask<0, 26>;
+ "'Zaamo' (Atomic Memory Operations)">;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -258,8 +240,7 @@ def HasStdExtAOrZaamo
def FeatureStdExtZabha
: RISCVExtension<"zabha", 1, 0,
- "'Zabha' (Byte and Halfword Atomic Memory Operations)">,
- RISCVExtensionBitmask<0, 27>;
+ "'Zabha' (Byte and Halfword Atomic Memory Operations)">;
def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
AssemblerPredicate<(all_of FeatureStdExtZabha),
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
@@ -267,7 +248,7 @@ def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
def FeatureStdExtZacas
: RISCVExtension<"zacas", 1, 0,
"'Zacas' (Atomic Compare-And-Swap Instructions)">,
- RISCVExtensionBitmask<0, 28>;
+ RISCVExtensionBitmask<1, 6>;
def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
AssemblerPredicate<(all_of FeatureStdExtZacas),
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
@@ -275,16 +256,14 @@ def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
def FeatureStdExtZalasr
: RISCVExperimentalExtension<"zalasr", 0, 1,
- "'Zalasr' (Load-Acquire and Store-Release Instructions)">,
- RISCVExtensionBitmask<0, 29>;
+ "'Zalasr' (Load-Acquire and Store-Release Instructions)">;
def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
AssemblerPredicate<(all_of FeatureStdExtZalasr),
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
def FeatureStdExtZalrsc
: RISCVExtension<"zalrsc", 1, 0,
- "'Zalrsc' (Load-Reserved/Store-Conditional)">,
- RISCVExtensionBitmask<0, 30>;
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
@@ -293,12 +272,10 @@ def HasStdExtAOrZalrsc
def FeatureStdExtZama16b
: RISCVExtension<"zama16b", 1, 0,
- "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">,
- RISCVExtensionBitmask<0, 31>;
+ "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">;
def FeatureStdExtZawrs : RISCVExtension<"zawrs", 1, 0,
- "'Zawrs' (Wait on Reservation Set)">,
- RISCVExtensionBitmask<0, 32>;
+ "'Zawrs' (Wait on Reservation Set)">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
AssemblerPredicate<(all_of FeatureStdExtZawrs),
"'Zawrs' (Wait on Reservation Set)">;
@@ -309,7 +286,7 @@ def FeatureStdExtF
: RISCVExtension<"f", 2, 2,
"'F' (Single-Precision Floating-Point)",
[FeatureStdExtZicsr]>,
- RISCVExtensionBitmask<0, 33>;
+ RISCVExtensionBitmask<0, 5>;
def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
AssemblerPredicate<(all_of FeatureStdExtF),
"'F' (Single-Precision Floating-Point)">;
@@ -318,7 +295,7 @@ def FeatureStdExtD
: RISCVExtension<"d", 2, 2,
"'D' (Double-Precision Floating-Point)",
[FeatureStdExtF]>,
- RISCVExtensionBitmask<0, 34>;
+ RISCVExtensionBitmask<0, 3>;
def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
AssemblerPredicate<(all_of FeatureStdExtD),
"'D' (Double-Precision Floating-Point)">;
@@ -327,7 +304,7 @@ def FeatureStdExtZfhmin
: RISCVExtension<"zfhmin", 1, 0,
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
[FeatureStdExtF]>,
- RISCVExtensionBitmask<0, 35>;
+ RISCVExtensionBitmask<1, 7>;
def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfhmin),
"'Zfh' (Half-Precision Floating-Point) or "
@@ -337,7 +314,7 @@ def FeatureStdExtZfh
: RISCVExtension<"zfh", 1, 0,
"'Zfh' (Half-Precision Floating-Point)",
[FeatureStdExtZfhmin]>,
- RISCVExtensionBitmask<0, 36>;
+ RISCVExtensionBitmask<1, 8>;
def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
AssemblerPredicate<(all_of FeatureStdExtZfh),
"'Zfh' (Half-Precision Floating-Point)">;
@@ -346,8 +323,7 @@ def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
def FeatureStdExtZfbfmin
: RISCVExperimentalExtension<"zfbfmin", 1, 0,
"'Zfbfmin' (Scalar BF16 Converts)",
- [FeatureStdExtF]>,
- RISCVExtensionBitmask<0, 37>;
+ [FeatureStdExtF]>;
def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
"'Zfbfmin' (Scalar BF16 Converts)">;
@@ -364,7 +340,7 @@ def FeatureStdExtZfa
: RISCVExtension<"zfa", 1, 0,
"'Zfa' (Additional Floating-Point)",
[FeatureStdExtF]>,
- RISCVExtensionBitmask<0, 38>;
+ RISCVExtensionBitmask<1, 9>;
def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
AssemblerPredicate<(all_of FeatureStdExtZfa),
"'Zfa' (Additional Floating-Point)">;
@@ -372,8 +348,7 @@ def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
def FeatureStdExtZfinx
: RISCVExtension<"zfinx", 1, 0,
"'Zfinx' (Float in Integer)",
- [FeatureStdExtZicsr]>,
- RISCVExtensionBitmask<0, 39>;
+ [FeatureStdExtZicsr]>;
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
AssemblerPredicate<(all_of FeatureStdExtZfinx),
"'Zfinx' (Float in Integer)">;
@@ -381,8 +356,7 @@ def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
def FeatureStdExtZdinx
: RISCVExtension<"zdinx", 1, 0,
"'Zdinx' (Double in Integer)",
- [FeatureStdExtZfinx]>,
- RISCVExtensionBitmask<0, 40>;
+ [FeatureStdExtZfinx]>;
def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
AssemblerPredicate<(all_of FeatureStdExtZdinx),
"'Zdinx' (Double in Integer)">;
@@ -390,8 +364,7 @@ def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
def FeatureStdExtZhinxmin
: RISCVExtension<"zhinxmin", 1, 0,
"'Zhinxmin' (Half Float in Integer Minimal)",
- [FeatureStdExtZfinx]>,
- RISCVExtensionBitmask<0, 41>;
+ [FeatureStdExtZfinx]>;
def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
"'Zhinx' (Half Float in Integer) or "
@@ -401,7 +374,7 @@ def FeatureStdExtZhinx
: RISCVExtension<"zhinx", 1, 0,
"'Zhinx' (Half Float in Integer)",
[FeatureStdExtZhinxmin]>,
- RISCVExtensionBitmask<0, 42>;
+ RISCVExtensionBitmask<1, 10>;
def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
AssemblerPredicate<(all_of FeatureStdExtZhinx),
"'Zhinx' (Half Float in Integer)">;
@@ -412,7 +385,7 @@ def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
def FeatureStdExtC
: RISCVExtension<"c", 2, 0,
"'C' (Compressed Instructions)">,
- RISCVExtensionBitmask<0, 43>;
+ RISCVExtensionBitmask<0, 2>;
def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtC),
"'C' (Compressed Instructions)">;
@@ -428,7 +401,7 @@ def FeatureStdExtZca
: RISCVExtension<"zca", 1, 0,
"'Zca' (part of the C extension, excluding compressed "
"floating point loads/stores)">,
- RISCVExtensionBitmask<0, 44>;
+ RISCVExtensionBitmask<1, 11>;
def HasStdExtCOrZca
: Predicate<"Subtarget->hasStdExtCOrZca()">,
@@ -440,8 +413,7 @@ def HasStdExtCOrZca
def FeatureStdExtZcb
: RISCVExtension<"zcb", 1, 0,
"'Zcb' (Compressed basic bit manipulation instructions)",
- [FeatureStdExtZca]>,
- RISCVExtensionBitmask<0, 45>;
+ [FeatureStdExtZca]>;
def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
AssemblerPredicate<(all_of FeatureStdExtZcb),
"'Zcb' (Compressed basic bit manipulation instructions)">;
@@ -449,8 +421,7 @@ def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
def FeatureStdExtZcd
: RISCVExtension<"zcd", 1, 0,
"'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
- [FeatureStdExtD, FeatureStdExtZca]>,
- RISCVExtensionBitmask<0, 46>;
+ [FeatureStdExtD, FeatureStdExtZca]>;
def HasStdExtCOrZcd
: Predicate<"Subtarget->hasStdExtCOrZcd()">,
@@ -461,14 +432,12 @@ def HasStdExtCOrZcd
def FeatureStdExtZcf
: RISCVExtension<"zcf", 1, 0,
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
- [FeatureStdExtF, FeatureStdExtZca]>,
- RISCVExtensionBitmask<0, 47>;
+ [FeatureStdExtF, FeatureStdExtZca]>;
def FeatureStdExtZcmp
: RISCVExtension<"zcmp", 1, 0,
"'Zcmp' (sequenced instuctions for code-size reduction)",
- [FeatureStdExtZca]>,
- RISCVExtensionBitmask<0, 48>;
+ [FeatureStdExtZca]>;
def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtZcmp),
"'Zcmp' (sequenced instuctions for code-size reduction)">;
@@ -476,8 +445,7 @@ def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdE
def FeatureStdExtZcmt
: RISCVExtension<"zcmt", 1, 0,
"'Zcmt' (table jump instuctions for code-size reduction)",
- [FeatureStdExtZca, FeatureStdExtZicsr]>,
- RISCVExtensionBitmask<0, 49>;
+ [FeatureStdExtZca, FeatureStdExtZicsr]>;
def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
AssemblerPredicate<(all_of FeatureStdExtZcmt),
"'Zcmt' (table jump instuctions for code-size reduction)">;
@@ -485,8 +453,7 @@ def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
def FeatureStdExtZce
: RISCVExtension<"zce", 1, 0,
"'Zce' (Compressed extensions for microcontrollers)",
- [FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>,
- RISCVExtensionBitmask<0, 50>;
+ [FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>;
def HasStdExtCOrZcfOrZce
: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
@@ -499,8 +466,7 @@ def HasStdExtCOrZcfOrZce
def FeatureStdExtZcmop
: RISCVExtension<"zcmop", 1, 0,
"'Zcmop' (Compressed May-Be-Operations)",
- [FeatureStdExtZca]>,
- RISCVExtensionBitmask<0, 51>;
+ [FeatureStdExtZca]>;
def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
AssemblerPredicate<(all_of FeatureStdExtZcmop),
"'Zcmop' (Compressed May-Be-Operations)">;
@@ -510,7 +476,7 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
def FeatureStdExtZba
: RISCVExtension<"zba", 1, 0,
"'Zba' (Address Generation Instructions)">,
- RISCVExtensionBitmask<0, 52>;
+ RISCVExtensionBitmask<1, 55>;
def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
AssemblerPredicate<(all_of FeatureStdExtZba),
"'Zba' (Address Generation Instructions)">;
@@ -519,7 +485,7 @@ def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
def FeatureStdExtZbb
: RISCVExtension<"zbb", 1, 0,
"'Zbb' (Basic Bit-Manipulation)">,
- RISCVExtensionBitmask<0, 53>;
+ RISCVExtensionBitmask<1, 12>;
def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
AssemblerPredicate<(all_of FeatureStdExtZbb),
"'Zbb' (Basic Bit-Manipulation)">;
@@ -527,7 +493,7 @@ def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
def FeatureStdExtZbc
: RISCVExtension<"zbc", 1, 0,
"'Zbc' (Carry-Less Multiplication)">,
- RISCVExtensionBitmask<0, 54>;
+ RISCVExtensionBitmask<1, 13>;
def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
AssemblerPredicate<(all_of FeatureStdExtZbc),
"'Zbc' (Carry-Less Multiplication)">;
@@ -535,7 +501,7 @@ def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
def FeatureStdExtZbs
: RISCVExtension<"zbs", 1, 0,
"'Zbs' (Single-Bit Instructions)">,
- RISCVExtensionBitmask<0, 55>;
+ RISCVExtensionBitmask<1, 14>;
def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
AssemblerPredicate<(all_of FeatureStdExtZbs),
"'Zbs' (Single-Bit Instructions)">;
@@ -545,7 +511,7 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
def FeatureStdExtZbkb
: RISCVExtension<"zbkb", 1, 0,
"'Zbkb' (Bitmanip instructions for Cryptography)">,
- RISCVExtensionBitmask<0, 56>;
+ RISCVExtensionBitmask<1, 15>;
def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
AssemblerPredicate<(all_of FeatureStdExtZbkb),
"'Zbkb' (Bitmanip instructions for Cryptography)">;
@@ -553,7 +519,7 @@ def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
def FeatureStdExtZbkx
: RISCVExtension<"zbkx", 1, 0,
"'Zbkx' (Crossbar permutation instructions)">,
- RISCVExtensionBitmask<0, 57>;
+ RISCVExtensionBitmask<1, 16>;
def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
AssemblerPredicate<(all_of FeatureStdExtZbkx),
"'Zbkx' (Crossbar permutation instructions)">;
@@ -571,7 +537,7 @@ def FeatureStdExtZbkc
: RISCVExtension<"zbkc", 1, 0,
"'Zbkc' (Carry-less multiply instructions for "
"Cryptography)">,
- RISCVExtensionBitmask<0, 58>;
+ RISCVExtensionBitmask<1, 17>;
def HasStdExtZbkc
: Predicate<"Subtarget->hasStdExtZbkc()">,
AssemblerPredicate<(all_of FeatureStdExtZbkc),
@@ -589,7 +555,7 @@ def HasStdExtZbcOrZbkc
def FeatureStdExtZknd
: RISCVExtension<"zknd", 1, 0,
"'Zknd' (NIST Suite: AES Decryption)">,
- RISCVExtensionBitmask<0, 59>;
+ RISCVExtensionBitmask<1, 18>;
def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
AssemblerPredicate<(all_of FeatureStdExtZknd),
"'Zknd' (NIST Suite: AES Decryption)">;
@@ -597,7 +563,7 @@ def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
def FeatureStdExtZkne
: RISCVExtension<"zkne", 1, 0,
"'Zkne' (NIST Suite: AES Encryption)">,
- RISCVExtensionBitmask<0, 60>;
+ RISCVExtensionBitmask<1, 19>;
def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
AssemblerPredicate<(all_of FeatureStdExtZkne),
"'Zkne' (NIST Suite: AES Encryption)">;
@@ -613,7 +579,7 @@ def HasStdExtZkndOrZkne
def FeatureStdExtZknh
: RISCVExtension<"zknh", 1, 0,
"'Zknh' (NIST Suite: Hash Function Instructions)">,
- RISCVExtensionBitmask<0, 61>;
+ RISCVExtensionBitmask<1, 20>;
def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
AssemblerPredicate<(all_of FeatureStdExtZknh),
"'Zknh' (NIST Suite: Hash Function Instructions)">;
@@ -621,7 +587,7 @@ def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
def FeatureStdExtZksed
: RISCVExtension<"zksed", 1, 0,
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">,
- RISCVExtensionBitmask<0, 62>;
+ RISCVExtensionBitmask<1, 21>;
def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
AssemblerPredicate<(all_of FeatureStdExtZksed),
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
@@ -629,7 +595,7 @@ def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
def FeatureStdExtZksh
: RISCVExtension<"zksh", 1, 0,
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">,
- RISCVExtensionBitmask<0, 63>;
+ RISCVExtensionBitmask<1, 22>;
def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
AssemblerPredicate<(all_of FeatureStdExtZksh),
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
@@ -637,7 +603,7 @@ def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
def FeatureStdExtZkr
: RISCVExtension<"zkr", 1, 0,
"'Zkr' (Entropy Source Extension)">,
- RISCVExtensionBitmask<1, 0>;
+ RISCVExtensionBitmask<1, 23>;
def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
AssemblerPredicate<(all_of FeatureStdExtZkr),
"'Zkr' (Entropy Source Extension)">;
@@ -650,8 +616,7 @@ def FeatureStdExtZkn
FeatureStdExtZbkx,
FeatureStdExtZkne,
FeatureStdExtZknd,
- FeatureStdExtZknh]>,
- RISCVExtensionBitmask<1, 1>;
+ FeatureStdExtZknh]>;
def FeatureStdExtZks
: RISCVExtension<"zks", 1, 0,
@@ -660,28 +625,26 @@ def FeatureStdExtZks
FeatureStdExtZbkc,
FeatureStdExtZbkx,
FeatureStdExtZksed,
- FeatureStdExtZksh]>,
- RISCVExtensionBitmask<1, 2>;
+ FeatureStdExtZksh]>;
def FeatureStdExtZkt
: RISCVExtension<"zkt", 1, 0,
"'Zkt' (Data Independent Execution Latency)">,
- RISCVExtensionBitmask<1, 3>;
+ RISCVExtensionBitmask<1, 24>;
def FeatureStdExtZk
: RISCVExtension<"zk", 1, 0,
"'Zk' (Standard scalar cryptography extension)",
[FeatureStdExtZkn,
FeatureStdExtZkr,
- FeatureStdExtZkt]>,
- RISCVExtensionBitmask<1, 4>;
+ FeatureStdExtZkt]>;
// Vector Extensions
def FeatureStdExtZvl32b : RISCVExtension<"zvl32b", 1, 0,
"'Zvl' (Minimum Vector Length) 32", [],
"ZvlLen", "32">,
- RISCVExtensionBitmask<1, 5>;
+ RISCVExtensionBitmask<1, 25>;
foreach i = { 6-16 } in {
defvar I = !shl(1, i);
@@ -690,7 +653,7 @@ foreach i = { 6-16 } in {
"'Zvl' (Minimum Vector Length) "#I,
[!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")],
"ZvlLen", !cast<string>(I)>,
- RISCVExtensionBitmask<1, !add(6, !sub(i, 6))>;
+ RISCVExtensionBitmask<1, !add(26, !sub(i, 6))>;
}
def FeatureStdExtZve32x
@@ -698,7 +661,7 @@ def FeatureStdExtZve32x
"'Zve32x' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW)",
[FeatureStdExtZicsr, FeatureStdExtZvl32b]>,
- RISCVExtensionBitmask<1, 17>;
+ RISCVExtensionBitmask<1, 37>;
def FeatureStdExtZve32f
@@ -706,40 +669,39 @@ def FeatureStdExtZve32f
"'Zve32f' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW and F extension)",
[FeatureStdExtZve32x, FeatureStdExtF]>,
- RISCVExtensionBitmask<1, 18>;
+ RISCVExtensionBitmask<1, 38>;
def FeatureStdExtZve64x
: RISCVExtension<"zve64x", 1, 0,
"'Zve64x' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW)",
[FeatureStdExtZve32x, FeatureStdExtZvl64b]>,
- RISCVExtensionBitmask<1, 19>;
+ RISCVExtensionBitmask<1, 39>;
def FeatureStdExtZve64f
: RISCVExtension<"zve64f", 1, 0,
"'Zve64f' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW and F extension)",
[FeatureStdExtZve32f, FeatureStdExtZve64x]>,
- RISCVExtensionBitmask<1, 20>;
+ RISCVExtensionBitmask<1, 40>;
def FeatureStdExtZve64d
: RISCVExtension<"zve64d", 1, 0,
"'Zve64d' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW, F and D extension)",
[FeatureStdExtZve64f, FeatureStdExtD]>,
- RISCVExtensionBitmask<1, 21>;
+ RISCVExtensionBitmask<1, 41>;
def FeatureStdExtV
: RISCVExtension<"v", 1, 0,
"'V' (Vector Extension for Application Processors)",
[FeatureStdExtZvl128b, FeatureStdExtZve64d]>,
- RISCVExtensionBitmask<1, 22>;
+ RISCVExtensionBitmask<0, 21>;
def FeatureStdExtZvfbfmin
: RISCVExperimentalExtension<"zvfbfmin", 1, 0,
"'Zvbfmin' (Vector BF16 Converts)",
- [FeatureStdExtZve32f]>,
- RISCVExtensionBitmask<1, 23>;
+ [FeatureStdExtZve32f]>;
def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
"'Zvfbfmin' (Vector BF16 Converts)">;
@@ -747,8 +709,7 @@ def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
def FeatureStdExtZvfbfwma
: RISCVExperimentalExtension<"zvfbfwma", 1, 0,
"'Zvfbfwma' (Vector BF16 widening mul-add)",
- [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>,
- RISCVExtensionBitmask<1, 24>;
+ [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>;
def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
"'Zvfbfwma' (Vector BF16 widening mul-add)">;
@@ -757,13 +718,13 @@ def FeatureStdExtZvfhmin
: RISCVExtension<"zvfhmin", 1, 0,
"'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
[FeatureStdExtZve32f]>,
- RISCVExtensionBitmask<1, 25>;
+ RISCVExtensionBitmask<1, 43>;
def FeatureStdExtZvfh
: RISCVExtension<"zvfh", 1, 0,
"'Zvfh' (Vector Half-Precision Floating-Point)",
[FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>,
- RISCVExtensionBitmask<1, 26>;
+ RISCVExtensionBitmask<1, 44>;
def HasStdExtZfhOrZvfh
: Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
@@ -776,7 +737,7 @@ def HasStdExtZfhOrZvfh
def FeatureStdExtZvkb
: RISCVExtension<"zvkb", 1, 0,
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">,
- RISCVExtensionBitmask<1, 27>;
+ RISCVExtensionBitmask<1, 45>;
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
AssemblerPredicate<(all_of FeatureStdExtZvkb),
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
@@ -785,7 +746,7 @@ def FeatureStdExtZvbb
: RISCVExtension<"zvbb", 1, 0,
"'Zvbb' (Vector basic bit-manipulation instructions)",
[FeatureStdExtZvkb]>,
- RISCVExtensionBitmask<1, 28>;
+ RISCVExtensionBitmask<1, 46>;
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
AssemblerPredicate<(all_of FeatureStdExtZvbb),
"'Zvbb' (Vector basic bit-manipulation instructions)">;
@@ -793,7 +754,7 @@ def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
def FeatureStdExtZvbc
: RISCVExtension<"zvbc", 1, 0,
"'Zvbc' (Vector Carryless Multiplication)">,
- RISCVExtensionBitmask<1, 29>;
+ RISCVExtensionBitmask<1, 47>;
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
AssemblerPredicate<(all_of FeatureStdExtZvbc),
"'Zvbc' (Vector Carryless Multiplication)">;
@@ -801,7 +762,7 @@ def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
def FeatureStdExtZvkg
: RISCVExtension<"zvkg", 1, 0,
"'Zvkg' (Vector GCM instructions for Cryptography)">,
- RISCVExtensionBitmask<1, 30>;
+ RISCVExtensionBitmask<1, 48>;
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
AssemblerPredicate<(all_of FeatureStdExtZvkg),
"'Zvkg' (Vector GCM instructions for Cryptography)">;
@@ -809,7 +770,7 @@ def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
def FeatureStdExtZvkned
: RISCVExtension<"zvkned", 1, 0,
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">,
- RISCVExtensionBitmask<1, 31>;
+ RISCVExtensionBitmask<1, 49>;
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
AssemblerPredicate<(all_of FeatureStdExtZvkned),
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
@@ -817,7 +778,7 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
def FeatureStdExtZvknha
: RISCVExtension<"zvknha", 1, 0,
"'Zvknha' (Vector SHA-2 (SHA-256 only))">,
- RISCVExtensionBitmask<1, 32>;
+ RISCVExtensionBitmask<1, 50>;
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
AssemblerPredicate<(all_of FeatureStdExtZvknha),
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
@@ -826,7 +787,7 @@ def FeatureStdExtZvknhb
: RISCVExtension<"zvknhb", 1, 0,
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
[FeatureStdExtZve64x]>,
- RISCVExtensionBitmask<1, 33>;
+ RISCVExtensionBitmask<1, 51>;
def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
AssemblerPredicate<(all_of FeatureStdExtZvknhb),
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;
@@ -838,7 +799,7 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg
def FeatureStdExtZvksed
: RISCVExtension<"zvksed", 1, 0,
"'Zvksed' (SM4 Block Cipher Instructions)">,
- RISCVExtensionBitmask<1, 34>;
+ RISCVExtensionBitmask<1, 52>;
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
AssemblerPredicate<(all_of FeatureStdExtZvksed),
"'Zvksed' (SM4 Block Cipher Instructions)">;
@@ -846,7 +807,7 @@ def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
def FeatureStdExtZvksh
: RISCVExtension<"zvksh", 1, 0,
"'Zvksh' (SM3 Hash Function Instructions)">,
- RISCVExtensionBitmask<1, 35>;
+ RISCVExtensionBitmask<1, 53>;
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
AssemblerPredicate<(all_of FeatureStdExtZvksh),
"'Zvksh' (SM3 Hash Function Instructions)">;
@@ -854,7 +815,7 @@ def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
def FeatureStdExtZvkt
: RISCVExtension<"zvkt", 1, 0,
"'Zvkt' (Vector Data-Independent Execution Latency)">,
- RISCVExtensionBitmask<1, 36>;
+ RISCVExtensionBitmask<1, 54>;
// Zvk short-hand extensions
@@ -864,19 +825,18 @@ def FeatureStdExtZvkn
"'Zvkt')",
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
FeatureStdExtZvkb, FeatureStdExtZvkt]>,
- RISCVExtensionBitmask<1, 37>;
+ RISCVExtensionBitmask<1, 56>;
def FeatureStdExtZvknc
: RISCVExtension<"zvknc", 1, 0,
"'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')",
- [FeatureStdExtZvkn, FeatureStdExtZvbc]>,
- RISCVExtensionBitmask<1, 38>;
+ [FeatureStdExtZvkn, FeatureStdExtZvbc]>;
def FeatureStdExtZvkng
: RISCVExtension<"zvkng", 1, 0,
"'zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
[FeatureStdExtZvkn, FeatureStdExtZvkg]>,
- RISCVExtensionBitmask<1, 39>;
+ RISCVExtensionBitmask<1, 57>;
def FeatureStdExtZvks
: RISCVExtension<"zvks", 1, 0,
@@ -884,19 +844,18 @@ def FeatureStdExtZvks
"'Zvkt')",
[FeatureStdExtZvksed, FeatureStdExtZvksh,
FeatureStdExtZvkb, FeatureStdExtZvkt]>,
- RISCVExtensionBitmask<1, 40>;
+ RISCVExtensionBitmask<1, 58>;
def FeatureStdExtZvksc
: RISCVExtension<"zvksc", 1, 0,
"'Zvksc' (shorthand for 'Zvks' and 'Zvbc')",
- [FeatureStdExtZvks, FeatureStdExtZvbc]>,
- RISCVExtensionBitmask<1, 41>;
+ [FeatureStdExtZvks, FeatureStdExtZvbc]>;
def FeatureStdExtZvksg
: RISCVExtension<"zvksg", 1, 0,
"'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
[FeatureStdExtZvks, FeatureStdExtZvkg]>,
- RISCVExtensionBitmask<1, 42>;
+ RISCVExtensionBitmask<1, 59>;
// Vector instruction predicates
>From 1984a454c4c89532f3d41a53fd3bce083bc13c06 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Sun, 23 Jun 2024 21:59:53 -0700
Subject: [PATCH 20/27] DenseMap into DenseSet
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index fa1540d7db7a3..88b86e7b8d7e8 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -11,7 +11,7 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/DenseSet.h"
#include "llvm/Support/RISCVISAUtils.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
>From 1e901b01d73848829bb42df94da4e428f2f779fd Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Sun, 23 Jun 2024 22:04:03 -0700
Subject: [PATCH 21/27] Drop null check
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 88b86e7b8d7e8..4850e1d9d5730 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -218,8 +218,7 @@ static inline uint64_t getValueFromBitsInit(const BitsInit *B,
uint64_t Value = 0;
for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
const auto *Bit = cast<BitInit>(B->getBit(i));
- if (Bit)
- Value |= uint64_t(Bit->getValue()) << i;
+ Value |= uint64_t(Bit->getValue()) << i;
}
return Value;
}
>From d7d2e589179751b0200be923bce7cd55d50eb6c1 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Sun, 23 Jun 2024 22:09:29 -0700
Subject: [PATCH 22/27] Drop ArrayRef
---
llvm/lib/TargetParser/RISCVTargetParser.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index ec6447a44f90d..adb594777be80 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -143,7 +143,7 @@ struct LessExtName {
static RISCVExtensionBitmaskTable::RISCVExtensionBitmask
getExtensionBitmask(StringRef ExtName) {
ArrayRef<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmasks =
- ArrayRef(RISCVExtensionBitmaskTable::ExtensionBitmask);
+ RISCVExtensionBitmaskTable::ExtensionBitmask;
auto *I = llvm::lower_bound(ExtBitmasks, ExtName, LessExtName());
if (I != ExtBitmasks.end())
>From 8c82be8180abc033ef235eddd638b1c49bc02e9b Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Mon, 24 Jun 2024 00:44:00 -0700
Subject: [PATCH 23/27] Use BitPos instead of bitmask inside
RISCVExtensionBitmask
---
llvm/include/llvm/TargetParser/RISCVTargetParser.h | 2 +-
llvm/test/TableGen/riscv-target-def.td | 8 ++++----
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 11 ++++++++++-
3 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 8444935bd666d..e998bc4ca59ee 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -28,7 +28,7 @@ namespace RISCVExtensionBitmaskTable {
struct RISCVExtensionBitmask {
const char *Name;
unsigned GroupID;
- uint64_t Bitmask;
+ unsigned BitPosition;
};
} // namespace RISCVExtensionBitmaskTable
diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
index 2303c1f4bf37f..e0d4d7fae20c1 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -183,9 +183,9 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
// CHECK: #ifdef GET_RISCVExtensionBitmaskTable_IMPL
// CHECK-NEXT: static const RISCVExtensionBitmask ExtensionBitmask[]={
-// CHECK-NEXT: {"f", 0, 8589934592ULL},
-// CHECK-NEXT: {"i", 0, 1ULL},
-// CHECK-NEXT: {"zicsr", 0, 1024ULL},
-// CHECK-NEXT: {"zifencei", 0, 8192ULL},
+// CHECK-NEXT: {"f", 0, 33ULL},
+// CHECK-NEXT: {"i", 0, 0ULL},
+// CHECK-NEXT: {"zicsr", 0, 10ULL},
+// CHECK-NEXT: {"zifencei", 0, 13ULL},
// CHECK-NEXT: };
// CHECK-NEXT: #endif
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 4850e1d9d5730..f86ab0c207551 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -223,6 +223,15 @@ static inline uint64_t getValueFromBitsInit(const BitsInit *B,
return Value;
}
+static unsigned getBitPosFromValue(uint64_t Val) {
+ int Pos = 0;
+ while (Val > 1) {
+ Pos += 1;
+ Val >>= 1;
+ }
+ return Pos;
+}
+
static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
std::vector<Record *> Extensions =
@@ -253,7 +262,7 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
OS << " {"
<< "\"" << ExtName << "\""
- << ", " << GroupIDVal << ", " << BitmaskVal << "ULL"
+ << ", " << GroupIDVal << ", " << getBitPosFromValue(BitmaskVal) << "ULL"
<< "},\n";
}
OS << "};\n";
>From ee5b744bc3b10a3819f13e54bb62209e03b22120 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 25 Jun 2024 23:19:23 -0700
Subject: [PATCH 24/27] Rearrange bitmask for extension
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 107 +++++++++++--------------
1 file changed, 49 insertions(+), 58 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 4072f1aff9746..da7cdb3864a0b 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -66,8 +66,7 @@ def FeatureStdExtI
def FeatureStdExtE
: RISCVExtension<"e", 2, 0,
- "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">,
- RISCVExtensionBitmask<0, 4>;
+ "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
def FeatureStdExtZic64b
: RISCVExtension<"zic64b", 1, 0,
@@ -90,7 +89,7 @@ def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
def FeatureStdExtZicboz
: RISCVExtension<"zicboz", 1, 0,
"'Zicboz' (Cache-Block Zero Instructions)">,
- RISCVExtensionBitmask<1, 0>;
+ RISCVExtensionBitmask<0, 26>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
@@ -114,7 +113,7 @@ def FeatureStdExtZiccrse
def FeatureStdExtZicsr
: RISCVExtension<"zicsr", 2, 0,
"'zicsr' (CSRs)">,
- RISCVExtensionBitmask<1, 1>;
+ RISCVExtensionBitmask<0, 27>;
def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
@@ -127,7 +126,7 @@ def FeatureStdExtZicntr
def FeatureStdExtZicond
: RISCVExtension<"zicond", 1, 0,
"'Zicond' (Integer Conditional Operations)">,
- RISCVExtensionBitmask<1, 2>;
+ RISCVExtensionBitmask<0, 28>;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
@@ -149,7 +148,7 @@ def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
def FeatureStdExtZihintntl
: RISCVExtension<"zihintntl", 1, 0,
"'Zihintntl' (Non-Temporal Locality Hints)">,
- RISCVExtensionBitmask<1, 3>;
+ RISCVExtensionBitmask<0, 29>;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -217,7 +216,7 @@ def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
def FeatureStdExtZtso
: RISCVExperimentalExtension<"ztso", 0, 1,
"'Ztso' (Memory Model - Total Store Order)">,
- RISCVExtensionBitmask<1, 5>;
+ RISCVExtensionBitmask<0, 30>;
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
@@ -248,7 +247,7 @@ def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
def FeatureStdExtZacas
: RISCVExtension<"zacas", 1, 0,
"'Zacas' (Atomic Compare-And-Swap Instructions)">,
- RISCVExtensionBitmask<1, 6>;
+ RISCVExtensionBitmask<0, 31>;
def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
AssemblerPredicate<(all_of FeatureStdExtZacas),
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
@@ -304,7 +303,7 @@ def FeatureStdExtZfhmin
: RISCVExtension<"zfhmin", 1, 0,
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
[FeatureStdExtF]>,
- RISCVExtensionBitmask<1, 7>;
+ RISCVExtensionBitmask<0, 32>;
def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfhmin),
"'Zfh' (Half-Precision Floating-Point) or "
@@ -314,7 +313,7 @@ def FeatureStdExtZfh
: RISCVExtension<"zfh", 1, 0,
"'Zfh' (Half-Precision Floating-Point)",
[FeatureStdExtZfhmin]>,
- RISCVExtensionBitmask<1, 8>;
+ RISCVExtensionBitmask<0, 33>;
def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
AssemblerPredicate<(all_of FeatureStdExtZfh),
"'Zfh' (Half-Precision Floating-Point)">;
@@ -340,7 +339,7 @@ def FeatureStdExtZfa
: RISCVExtension<"zfa", 1, 0,
"'Zfa' (Additional Floating-Point)",
[FeatureStdExtF]>,
- RISCVExtensionBitmask<1, 9>;
+ RISCVExtensionBitmask<0, 34>;
def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
AssemblerPredicate<(all_of FeatureStdExtZfa),
"'Zfa' (Additional Floating-Point)">;
@@ -373,8 +372,7 @@ def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
def FeatureStdExtZhinx
: RISCVExtension<"zhinx", 1, 0,
"'Zhinx' (Half Float in Integer)",
- [FeatureStdExtZhinxmin]>,
- RISCVExtensionBitmask<1, 10>;
+ [FeatureStdExtZhinxmin]>;
def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
AssemblerPredicate<(all_of FeatureStdExtZhinx),
"'Zhinx' (Half Float in Integer)">;
@@ -400,8 +398,7 @@ def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
def FeatureStdExtZca
: RISCVExtension<"zca", 1, 0,
"'Zca' (part of the C extension, excluding compressed "
- "floating point loads/stores)">,
- RISCVExtensionBitmask<1, 11>;
+ "floating point loads/stores)">;
def HasStdExtCOrZca
: Predicate<"Subtarget->hasStdExtCOrZca()">,
@@ -476,7 +473,7 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
def FeatureStdExtZba
: RISCVExtension<"zba", 1, 0,
"'Zba' (Address Generation Instructions)">,
- RISCVExtensionBitmask<1, 55>;
+ RISCVExtensionBitmask<0, 35>;
def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
AssemblerPredicate<(all_of FeatureStdExtZba),
"'Zba' (Address Generation Instructions)">;
@@ -485,7 +482,7 @@ def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
def FeatureStdExtZbb
: RISCVExtension<"zbb", 1, 0,
"'Zbb' (Basic Bit-Manipulation)">,
- RISCVExtensionBitmask<1, 12>;
+ RISCVExtensionBitmask<0, 36>;
def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
AssemblerPredicate<(all_of FeatureStdExtZbb),
"'Zbb' (Basic Bit-Manipulation)">;
@@ -493,7 +490,7 @@ def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
def FeatureStdExtZbc
: RISCVExtension<"zbc", 1, 0,
"'Zbc' (Carry-Less Multiplication)">,
- RISCVExtensionBitmask<1, 13>;
+ RISCVExtensionBitmask<0, 37>;
def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
AssemblerPredicate<(all_of FeatureStdExtZbc),
"'Zbc' (Carry-Less Multiplication)">;
@@ -501,7 +498,7 @@ def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
def FeatureStdExtZbs
: RISCVExtension<"zbs", 1, 0,
"'Zbs' (Single-Bit Instructions)">,
- RISCVExtensionBitmask<1, 14>;
+ RISCVExtensionBitmask<0, 38>;
def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
AssemblerPredicate<(all_of FeatureStdExtZbs),
"'Zbs' (Single-Bit Instructions)">;
@@ -511,7 +508,7 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
def FeatureStdExtZbkb
: RISCVExtension<"zbkb", 1, 0,
"'Zbkb' (Bitmanip instructions for Cryptography)">,
- RISCVExtensionBitmask<1, 15>;
+ RISCVExtensionBitmask<0, 39>;
def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
AssemblerPredicate<(all_of FeatureStdExtZbkb),
"'Zbkb' (Bitmanip instructions for Cryptography)">;
@@ -519,7 +516,7 @@ def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
def FeatureStdExtZbkx
: RISCVExtension<"zbkx", 1, 0,
"'Zbkx' (Crossbar permutation instructions)">,
- RISCVExtensionBitmask<1, 16>;
+ RISCVExtensionBitmask<0, 40>;
def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
AssemblerPredicate<(all_of FeatureStdExtZbkx),
"'Zbkx' (Crossbar permutation instructions)">;
@@ -537,7 +534,7 @@ def FeatureStdExtZbkc
: RISCVExtension<"zbkc", 1, 0,
"'Zbkc' (Carry-less multiply instructions for "
"Cryptography)">,
- RISCVExtensionBitmask<1, 17>;
+ RISCVExtensionBitmask<0, 41>;
def HasStdExtZbkc
: Predicate<"Subtarget->hasStdExtZbkc()">,
AssemblerPredicate<(all_of FeatureStdExtZbkc),
@@ -555,7 +552,7 @@ def HasStdExtZbcOrZbkc
def FeatureStdExtZknd
: RISCVExtension<"zknd", 1, 0,
"'Zknd' (NIST Suite: AES Decryption)">,
- RISCVExtensionBitmask<1, 18>;
+ RISCVExtensionBitmask<0, 42>;
def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
AssemblerPredicate<(all_of FeatureStdExtZknd),
"'Zknd' (NIST Suite: AES Decryption)">;
@@ -563,7 +560,7 @@ def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
def FeatureStdExtZkne
: RISCVExtension<"zkne", 1, 0,
"'Zkne' (NIST Suite: AES Encryption)">,
- RISCVExtensionBitmask<1, 19>;
+ RISCVExtensionBitmask<0, 43>;
def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
AssemblerPredicate<(all_of FeatureStdExtZkne),
"'Zkne' (NIST Suite: AES Encryption)">;
@@ -579,7 +576,7 @@ def HasStdExtZkndOrZkne
def FeatureStdExtZknh
: RISCVExtension<"zknh", 1, 0,
"'Zknh' (NIST Suite: Hash Function Instructions)">,
- RISCVExtensionBitmask<1, 20>;
+ RISCVExtensionBitmask<0, 44>;
def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
AssemblerPredicate<(all_of FeatureStdExtZknh),
"'Zknh' (NIST Suite: Hash Function Instructions)">;
@@ -587,7 +584,7 @@ def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
def FeatureStdExtZksed
: RISCVExtension<"zksed", 1, 0,
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">,
- RISCVExtensionBitmask<1, 21>;
+ RISCVExtensionBitmask<0, 45>;
def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
AssemblerPredicate<(all_of FeatureStdExtZksed),
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
@@ -595,15 +592,14 @@ def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
def FeatureStdExtZksh
: RISCVExtension<"zksh", 1, 0,
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">,
- RISCVExtensionBitmask<1, 22>;
+ RISCVExtensionBitmask<0, 46>;
def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
AssemblerPredicate<(all_of FeatureStdExtZksh),
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
def FeatureStdExtZkr
: RISCVExtension<"zkr", 1, 0,
- "'Zkr' (Entropy Source Extension)">,
- RISCVExtensionBitmask<1, 23>;
+ "'Zkr' (Entropy Source Extension)">;
def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
AssemblerPredicate<(all_of FeatureStdExtZkr),
"'Zkr' (Entropy Source Extension)">;
@@ -630,7 +626,7 @@ def FeatureStdExtZks
def FeatureStdExtZkt
: RISCVExtension<"zkt", 1, 0,
"'Zkt' (Data Independent Execution Latency)">,
- RISCVExtensionBitmask<1, 24>;
+ RISCVExtensionBitmask<0, 47>;
def FeatureStdExtZk
: RISCVExtension<"zk", 1, 0,
@@ -644,7 +640,7 @@ def FeatureStdExtZk
def FeatureStdExtZvl32b : RISCVExtension<"zvl32b", 1, 0,
"'Zvl' (Minimum Vector Length) 32", [],
"ZvlLen", "32">,
- RISCVExtensionBitmask<1, 25>;
+ RISCVExtensionBitmask<0, 48>;
foreach i = { 6-16 } in {
defvar I = !shl(1, i);
@@ -653,7 +649,7 @@ foreach i = { 6-16 } in {
"'Zvl' (Minimum Vector Length) "#I,
[!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")],
"ZvlLen", !cast<string>(I)>,
- RISCVExtensionBitmask<1, !add(26, !sub(i, 6))>;
+ RISCVExtensionBitmask<0, !add(49, !sub(i, 6))>;
}
def FeatureStdExtZve32x
@@ -661,7 +657,7 @@ def FeatureStdExtZve32x
"'Zve32x' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW)",
[FeatureStdExtZicsr, FeatureStdExtZvl32b]>,
- RISCVExtensionBitmask<1, 37>;
+ RISCVExtensionBitmask<0, 60>;
def FeatureStdExtZve32f
@@ -669,28 +665,28 @@ def FeatureStdExtZve32f
"'Zve32f' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW and F extension)",
[FeatureStdExtZve32x, FeatureStdExtF]>,
- RISCVExtensionBitmask<1, 38>;
+ RISCVExtensionBitmask<0, 61>;
def FeatureStdExtZve64x
: RISCVExtension<"zve64x", 1, 0,
"'Zve64x' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW)",
[FeatureStdExtZve32x, FeatureStdExtZvl64b]>,
- RISCVExtensionBitmask<1, 39>;
+ RISCVExtensionBitmask<0, 62>;
def FeatureStdExtZve64f
: RISCVExtension<"zve64f", 1, 0,
"'Zve64f' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW and F extension)",
[FeatureStdExtZve32f, FeatureStdExtZve64x]>,
- RISCVExtensionBitmask<1, 40>;
+ RISCVExtensionBitmask<0, 63>;
def FeatureStdExtZve64d
: RISCVExtension<"zve64d", 1, 0,
"'Zve64d' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW, F and D extension)",
[FeatureStdExtZve64f, FeatureStdExtD]>,
- RISCVExtensionBitmask<1, 41>;
+ RISCVExtensionBitmask<1, 0>;
def FeatureStdExtV
: RISCVExtension<"v", 1, 0,
@@ -718,13 +714,13 @@ def FeatureStdExtZvfhmin
: RISCVExtension<"zvfhmin", 1, 0,
"'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
[FeatureStdExtZve32f]>,
- RISCVExtensionBitmask<1, 43>;
+ RISCVExtensionBitmask<1, 1>;
def FeatureStdExtZvfh
: RISCVExtension<"zvfh", 1, 0,
"'Zvfh' (Vector Half-Precision Floating-Point)",
[FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>,
- RISCVExtensionBitmask<1, 44>;
+ RISCVExtensionBitmask<1, 2>;
def HasStdExtZfhOrZvfh
: Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
@@ -737,7 +733,7 @@ def HasStdExtZfhOrZvfh
def FeatureStdExtZvkb
: RISCVExtension<"zvkb", 1, 0,
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">,
- RISCVExtensionBitmask<1, 45>;
+ RISCVExtensionBitmask<1, 3>;
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
AssemblerPredicate<(all_of FeatureStdExtZvkb),
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
@@ -746,7 +742,7 @@ def FeatureStdExtZvbb
: RISCVExtension<"zvbb", 1, 0,
"'Zvbb' (Vector basic bit-manipulation instructions)",
[FeatureStdExtZvkb]>,
- RISCVExtensionBitmask<1, 46>;
+ RISCVExtensionBitmask<1, 4>;
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
AssemblerPredicate<(all_of FeatureStdExtZvbb),
"'Zvbb' (Vector basic bit-manipulation instructions)">;
@@ -754,7 +750,7 @@ def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
def FeatureStdExtZvbc
: RISCVExtension<"zvbc", 1, 0,
"'Zvbc' (Vector Carryless Multiplication)">,
- RISCVExtensionBitmask<1, 47>;
+ RISCVExtensionBitmask<1, 5>;
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
AssemblerPredicate<(all_of FeatureStdExtZvbc),
"'Zvbc' (Vector Carryless Multiplication)">;
@@ -762,7 +758,7 @@ def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
def FeatureStdExtZvkg
: RISCVExtension<"zvkg", 1, 0,
"'Zvkg' (Vector GCM instructions for Cryptography)">,
- RISCVExtensionBitmask<1, 48>;
+ RISCVExtensionBitmask<1, 6>;
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
AssemblerPredicate<(all_of FeatureStdExtZvkg),
"'Zvkg' (Vector GCM instructions for Cryptography)">;
@@ -770,7 +766,7 @@ def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
def FeatureStdExtZvkned
: RISCVExtension<"zvkned", 1, 0,
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">,
- RISCVExtensionBitmask<1, 49>;
+ RISCVExtensionBitmask<1, 7>;
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
AssemblerPredicate<(all_of FeatureStdExtZvkned),
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
@@ -778,7 +774,7 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
def FeatureStdExtZvknha
: RISCVExtension<"zvknha", 1, 0,
"'Zvknha' (Vector SHA-2 (SHA-256 only))">,
- RISCVExtensionBitmask<1, 50>;
+ RISCVExtensionBitmask<1, 8>;
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
AssemblerPredicate<(all_of FeatureStdExtZvknha),
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
@@ -787,7 +783,7 @@ def FeatureStdExtZvknhb
: RISCVExtension<"zvknhb", 1, 0,
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
[FeatureStdExtZve64x]>,
- RISCVExtensionBitmask<1, 51>;
+ RISCVExtensionBitmask<1, 9>;
def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
AssemblerPredicate<(all_of FeatureStdExtZvknhb),
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;
@@ -799,7 +795,7 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg
def FeatureStdExtZvksed
: RISCVExtension<"zvksed", 1, 0,
"'Zvksed' (SM4 Block Cipher Instructions)">,
- RISCVExtensionBitmask<1, 52>;
+ RISCVExtensionBitmask<1, 10>;
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
AssemblerPredicate<(all_of FeatureStdExtZvksed),
"'Zvksed' (SM4 Block Cipher Instructions)">;
@@ -807,7 +803,7 @@ def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
def FeatureStdExtZvksh
: RISCVExtension<"zvksh", 1, 0,
"'Zvksh' (SM3 Hash Function Instructions)">,
- RISCVExtensionBitmask<1, 53>;
+ RISCVExtensionBitmask<1, 11>;
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
AssemblerPredicate<(all_of FeatureStdExtZvksh),
"'Zvksh' (SM3 Hash Function Instructions)">;
@@ -815,7 +811,7 @@ def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
def FeatureStdExtZvkt
: RISCVExtension<"zvkt", 1, 0,
"'Zvkt' (Vector Data-Independent Execution Latency)">,
- RISCVExtensionBitmask<1, 54>;
+ RISCVExtensionBitmask<1, 12>;
// Zvk short-hand extensions
@@ -824,8 +820,7 @@ def FeatureStdExtZvkn
"'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and "
"'Zvkt')",
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
- FeatureStdExtZvkb, FeatureStdExtZvkt]>,
- RISCVExtensionBitmask<1, 56>;
+ FeatureStdExtZvkb, FeatureStdExtZvkt]>;
def FeatureStdExtZvknc
: RISCVExtension<"zvknc", 1, 0,
@@ -835,16 +830,14 @@ def FeatureStdExtZvknc
def FeatureStdExtZvkng
: RISCVExtension<"zvkng", 1, 0,
"'zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
- [FeatureStdExtZvkn, FeatureStdExtZvkg]>,
- RISCVExtensionBitmask<1, 57>;
+ [FeatureStdExtZvkn, FeatureStdExtZvkg]>;
def FeatureStdExtZvks
: RISCVExtension<"zvks", 1, 0,
"'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and "
"'Zvkt')",
[FeatureStdExtZvksed, FeatureStdExtZvksh,
- FeatureStdExtZvkb, FeatureStdExtZvkt]>,
- RISCVExtensionBitmask<1, 58>;
+ FeatureStdExtZvkb, FeatureStdExtZvkt]>;
def FeatureStdExtZvksc
: RISCVExtension<"zvksc", 1, 0,
@@ -854,9 +847,7 @@ def FeatureStdExtZvksc
def FeatureStdExtZvksg
: RISCVExtension<"zvksg", 1, 0,
"'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
- [FeatureStdExtZvks, FeatureStdExtZvkg]>,
- RISCVExtensionBitmask<1, 59>;
-
+ [FeatureStdExtZvks, FeatureStdExtZvkg]>;
// Vector instruction predicates
def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">,
>From 1e8738aa88011ea45d31741eead43b45385c812d Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 25 Jun 2024 23:19:51 -0700
Subject: [PATCH 25/27] Use int store bit position and groupID
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 +--
llvm/test/TableGen/riscv-target-def.td | 4 +--
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 29 ++-----------------
3 files changed, 7 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index da7cdb3864a0b..155443761863a 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -42,8 +42,8 @@ class RISCVExtension<string name, int major, int minor, string desc,
// gourpID - groupID of extension
// bitmaskShift - bitmask shift of extension
class RISCVExtensionBitmask<bits<3> groupID, int bitmaskShift> {
- bits<3> GroupID = groupID;
- bits<64> Bitmask = !shl(1, bitmaskShift);
+ int GroupID = groupID;
+ int Bitmask = bitmaskShift;
}
// Version of RISCVExtension to be used for Experimental extensions. This
diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
index e0d4d7fae20c1..106ce57ecfdc4 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -13,8 +13,8 @@ class RISCVExtension<string name, int major, int minor, string desc,
}
class RISCVExtensionBitmask<bits<3> groupID, int bitmaskShift> {
- bits<3> GroupID = groupID;
- bits<64> Bitmask = !shl(1, bitmaskShift);
+ int GroupID = groupID;
+ int Bitmask = bitmaskShift;
}
class RISCVExperimentalExtension<string name, int major, int minor, string desc,
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index f86ab0c207551..ca85053aeddb2 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -211,27 +211,6 @@ static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) {
OS << "\n#undef TUNE_PROC\n";
}
-static inline uint64_t getValueFromBitsInit(const BitsInit *B,
- const Record &R) {
- assert(B->getNumBits() <= 64 && "BitInits' too long!");
-
- uint64_t Value = 0;
- for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
- const auto *Bit = cast<BitInit>(B->getBit(i));
- Value |= uint64_t(Bit->getValue()) << i;
- }
- return Value;
-}
-
-static unsigned getBitPosFromValue(uint64_t Val) {
- int Pos = 0;
- while (Val > 1) {
- Pos += 1;
- Val >>= 1;
- }
- return Pos;
-}
-
static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
std::vector<Record *> Extensions =
@@ -247,13 +226,11 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
OS << "#ifdef GET_RISCVExtensionBitmaskTable_IMPL\n";
OS << "static const RISCVExtensionBitmask ExtensionBitmask[]={\n";
for (const Record *Rec : Extensions) {
- BitsInit *GroupIDBits = Rec->getValueAsBitsInit("GroupID");
- BitsInit *BitmaskBits = Rec->getValueAsBitsInit("Bitmask");
+ unsigned GroupIDVal = Rec->getValueAsInt("GroupID");
+ unsigned BitmaskVal = Rec->getValueAsInt("Bitmask");
StringRef ExtName = Rec->getValueAsString("Name");
ExtName.consume_front("experimental-");
- uint64_t GroupIDVal = getValueFromBitsInit(GroupIDBits, *Rec);
- uint64_t BitmaskVal = getValueFromBitsInit(BitmaskBits, *Rec);
#ifndef NDEBUG
assert(Seen.insert(std::make_pair(GroupIDVal, BitmaskVal)).second &&
@@ -262,7 +239,7 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
OS << " {"
<< "\"" << ExtName << "\""
- << ", " << GroupIDVal << ", " << getBitPosFromValue(BitmaskVal) << "ULL"
+ << ", " << GroupIDVal << ", " << BitmaskVal << "ULL"
<< "},\n";
}
OS << "};\n";
>From 5f84ee1b9c8e80c44276d10ecc973223b5f09a25 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 25 Jun 2024 23:40:15 -0700
Subject: [PATCH 26/27] Rename bitmask into bitPos
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +-
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 155443761863a..8610f68d6234c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -43,7 +43,7 @@ class RISCVExtension<string name, int major, int minor, string desc,
// bitmaskShift - bitmask shift of extension
class RISCVExtensionBitmask<bits<3> groupID, int bitmaskShift> {
int GroupID = groupID;
- int Bitmask = bitmaskShift;
+ int BitPos = bitmaskShift;
}
// Version of RISCVExtension to be used for Experimental extensions. This
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index ca85053aeddb2..edb1a4d5d8531 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -227,19 +227,19 @@ static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) {
OS << "static const RISCVExtensionBitmask ExtensionBitmask[]={\n";
for (const Record *Rec : Extensions) {
unsigned GroupIDVal = Rec->getValueAsInt("GroupID");
- unsigned BitmaskVal = Rec->getValueAsInt("Bitmask");
+ unsigned BitPosVal = Rec->getValueAsInt("BitPos");
StringRef ExtName = Rec->getValueAsString("Name");
ExtName.consume_front("experimental-");
#ifndef NDEBUG
- assert(Seen.insert(std::make_pair(GroupIDVal, BitmaskVal)).second &&
+ assert(Seen.insert(std::make_pair(GroupIDVal, BitPosVal)).second &&
"duplicated bitmask");
#endif
OS << " {"
<< "\"" << ExtName << "\""
- << ", " << GroupIDVal << ", " << BitmaskVal << "ULL"
+ << ", " << GroupIDVal << ", " << BitPosVal << "ULL"
<< "},\n";
}
OS << "};\n";
>From 7329954503fd81bcdbc0b0c5f49b84d1fbc11d6c Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 27 Jun 2024 05:48:30 -0700
Subject: [PATCH 27/27] Bitmask -> BitPos
---
llvm/test/TableGen/riscv-target-def.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
index 106ce57ecfdc4..8c7917acb2d36 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -14,7 +14,7 @@ class RISCVExtension<string name, int major, int minor, string desc,
class RISCVExtensionBitmask<bits<3> groupID, int bitmaskShift> {
int GroupID = groupID;
- int Bitmask = bitmaskShift;
+ int BitPos = bitmaskShift;
}
class RISCVExperimentalExtension<string name, int major, int minor, string desc,
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