[llvm] [X86][CodeGen] Support hoisting load/store with conditional faulting (PR #96720)

[Shengchen Kan via llvm-commits]

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@@ -32308,6 +32308,54 @@ bool X86TargetLowering::isInlineAsmTargetBranch(
   return Inst.equals_insensitive("call") || Inst.equals_insensitive("jmp");
 }
 
+static SDValue getFlagsOfCmpZeroFori1(SelectionDAG &DAG, const SDLoc &DL,
+                                      SDValue Mask) {
+  EVT Ty = MVT::i8;
+  auto V = DAG.getBitcast(MVT::i1, Mask);
+  auto VE = DAG.getZExtOrTrunc(V, DL, Ty);
+  auto Zero = DAG.getConstant(0, DL, Ty);
+  SDVTList X86SubVTs = DAG.getVTList(Ty, MVT::i32);
+  auto CmpZero = DAG.getNode(X86ISD::SUB, DL, X86SubVTs, Zero, VE);
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KanRobert wrote:

For machine CSE cases like `a ? -a: b;`, SUB will be transformed to TEST if possible, which can verified from test cf.ll

https://github.com/llvm/llvm-project/pull/96720