[llvm] [RegisterCoalescer] Fix issue in the RegisterCoalescer. (PR #96839)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,124 @@
+# RUN: llc -mtriple x86_64-unknown-unknown -x mir < %s \
+# RUN:   -verify-machineinstrs -enable-subreg-liveness=true \
+# RUN:   --run-pass=register-coalescer -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+  target triple = "x86_64-unknown-unknown"
+  
+  %pair = type { i64, double }
+  %t21 = type { ptr }
+  %t13 = type { ptr, %t15, %t15 }
+  %t15 = type { i8, i32, i32 }
+  
+  @__force_order = external hidden global i32, align 4
+  @.str = private unnamed_addr constant { [1 x i8], [63 x i8] } zeroinitializer, align 32
+  @a = external global i32, align 4
+  @fn1.g = private unnamed_addr constant [9 x ptr] [ptr null, ptr @a, ptr null, ptr null, ptr null, ptr null, ptr null, ptr null, ptr null], align 16
+  @e = external global i32, align 4
+  @__stack_chk_guard = external dso_local global ptr
+  
+  ; Function Attrs: nounwind ssp
+  define i32 @test1() #0 {
+  entry:
+    %tmp5.i = load volatile i32, ptr undef, align 4
+    %conv.i = zext i32 %tmp5.i to i64
+    %tmp12.i = load volatile i32, ptr undef, align 4
+    %conv13.i = zext i32 %tmp12.i to i64
+    %shl.i = shl i64 %conv13.i, 32
+    %or.i = or i64 %shl.i, %conv.i
+    %add16.i = add i64 %or.i, 256
+    %shr.i = lshr i64 %add16.i, 8
+    %conv19.i = trunc i64 %shr.i to i32
+    store volatile i32 %conv19.i, ptr undef, align 4
+    ret i32 undef
+  }
+...
+---
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arsenm wrote:

Should be able to drop the IR section, and most of the function flags 

https://github.com/llvm/llvm-project/pull/96839