[llvm] [AMDGPU] In instruction selector, allow copy from physical reg to s1 (PR #96157)

[Jun Wang via llvm-commits]

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@@ -131,6 +131,16 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
   Register SrcReg = Src.getReg();
 
   if (isVCC(DstReg, *MRI)) {
+    // In planned update of calling convention, i1 arguments/returns are
+    // assigned to SGPRs without promoting to i32. The following if statement
+    // allows insturctions such as "%0:sreg_64_xexec(s1) = COPY $sgpr4_sgpr5"
+    // to be accepted.
+    if (SrcReg.isPhysical() && SrcReg != AMDGPU::SCC) {
+      const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DstReg);
+      if (DstRC)
+        return DstRC->contains(SrcReg);
----------------
jwanggit86 wrote:

Once [96155](https://github.com/llvm/llvm-project/pull/96155) is committed, the reg banks for both src and dest of the above instruction would be set to VCCRegBank. So perhaps we could do something like this:
```C
RegisterBank *Bank = MRI->getRegBankOrNull(SrcReg);
if (Bank)
  return Bank == AMDGPU::VCCRegBank;
```


https://github.com/llvm/llvm-project/pull/96157