[llvm] 581fd2f - [RISCV][GISel] Support fptoi and itofp for Zfh. (#96707)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 26 09:53:41 PDT 2024
Author: Craig Topper
Date: 2024-06-26T09:53:37-07:00
New Revision: 581fd2fa573e39607ea164c0b4a8057baeb62c69
URL: https://github.com/llvm/llvm-project/commit/581fd2fa573e39607ea164c0b4a8057baeb62c69
DIFF: https://github.com/llvm/llvm-project/commit/581fd2fa573e39607ea164c0b4a8057baeb62c69.diff
LOG: [RISCV][GISel] Support fptoi and itofp for Zfh. (#96707)
Added:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
Modified:
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index f6761ce5c105e..4ce182809db13 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -423,16 +423,19 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
FConstantActions.legalFor({s16});
FConstantActions.lowerFor({s32, s64});
- getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
- .legalIf(all(typeInSet(0, {s32, sXLen}), typeIsScalarFPArith(1, ST)))
- .widenScalarToNextPow2(0)
- .clampScalar(0, s32, sXLen)
- .libcall();
+ auto &FPToIActions =
+ getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
+ .legalIf(all(typeInSet(0, {s32, sXLen}), typeIsScalarFPArith(1, ST)));
+ if (ST.hasStdExtZfh())
+ FPToIActions.legalFor({{s32, s16}, {sXLen, s16}});
+ FPToIActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen).libcall();
- getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
- .legalIf(all(typeIsScalarFPArith(0, ST), typeInSet(1, {s32, sXLen})))
- .widenScalarToNextPow2(1)
- .clampScalar(1, s32, sXLen);
+ auto &IToFPActions =
+ getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
+ .legalIf(all(typeIsScalarFPArith(0, ST), typeInSet(1, {s32, sXLen})));
+ if (ST.hasStdExtZfh())
+ IToFPActions.legalFor({{s16, s32}, {s16, sXLen}});
+ IToFPActions.widenScalarToNextPow2(1).clampScalar(1, s32, sXLen);
// FIXME: We can do custom inline expansion like SelectionDAG.
// FIXME: Legal with Zfa.
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv32.mir
new file mode 100644
index 0000000000000..13dac86ac1df6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv32.mir
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fptosi_s32_s16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s32_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[FCVT_W_H:%[0-9]+]]:gpr = nofpexcept FCVT_W_H [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_W_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:gprb(s32) = G_FPTOSI %0(s16)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s32_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[FCVT_WU_H:%[0-9]+]]:gpr = nofpexcept FCVT_WU_H [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:gprb(s32) = G_FPTOUI %0(s16)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir
new file mode 100644
index 0000000000000..11a3f47ea7f14
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir
@@ -0,0 +1,94 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fptosi_s32_s16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s32_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[FCVT_W_H:%[0-9]+]]:gpr = nofpexcept FCVT_W_H [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_W_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:gprb(s32) = G_FPTOSI %0(s16)
+ %2:gprb(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s32_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[FCVT_WU_H:%[0-9]+]]:gpr = nofpexcept FCVT_WU_H [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:gprb(s32) = G_FPTOUI %0(s16)
+ %2:gprb(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s64_s16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s64_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[FCVT_L_H:%[0-9]+]]:gpr = nofpexcept FCVT_L_H [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_L_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:gprb(s64) = G_FPTOSI %0(s16)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s64_s16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s64_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[FCVT_LU_H:%[0-9]+]]:gpr = nofpexcept FCVT_LU_H [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_LU_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:gprb(s64) = G_FPTOUI %0(s16)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv32.mir
new file mode 100644
index 0000000000000..fbcf124f9f468
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv32.mir
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: sitofp_s16_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s16_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[FCVT_H_W:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_W [[COPY]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_W]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:gprb(s32) = COPY $x10
+ %1:fprb(s16) = G_SITOFP %0(s32)
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s16_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s16_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[FCVT_H_WU:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_WU [[COPY]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_WU]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:gprb(s32) = COPY $x10
+ %1:fprb(s16) = G_UITOFP %0(s32)
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
new file mode 100644
index 0000000000000..1afb1d9be6a09
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
@@ -0,0 +1,94 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: sitofp_s64_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s64_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[FCVT_H_W:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_W [[COPY]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_W]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:gprb(s64) = COPY $x10
+ %1:gprb(s32) = G_TRUNC %0(s64)
+ %2:fprb(s16) = G_SITOFP %1(s32)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s64_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s64_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[FCVT_H_WU:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_WU [[COPY]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_WU]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:gprb(s64) = COPY $x10
+ %1:gprb(s32) = G_TRUNC %0(s64)
+ %2:fprb(s16) = G_UITOFP %1(s32)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: sitofp_s64_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s64_s64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[FCVT_H_L:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_L [[COPY]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_L]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:gprb(s64) = COPY $x10
+ %1:fprb(s16) = G_SITOFP %0(s64)
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s64_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s64_s64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[FCVT_H_LU:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_LU [[COPY]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_LU]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:gprb(s64) = COPY $x10
+ %1:fprb(s16) = G_UITOFP %0(s64)
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv32.mir
new file mode 100644
index 0000000000000..27e52feb1d9a3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv32.mir
@@ -0,0 +1,142 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+
+---
+name: fptoui_s1_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s1_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s1) = G_FPTOUI %0(s16)
+ %2:_(s32) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s8_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s8_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s8) = G_FPTOSI %0(s16)
+ %2:_(s32) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s8_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s8_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s8) = G_FPTOUI %0(s16)
+ %2:_(s32) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s16_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s16_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = G_FPTOSI %0(s16)
+ %2:_(s32) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s16_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s16_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = G_FPTOUI %0(s16)
+ %2:_(s32) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s32_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s32_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s32) = G_FPTOSI %0(s16)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s32_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s32) = G_FPTOUI %0(s16)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir
new file mode 100644
index 0000000000000..12a0d0e4c763c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir
@@ -0,0 +1,210 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+
+---
+name: fptosi_s1_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s1_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s1) = G_FPTOSI %0(s16)
+ %2:_(s64) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s1_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s1_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s1) = G_FPTOUI %0(s16)
+ %2:_(s64) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s8_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s8_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s8) = G_FPTOSI %0(s16)
+ %2:_(s64) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s8_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s8_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s8) = G_FPTOUI %0(s16)
+ %2:_(s64) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s16_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s16_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = G_FPTOSI %0(s16)
+ %2:_(s64) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s16_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s16_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = G_FPTOUI %0(s16)
+ %2:_(s64) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s32_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s32_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s32) = G_FPTOSI %0(s16)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s32_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s32) = G_FPTOUI %0(s16)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s64_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s64_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s64) = G_FPTOSI %0(s16)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s64_s16
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s64_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s64) = G_FPTOUI %0(s16)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv32.mir
new file mode 100644
index 0000000000000..f68902c715aff
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv32.mir
@@ -0,0 +1,185 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+
+---
+name: sitofp_s16_s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s16_s1
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s32) = COPY $x10
+ %0:_(s1) = G_TRUNC %1(s32)
+ %2:_(s16) = G_SITOFP %0(s1)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s16_s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s16_s1
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s32) = COPY $x10
+ %0:_(s1) = G_TRUNC %1(s32)
+ %2:_(s16) = G_UITOFP %0(s1)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: sitofp_s16_s8
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s16_s8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s32) = COPY $x10
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:_(s16) = G_SITOFP %0(s8)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s16_s8
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s16_s8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s32) = COPY $x10
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:_(s16) = G_UITOFP %0(s8)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: sitofp_s16_s16
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s16_s16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s32) = COPY $x10
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:_(s16) = G_SITOFP %0(s16)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s16_s16
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s16_s16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s32) = COPY $x10
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:_(s16) = G_UITOFP %0(s16)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: sitofp_s16_s32
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s16_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[COPY]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s32) = COPY $x10
+ %1:_(s16) = G_SITOFP %0(s32)
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s16_s32
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s16_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[COPY]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s32) = COPY $x10
+ %1:_(s16) = G_UITOFP %0(s32)
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir
new file mode 100644
index 0000000000000..797e79b69da5f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir
@@ -0,0 +1,238 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+
+---
+name: sitofp_s16_s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s16_s1
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s64) = COPY $x10
+ %0:_(s1) = G_TRUNC %1(s64)
+ %2:_(s16) = G_SITOFP %0(s1)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s16_s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s16_s1
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s64) = COPY $x10
+ %0:_(s1) = G_TRUNC %1(s64)
+ %2:_(s16) = G_UITOFP %0(s1)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: sitofp_s16_s8
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s16_s8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s64) = COPY $x10
+ %0:_(s8) = G_TRUNC %1(s64)
+ %2:_(s16) = G_SITOFP %0(s8)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s16_s8
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s16_s8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s64) = COPY $x10
+ %0:_(s8) = G_TRUNC %1(s64)
+ %2:_(s16) = G_UITOFP %0(s8)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: sitofp_s16_s16
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s16_s16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s64) = COPY $x10
+ %0:_(s16) = G_TRUNC %1(s64)
+ %2:_(s16) = G_SITOFP %0(s16)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s16_s16
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s16_s16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s64) = COPY $x10
+ %0:_(s16) = G_TRUNC %1(s64)
+ %2:_(s16) = G_UITOFP %0(s16)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: sitofp_s16_s32
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s16_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[TRUNC]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s64) = COPY $x10
+ %0:_(s32) = G_TRUNC %1(s64)
+ %2:_(s16) = G_SITOFP %0(s32)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s16_s32
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s16_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[TRUNC]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:_(s64) = COPY $x10
+ %0:_(s32) = G_TRUNC %1(s64)
+ %2:_(s16) = G_UITOFP %0(s32)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: sitofp_s16_s64
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s16_s64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[COPY]](s64)
+ ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s64) = COPY $x10
+ %1:_(s16) = G_SITOFP %0(s64)
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s16_s64
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s16_s64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[COPY]](s64)
+ ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s64) = COPY $x10
+ %1:_(s16) = G_UITOFP %0(s64)
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir
new file mode 100644
index 0000000000000..346dd28eb3778
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir
@@ -0,0 +1,47 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \
+# RUN: -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck %s
+
+---
+name: fptosi_s32_s16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s32_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s32) = G_FPTOSI %0(s16)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s32_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s32) = G_FPTOUI [[COPY]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s32) = G_FPTOUI %0(s16)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
new file mode 100644
index 0000000000000..37aefa3ecbf0c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \
+# RUN: -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck %s
+
+---
+name: fptosi_s32_s16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s32_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s16)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s32) = G_FPTOSI %0(s16)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s32_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s32) = G_FPTOUI [[COPY]](s16)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s32) = G_FPTOUI %0(s16)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s64_s16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptosi_s64_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s64) = G_FPTOSI [[COPY]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s64) = G_FPTOSI %0(s16)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s64_s16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fptoui_s64_s16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s64) = G_FPTOUI [[COPY]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s16) = COPY $f10_h
+ %1:_(s64) = G_FPTOUI %0(s16)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir
new file mode 100644
index 0000000000000..02e5a9a982ed0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir
@@ -0,0 +1,47 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \
+# RUN: -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck %s
+
+---
+name: sitofp_s16_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s16_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fprb(s16) = G_SITOFP [[COPY]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s32) = COPY $x10
+ %1:_(s16) = G_SITOFP %0(s32)
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s16_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s16_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fprb(s16) = G_UITOFP [[COPY]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s32) = COPY $x10
+ %1:_(s16) = G_UITOFP %0(s32)
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
new file mode 100644
index 0000000000000..10da1f8fc9fb3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \
+# RUN: -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck %s
+
+---
+name: sitofp_s16_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s16_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fprb(s16) = G_SITOFP [[TRUNC]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s64) = COPY $x10
+ %1:_(s32) = G_TRUNC %0(s64)
+ %2:_(s16) = G_SITOFP %1(s32)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s16_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s16_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fprb(s16) = G_UITOFP [[TRUNC]](s32)
+ ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s64) = COPY $x10
+ %1:_(s32) = G_TRUNC %0(s64)
+ %2:_(s16) = G_UITOFP %1(s32)
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: sitofp_s16_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sitofp_s16_s64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fprb(s16) = G_SITOFP [[COPY]](s64)
+ ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s64) = COPY $x10
+ %1:_(s16) = G_SITOFP %0(s64)
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: uitofp_s16_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: uitofp_s16_s64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fprb(s16) = G_UITOFP [[COPY]](s64)
+ ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s64) = COPY $x10
+ %1:_(s16) = G_UITOFP %0(s64)
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
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